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generic: ar8216: rename cpuport_cfg to port0_cfg in ar8327_platform_data
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8216_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8216_priv *priv);
67 void (*init_globals)(struct ar8216_priv *priv);
68 void (*init_port)(struct ar8216_priv *priv, int port);
69 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72 int (*atu_flush)(struct ar8216_priv *priv);
73 void (*vtu_flush)(struct ar8216_priv *priv);
74 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8216_priv {
81 struct switch_dev dev;
82 struct phy_device *phy;
83 u32 (*read)(struct ar8216_priv *priv, int reg);
84 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
85 const struct net_device_ops *ndo_old;
86 struct net_device_ops ndo;
87 struct mutex reg_mutex;
88 u8 chip_ver;
89 u8 chip_rev;
90 const struct ar8xxx_chip *chip;
91 bool initialized;
92 bool port4_phy;
93 char buf[2048];
94
95 bool init;
96 bool mii_lo_first;
97
98 struct mutex mib_lock;
99 struct delayed_work mib_work;
100 int mib_next_port;
101 u64 *mib_stats;
102
103 /* all fields below are cleared on reset */
104 bool vlan;
105 u16 vlan_id[AR8X16_MAX_VLANS];
106 u8 vlan_table[AR8X16_MAX_VLANS];
107 u8 vlan_tagged;
108 u16 pvid[AR8X16_MAX_PORTS];
109 };
110
111 #define MIB_DESC(_s , _o, _n) \
112 { \
113 .size = (_s), \
114 .offset = (_o), \
115 .name = (_n), \
116 }
117
118 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
119 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
120 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
121 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
122 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
123 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
124 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
125 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
126 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
127 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
128 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
129 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
130 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
131 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
132 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
133 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
134 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
135 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
136 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
137 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
138 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
139 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
140 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
141 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
142 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
143 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
144 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
145 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
146 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
147 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
148 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
149 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
150 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
151 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
152 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
153 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
154 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
155 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
156 };
157
158 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
159 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
160 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
161 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
162 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
163 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
164 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
165 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
166 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
167 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
168 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
169 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
170 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
172 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
173 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
174 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
175 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
176 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
177 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
178 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
179 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
180 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
181 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
182 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
183 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
184 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
185 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
186 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
188 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
189 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
190 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
191 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
192 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
193 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
194 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
195 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
196 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
197 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
198 };
199
200 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
201
202 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
203 {
204 return priv->chip->caps & AR8XXX_CAP_GIGE;
205 }
206
207 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
208 {
209 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
210 }
211
212 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
213 {
214 return priv->chip_ver == AR8XXX_VER_AR8216;
215 }
216
217 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
218 {
219 return priv->chip_ver == AR8XXX_VER_AR8236;
220 }
221
222 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
223 {
224 return priv->chip_ver == AR8XXX_VER_AR8316;
225 }
226
227 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
228 {
229 return priv->chip_ver == AR8XXX_VER_AR8327;
230 }
231
232 static inline void
233 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
234 {
235 regaddr >>= 1;
236 *r1 = regaddr & 0x1e;
237
238 regaddr >>= 5;
239 *r2 = regaddr & 0x7;
240
241 regaddr >>= 3;
242 *page = regaddr & 0x1ff;
243 }
244
245 static u32
246 ar8216_mii_read(struct ar8216_priv *priv, int reg)
247 {
248 struct phy_device *phy = priv->phy;
249 struct mii_bus *bus = phy->bus;
250 u16 r1, r2, page;
251 u16 lo, hi;
252
253 split_addr((u32) reg, &r1, &r2, &page);
254
255 mutex_lock(&bus->mdio_lock);
256
257 bus->write(bus, 0x18, 0, page);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo = bus->read(bus, 0x10 | r2, r1);
260 hi = bus->read(bus, 0x10 | r2, r1 + 1);
261
262 mutex_unlock(&bus->mdio_lock);
263
264 return (hi << 16) | lo;
265 }
266
267 static void
268 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
269 {
270 struct phy_device *phy = priv->phy;
271 struct mii_bus *bus = phy->bus;
272 u16 r1, r2, r3;
273 u16 lo, hi;
274
275 split_addr((u32) reg, &r1, &r2, &r3);
276 lo = val & 0xffff;
277 hi = (u16) (val >> 16);
278
279 mutex_lock(&bus->mdio_lock);
280
281 bus->write(bus, 0x18, 0, r3);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 if (priv->mii_lo_first) {
284 bus->write(bus, 0x10 | r2, r1, lo);
285 bus->write(bus, 0x10 | r2, r1 + 1, hi);
286 } else {
287 bus->write(bus, 0x10 | r2, r1 + 1, hi);
288 bus->write(bus, 0x10 | r2, r1, lo);
289 }
290
291 mutex_unlock(&bus->mdio_lock);
292 }
293
294 static void
295 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
296 u16 dbg_addr, u16 dbg_data)
297 {
298 struct mii_bus *bus = priv->phy->bus;
299
300 mutex_lock(&bus->mdio_lock);
301 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
302 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
303 mutex_unlock(&bus->mdio_lock);
304 }
305
306 static void
307 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
308 {
309 struct mii_bus *bus = priv->phy->bus;
310
311 mutex_lock(&bus->mdio_lock);
312 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
313 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
314 mutex_unlock(&bus->mdio_lock);
315 }
316
317 static u32
318 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
319 {
320 u32 v;
321
322 lockdep_assert_held(&priv->reg_mutex);
323
324 v = priv->read(priv, reg);
325 v &= ~mask;
326 v |= val;
327 priv->write(priv, reg, v);
328
329 return v;
330 }
331
332 static inline void
333 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
334 {
335 u32 v;
336
337 lockdep_assert_held(&priv->reg_mutex);
338
339 v = priv->read(priv, reg);
340 v |= val;
341 priv->write(priv, reg, v);
342 }
343
344 static int
345 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
346 unsigned timeout)
347 {
348 int i;
349
350 for (i = 0; i < timeout; i++) {
351 u32 t;
352
353 t = priv->read(priv, reg);
354 if ((t & mask) == val)
355 return 0;
356
357 usleep_range(1000, 2000);
358 }
359
360 return -ETIMEDOUT;
361 }
362
363 static int
364 ar8216_mib_op(struct ar8216_priv *priv, u32 op)
365 {
366 unsigned mib_func;
367 int ret;
368
369 lockdep_assert_held(&priv->mib_lock);
370
371 if (chip_is_ar8327(priv))
372 mib_func = AR8327_REG_MIB_FUNC;
373 else
374 mib_func = AR8216_REG_MIB_FUNC;
375
376 mutex_lock(&priv->reg_mutex);
377 /* Capture the hardware statistics for all ports */
378 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
379 mutex_unlock(&priv->reg_mutex);
380
381 /* Wait for the capturing to complete. */
382 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
383 if (ret)
384 goto out;
385
386 ret = 0;
387
388 out:
389 return ret;
390 }
391
392 static int
393 ar8216_mib_capture(struct ar8216_priv *priv)
394 {
395 return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
396 }
397
398 static int
399 ar8216_mib_flush(struct ar8216_priv *priv)
400 {
401 return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
402 }
403
404 static void
405 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
406 {
407 unsigned int base;
408 u64 *mib_stats;
409 int i;
410
411 WARN_ON(port >= priv->dev.ports);
412
413 lockdep_assert_held(&priv->mib_lock);
414
415 if (chip_is_ar8327(priv))
416 base = AR8327_REG_PORT_STATS_BASE(port);
417 else if (chip_is_ar8236(priv) ||
418 chip_is_ar8316(priv))
419 base = AR8236_REG_PORT_STATS_BASE(port);
420 else
421 base = AR8216_REG_PORT_STATS_BASE(port);
422
423 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
424 for (i = 0; i < priv->chip->num_mibs; i++) {
425 const struct ar8xxx_mib_desc *mib;
426 u64 t;
427
428 mib = &priv->chip->mib_decs[i];
429 t = priv->read(priv, base + mib->offset);
430 if (mib->size == 2) {
431 u64 hi;
432
433 hi = priv->read(priv, base + mib->offset + 4);
434 t |= hi << 32;
435 }
436
437 if (flush)
438 mib_stats[i] = 0;
439 else
440 mib_stats[i] += t;
441 }
442 }
443
444 static void
445 ar8216_read_port_link(struct ar8216_priv *priv, int port,
446 struct switch_port_link *link)
447 {
448 u32 status;
449 u32 speed;
450
451 memset(link, '\0', sizeof(*link));
452
453 status = priv->chip->read_port_status(priv, port);
454
455 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
456 if (link->aneg) {
457 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
458 if (!link->link)
459 return;
460 } else {
461 link->link = true;
462 }
463
464 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
465 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
466 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
467
468 speed = (status & AR8216_PORT_STATUS_SPEED) >>
469 AR8216_PORT_STATUS_SPEED_S;
470
471 switch (speed) {
472 case AR8216_PORT_SPEED_10M:
473 link->speed = SWITCH_PORT_SPEED_10;
474 break;
475 case AR8216_PORT_SPEED_100M:
476 link->speed = SWITCH_PORT_SPEED_100;
477 break;
478 case AR8216_PORT_SPEED_1000M:
479 link->speed = SWITCH_PORT_SPEED_1000;
480 break;
481 default:
482 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
483 break;
484 }
485 }
486
487 static struct sk_buff *
488 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
489 {
490 struct ar8216_priv *priv = dev->phy_ptr;
491 unsigned char *buf;
492
493 if (unlikely(!priv))
494 goto error;
495
496 if (!priv->vlan)
497 goto send;
498
499 if (unlikely(skb_headroom(skb) < 2)) {
500 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
501 goto error;
502 }
503
504 buf = skb_push(skb, 2);
505 buf[0] = 0x10;
506 buf[1] = 0x80;
507
508 send:
509 return skb;
510
511 error:
512 dev_kfree_skb_any(skb);
513 return NULL;
514 }
515
516 static void
517 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
518 {
519 struct ar8216_priv *priv;
520 unsigned char *buf;
521 int port, vlan;
522
523 priv = dev->phy_ptr;
524 if (!priv)
525 return;
526
527 /* don't strip the header if vlan mode is disabled */
528 if (!priv->vlan)
529 return;
530
531 /* strip header, get vlan id */
532 buf = skb->data;
533 skb_pull(skb, 2);
534
535 /* check for vlan header presence */
536 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
537 return;
538
539 port = buf[0] & 0xf;
540
541 /* no need to fix up packets coming from a tagged source */
542 if (priv->vlan_tagged & (1 << port))
543 return;
544
545 /* lookup port vid from local table, the switch passes an invalid vlan id */
546 vlan = priv->vlan_id[priv->pvid[port]];
547
548 buf[14 + 2] &= 0xf0;
549 buf[14 + 2] |= vlan >> 8;
550 buf[15 + 2] = vlan & 0xff;
551 }
552
553 static int
554 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
555 {
556 int timeout = 20;
557 u32 t = 0;
558
559 while (1) {
560 t = priv->read(priv, reg);
561 if ((t & mask) == val)
562 return 0;
563
564 if (timeout-- <= 0)
565 break;
566
567 udelay(10);
568 }
569
570 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
571 (unsigned int) reg, t, mask, val);
572 return -ETIMEDOUT;
573 }
574
575 static void
576 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
577 {
578 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
579 return;
580 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
581 val &= AR8216_VTUDATA_MEMBER;
582 val |= AR8216_VTUDATA_VALID;
583 priv->write(priv, AR8216_REG_VTU_DATA, val);
584 }
585 op |= AR8216_VTU_ACTIVE;
586 priv->write(priv, AR8216_REG_VTU, op);
587 }
588
589 static void
590 ar8216_vtu_flush(struct ar8216_priv *priv)
591 {
592 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
593 }
594
595 static void
596 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
597 {
598 u32 op;
599
600 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
601 ar8216_vtu_op(priv, op, port_mask);
602 }
603
604 static int
605 ar8216_atu_flush(struct ar8216_priv *priv)
606 {
607 int ret;
608
609 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
610 if (!ret)
611 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
612
613 return ret;
614 }
615
616 static u32
617 ar8216_read_port_status(struct ar8216_priv *priv, int port)
618 {
619 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
620 }
621
622 static void
623 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
624 u32 members, u32 pvid)
625 {
626 u32 header;
627
628 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
629 header = AR8216_PORT_CTRL_HEADER;
630 else
631 header = 0;
632
633 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
634 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
635 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
636 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
637 AR8216_PORT_CTRL_LEARN | header |
638 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
639 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
640
641 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
642 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
643 AR8216_PORT_VLAN_DEFAULT_ID,
644 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
645 (ingress << AR8216_PORT_VLAN_MODE_S) |
646 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
647 }
648
649 static int
650 ar8216_hw_init(struct ar8216_priv *priv)
651 {
652 return 0;
653 }
654
655 static void
656 ar8216_init_globals(struct ar8216_priv *priv)
657 {
658 /* standard atheros magic */
659 priv->write(priv, 0x38, 0xc000050e);
660
661 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
662 AR8216_GCTRL_MTU, 1518 + 8 + 2);
663 }
664
665 static void
666 ar8216_init_port(struct ar8216_priv *priv, int port)
667 {
668 /* Enable port learning and tx */
669 priv->write(priv, AR8216_REG_PORT_CTRL(port),
670 AR8216_PORT_CTRL_LEARN |
671 (4 << AR8216_PORT_CTRL_STATE_S));
672
673 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
674
675 if (port == AR8216_PORT_CPU) {
676 priv->write(priv, AR8216_REG_PORT_STATUS(port),
677 AR8216_PORT_STATUS_LINK_UP |
678 (ar8xxx_has_gige(priv) ?
679 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
680 AR8216_PORT_STATUS_TXMAC |
681 AR8216_PORT_STATUS_RXMAC |
682 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
683 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
684 AR8216_PORT_STATUS_DUPLEX);
685 } else {
686 priv->write(priv, AR8216_REG_PORT_STATUS(port),
687 AR8216_PORT_STATUS_LINK_AUTO);
688 }
689 }
690
691 static const struct ar8xxx_chip ar8216_chip = {
692 .caps = AR8XXX_CAP_MIB_COUNTERS,
693
694 .hw_init = ar8216_hw_init,
695 .init_globals = ar8216_init_globals,
696 .init_port = ar8216_init_port,
697 .setup_port = ar8216_setup_port,
698 .read_port_status = ar8216_read_port_status,
699 .atu_flush = ar8216_atu_flush,
700 .vtu_flush = ar8216_vtu_flush,
701 .vtu_load_vlan = ar8216_vtu_load_vlan,
702
703 .num_mibs = ARRAY_SIZE(ar8216_mibs),
704 .mib_decs = ar8216_mibs,
705 };
706
707 static void
708 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
709 u32 members, u32 pvid)
710 {
711 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
712 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
713 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
714 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
715 AR8216_PORT_CTRL_LEARN |
716 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
717 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
718
719 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
720 AR8236_PORT_VLAN_DEFAULT_ID,
721 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
722
723 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
724 AR8236_PORT_VLAN2_VLAN_MODE |
725 AR8236_PORT_VLAN2_MEMBER,
726 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
727 (members << AR8236_PORT_VLAN2_MEMBER_S));
728 }
729
730 static int
731 ar8236_hw_init(struct ar8216_priv *priv)
732 {
733 int i;
734 struct mii_bus *bus;
735
736 if (priv->initialized)
737 return 0;
738
739 /* Initialize the PHYs */
740 bus = priv->phy->bus;
741 for (i = 0; i < 5; i++) {
742 mdiobus_write(bus, i, MII_ADVERTISE,
743 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
744 ADVERTISE_PAUSE_ASYM);
745 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
746 }
747 msleep(1000);
748
749 priv->initialized = true;
750 return 0;
751 }
752
753 static void
754 ar8236_init_globals(struct ar8216_priv *priv)
755 {
756 /* enable jumbo frames */
757 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
758 AR8316_GCTRL_MTU, 9018 + 8 + 2);
759
760 /* Enable MIB counters */
761 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
762 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
763 AR8236_MIB_EN);
764 }
765
766 static const struct ar8xxx_chip ar8236_chip = {
767 .caps = AR8XXX_CAP_MIB_COUNTERS,
768 .hw_init = ar8236_hw_init,
769 .init_globals = ar8236_init_globals,
770 .init_port = ar8216_init_port,
771 .setup_port = ar8236_setup_port,
772 .read_port_status = ar8216_read_port_status,
773 .atu_flush = ar8216_atu_flush,
774 .vtu_flush = ar8216_vtu_flush,
775 .vtu_load_vlan = ar8216_vtu_load_vlan,
776
777 .num_mibs = ARRAY_SIZE(ar8236_mibs),
778 .mib_decs = ar8236_mibs,
779 };
780
781 static int
782 ar8316_hw_init(struct ar8216_priv *priv)
783 {
784 int i;
785 u32 val, newval;
786 struct mii_bus *bus;
787
788 val = priv->read(priv, 0x8);
789
790 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
791 if (priv->port4_phy) {
792 /* value taken from Ubiquiti RouterStation Pro */
793 newval = 0x81461bea;
794 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
795 } else {
796 newval = 0x01261be2;
797 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
798 }
799 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
800 /* value taken from AVM Fritz!Box 7390 sources */
801 newval = 0x010e5b71;
802 } else {
803 /* no known value for phy interface */
804 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
805 priv->phy->interface);
806 return -EINVAL;
807 }
808
809 if (val == newval)
810 goto out;
811
812 priv->write(priv, 0x8, newval);
813
814 /* Initialize the ports */
815 bus = priv->phy->bus;
816 for (i = 0; i < 5; i++) {
817 if ((i == 4) && priv->port4_phy &&
818 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
819 /* work around for phy4 rgmii mode */
820 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
821 /* rx delay */
822 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
823 /* tx delay */
824 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
825 msleep(1000);
826 }
827
828 /* initialize the port itself */
829 mdiobus_write(bus, i, MII_ADVERTISE,
830 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
831 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
832 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
833 msleep(1000);
834 }
835
836 out:
837 priv->initialized = true;
838 return 0;
839 }
840
841 static void
842 ar8316_init_globals(struct ar8216_priv *priv)
843 {
844 /* standard atheros magic */
845 priv->write(priv, 0x38, 0xc000050e);
846
847 /* enable cpu port to receive multicast and broadcast frames */
848 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
849
850 /* enable jumbo frames */
851 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
852 AR8316_GCTRL_MTU, 9018 + 8 + 2);
853
854 /* Enable MIB counters */
855 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
856 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
857 AR8236_MIB_EN);
858 }
859
860 static const struct ar8xxx_chip ar8316_chip = {
861 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
862 .hw_init = ar8316_hw_init,
863 .init_globals = ar8316_init_globals,
864 .init_port = ar8216_init_port,
865 .setup_port = ar8216_setup_port,
866 .read_port_status = ar8216_read_port_status,
867 .atu_flush = ar8216_atu_flush,
868 .vtu_flush = ar8216_vtu_flush,
869 .vtu_load_vlan = ar8216_vtu_load_vlan,
870
871 .num_mibs = ARRAY_SIZE(ar8236_mibs),
872 .mib_decs = ar8236_mibs,
873 };
874
875 static u32
876 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
877 {
878 u32 t;
879
880 if (!cfg)
881 return 0;
882
883 t = 0;
884 switch (cfg->mode) {
885 case AR8327_PAD_NC:
886 break;
887
888 case AR8327_PAD_MAC2MAC_MII:
889 t = AR8327_PAD_MAC_MII_EN;
890 if (cfg->rxclk_sel)
891 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
892 if (cfg->txclk_sel)
893 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
894 break;
895
896 case AR8327_PAD_MAC2MAC_GMII:
897 t = AR8327_PAD_MAC_GMII_EN;
898 if (cfg->rxclk_sel)
899 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
900 if (cfg->txclk_sel)
901 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
902 break;
903
904 case AR8327_PAD_MAC_SGMII:
905 t = AR8327_PAD_SGMII_EN;
906
907 /*
908 * WAR for the QUalcomm Atheros AP136 board.
909 * It seems that RGMII TX/RX delay settings needs to be
910 * applied for SGMII mode as well, The ethernet is not
911 * reliable without this.
912 */
913 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
914 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
915 if (cfg->rxclk_delay_en)
916 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
917 if (cfg->txclk_delay_en)
918 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
919
920 break;
921
922 case AR8327_PAD_MAC2PHY_MII:
923 t = AR8327_PAD_PHY_MII_EN;
924 if (cfg->rxclk_sel)
925 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
926 if (cfg->txclk_sel)
927 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
928 break;
929
930 case AR8327_PAD_MAC2PHY_GMII:
931 t = AR8327_PAD_PHY_GMII_EN;
932 if (cfg->pipe_rxclk_sel)
933 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
934 if (cfg->rxclk_sel)
935 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
936 if (cfg->txclk_sel)
937 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
938 break;
939
940 case AR8327_PAD_MAC_RGMII:
941 t = AR8327_PAD_RGMII_EN;
942 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
943 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
944 if (cfg->rxclk_delay_en)
945 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
946 if (cfg->txclk_delay_en)
947 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
948 break;
949
950 case AR8327_PAD_PHY_GMII:
951 t = AR8327_PAD_PHYX_GMII_EN;
952 break;
953
954 case AR8327_PAD_PHY_RGMII:
955 t = AR8327_PAD_PHYX_RGMII_EN;
956 break;
957
958 case AR8327_PAD_PHY_MII:
959 t = AR8327_PAD_PHYX_MII_EN;
960 break;
961 }
962
963 return t;
964 }
965
966 static void
967 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
968 {
969 switch (priv->chip_rev) {
970 case 1:
971 /* For 100M waveform */
972 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
973 /* Turn on Gigabit clock */
974 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
975 break;
976
977 case 2:
978 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
979 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
980 /* fallthrough */
981 case 4:
982 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
983 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
984
985 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
986 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
987 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
988 break;
989 }
990 }
991
992 static int
993 ar8327_hw_init(struct ar8216_priv *priv)
994 {
995 struct ar8327_platform_data *pdata;
996 struct ar8327_led_cfg *led_cfg;
997 struct mii_bus *bus;
998 u32 pos, new_pos;
999 u32 t;
1000 int i;
1001
1002 pdata = priv->phy->dev.platform_data;
1003 if (!pdata)
1004 return -EINVAL;
1005
1006 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1007 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1008 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1009 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1010 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1011 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1012
1013 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1014 new_pos = pos;
1015
1016 led_cfg = pdata->led_cfg;
1017 if (led_cfg) {
1018 if (led_cfg->open_drain)
1019 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1020 else
1021 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1022
1023 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1024 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1025 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1026 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1027 }
1028
1029 if (new_pos != pos) {
1030 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1031 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1032 }
1033
1034 bus = priv->phy->bus;
1035 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1036 ar8327_phy_fixup(priv, i);
1037
1038 /* start aneg on the PHY */
1039 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1040 ADVERTISE_PAUSE_CAP |
1041 ADVERTISE_PAUSE_ASYM);
1042 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1043 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1044 }
1045
1046 msleep(1000);
1047
1048 return 0;
1049 }
1050
1051 static void
1052 ar8327_init_globals(struct ar8216_priv *priv)
1053 {
1054 u32 t;
1055
1056 /* enable CPU port and disable mirror port */
1057 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1058 AR8327_FWD_CTRL0_MIRROR_PORT;
1059 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1060
1061 /* forward multicast and broadcast frames to CPU */
1062 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1063 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1064 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1065 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1066
1067 /* setup MTU */
1068 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1069 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1070
1071 /* Enable MIB counters */
1072 ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1073 AR8327_MODULE_EN_MIB);
1074 }
1075
1076 static void
1077 ar8327_init_cpuport(struct ar8216_priv *priv)
1078 {
1079 struct ar8327_platform_data *pdata;
1080 struct ar8327_port_cfg *cfg;
1081 u32 t;
1082
1083 pdata = priv->phy->dev.platform_data;
1084 if (!pdata)
1085 return;
1086
1087 cfg = &pdata->port0_cfg;
1088 if (!cfg->force_link) {
1089 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
1090 AR8216_PORT_STATUS_LINK_AUTO);
1091 return;
1092 }
1093
1094 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1095 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1096 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1097 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1098 switch (cfg->speed) {
1099 case AR8327_PORT_SPEED_10:
1100 t |= AR8216_PORT_SPEED_10M;
1101 break;
1102 case AR8327_PORT_SPEED_100:
1103 t |= AR8216_PORT_SPEED_100M;
1104 break;
1105 case AR8327_PORT_SPEED_1000:
1106 t |= AR8216_PORT_SPEED_1000M;
1107 break;
1108 }
1109
1110 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
1111 }
1112
1113 static void
1114 ar8327_init_port(struct ar8216_priv *priv, int port)
1115 {
1116 u32 t;
1117
1118 if (port == AR8216_PORT_CPU) {
1119 ar8327_init_cpuport(priv);
1120 } else {
1121 t = AR8216_PORT_STATUS_LINK_AUTO;
1122 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1123 }
1124
1125 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1126
1127 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
1128
1129 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1130 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1131
1132 t = AR8327_PORT_LOOKUP_LEARN;
1133 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1134 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1135 }
1136
1137 static u32
1138 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1139 {
1140 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1141 }
1142
1143 static int
1144 ar8327_atu_flush(struct ar8216_priv *priv)
1145 {
1146 int ret;
1147
1148 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1149 AR8327_ATU_FUNC_BUSY, 0);
1150 if (!ret)
1151 priv->write(priv, AR8327_REG_ATU_FUNC,
1152 AR8327_ATU_FUNC_OP_FLUSH);
1153
1154 return ret;
1155 }
1156
1157 static void
1158 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1159 {
1160 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1161 AR8327_VTU_FUNC1_BUSY, 0))
1162 return;
1163
1164 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1165 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1166
1167 op |= AR8327_VTU_FUNC1_BUSY;
1168 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1169 }
1170
1171 static void
1172 ar8327_vtu_flush(struct ar8216_priv *priv)
1173 {
1174 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1175 }
1176
1177 static void
1178 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1179 {
1180 u32 op;
1181 u32 val;
1182 int i;
1183
1184 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1185 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1186 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1187 u32 mode;
1188
1189 if ((port_mask & BIT(i)) == 0)
1190 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1191 else if (priv->vlan == 0)
1192 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1193 else if (priv->vlan_tagged & BIT(i))
1194 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1195 else
1196 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1197
1198 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1199 }
1200 ar8327_vtu_op(priv, op, val);
1201 }
1202
1203 static void
1204 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1205 u32 members, u32 pvid)
1206 {
1207 u32 t;
1208 u32 mode;
1209
1210 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1211 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1212 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1213
1214 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1215 switch (egress) {
1216 case AR8216_OUT_KEEP:
1217 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1218 break;
1219 case AR8216_OUT_STRIP_VLAN:
1220 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1221 break;
1222 case AR8216_OUT_ADD_VLAN:
1223 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1224 break;
1225 }
1226
1227 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1228 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1229 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1230
1231 t = members;
1232 t |= AR8327_PORT_LOOKUP_LEARN;
1233 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1234 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1235 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1236 }
1237
1238 static const struct ar8xxx_chip ar8327_chip = {
1239 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1240 .hw_init = ar8327_hw_init,
1241 .init_globals = ar8327_init_globals,
1242 .init_port = ar8327_init_port,
1243 .setup_port = ar8327_setup_port,
1244 .read_port_status = ar8327_read_port_status,
1245 .atu_flush = ar8327_atu_flush,
1246 .vtu_flush = ar8327_vtu_flush,
1247 .vtu_load_vlan = ar8327_vtu_load_vlan,
1248
1249 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1250 .mib_decs = ar8236_mibs,
1251 };
1252
1253 static int
1254 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1255 struct switch_val *val)
1256 {
1257 struct ar8216_priv *priv = to_ar8216(dev);
1258 priv->vlan = !!val->value.i;
1259 return 0;
1260 }
1261
1262 static int
1263 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1264 struct switch_val *val)
1265 {
1266 struct ar8216_priv *priv = to_ar8216(dev);
1267 val->value.i = priv->vlan;
1268 return 0;
1269 }
1270
1271
1272 static int
1273 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1274 {
1275 struct ar8216_priv *priv = to_ar8216(dev);
1276
1277 /* make sure no invalid PVIDs get set */
1278
1279 if (vlan >= dev->vlans)
1280 return -EINVAL;
1281
1282 priv->pvid[port] = vlan;
1283 return 0;
1284 }
1285
1286 static int
1287 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1288 {
1289 struct ar8216_priv *priv = to_ar8216(dev);
1290 *vlan = priv->pvid[port];
1291 return 0;
1292 }
1293
1294 static int
1295 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1296 struct switch_val *val)
1297 {
1298 struct ar8216_priv *priv = to_ar8216(dev);
1299 priv->vlan_id[val->port_vlan] = val->value.i;
1300 return 0;
1301 }
1302
1303 static int
1304 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1305 struct switch_val *val)
1306 {
1307 struct ar8216_priv *priv = to_ar8216(dev);
1308 val->value.i = priv->vlan_id[val->port_vlan];
1309 return 0;
1310 }
1311
1312 static int
1313 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1314 struct switch_port_link *link)
1315 {
1316 struct ar8216_priv *priv = to_ar8216(dev);
1317
1318 ar8216_read_port_link(priv, port, link);
1319 return 0;
1320 }
1321
1322 static int
1323 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1324 {
1325 struct ar8216_priv *priv = to_ar8216(dev);
1326 u8 ports = priv->vlan_table[val->port_vlan];
1327 int i;
1328
1329 val->len = 0;
1330 for (i = 0; i < dev->ports; i++) {
1331 struct switch_port *p;
1332
1333 if (!(ports & (1 << i)))
1334 continue;
1335
1336 p = &val->value.ports[val->len++];
1337 p->id = i;
1338 if (priv->vlan_tagged & (1 << i))
1339 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1340 else
1341 p->flags = 0;
1342 }
1343 return 0;
1344 }
1345
1346 static int
1347 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1348 {
1349 struct ar8216_priv *priv = to_ar8216(dev);
1350 u8 *vt = &priv->vlan_table[val->port_vlan];
1351 int i, j;
1352
1353 *vt = 0;
1354 for (i = 0; i < val->len; i++) {
1355 struct switch_port *p = &val->value.ports[i];
1356
1357 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1358 priv->vlan_tagged |= (1 << p->id);
1359 } else {
1360 priv->vlan_tagged &= ~(1 << p->id);
1361 priv->pvid[p->id] = val->port_vlan;
1362
1363 /* make sure that an untagged port does not
1364 * appear in other vlans */
1365 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1366 if (j == val->port_vlan)
1367 continue;
1368 priv->vlan_table[j] &= ~(1 << p->id);
1369 }
1370 }
1371
1372 *vt |= 1 << p->id;
1373 }
1374 return 0;
1375 }
1376
1377 static int
1378 ar8216_sw_hw_apply(struct switch_dev *dev)
1379 {
1380 struct ar8216_priv *priv = to_ar8216(dev);
1381 u8 portmask[AR8X16_MAX_PORTS];
1382 int i, j;
1383
1384 mutex_lock(&priv->reg_mutex);
1385 /* flush all vlan translation unit entries */
1386 priv->chip->vtu_flush(priv);
1387
1388 memset(portmask, 0, sizeof(portmask));
1389 if (!priv->init) {
1390 /* calculate the port destination masks and load vlans
1391 * into the vlan translation unit */
1392 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1393 u8 vp = priv->vlan_table[j];
1394
1395 if (!vp)
1396 continue;
1397
1398 for (i = 0; i < dev->ports; i++) {
1399 u8 mask = (1 << i);
1400 if (vp & mask)
1401 portmask[i] |= vp & ~mask;
1402 }
1403
1404 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1405 priv->vlan_table[j]);
1406 }
1407 } else {
1408 /* vlan disabled:
1409 * isolate all ports, but connect them to the cpu port */
1410 for (i = 0; i < dev->ports; i++) {
1411 if (i == AR8216_PORT_CPU)
1412 continue;
1413
1414 portmask[i] = 1 << AR8216_PORT_CPU;
1415 portmask[AR8216_PORT_CPU] |= (1 << i);
1416 }
1417 }
1418
1419 /* update the port destination mask registers and tag settings */
1420 for (i = 0; i < dev->ports; i++) {
1421 int egress, ingress;
1422 int pvid;
1423
1424 if (priv->vlan) {
1425 pvid = priv->vlan_id[priv->pvid[i]];
1426 if (priv->vlan_tagged & (1 << i))
1427 egress = AR8216_OUT_ADD_VLAN;
1428 else
1429 egress = AR8216_OUT_STRIP_VLAN;
1430 ingress = AR8216_IN_SECURE;
1431 } else {
1432 pvid = i;
1433 egress = AR8216_OUT_KEEP;
1434 ingress = AR8216_IN_PORT_ONLY;
1435 }
1436
1437 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1438 pvid);
1439 }
1440 mutex_unlock(&priv->reg_mutex);
1441 return 0;
1442 }
1443
1444 static int
1445 ar8216_sw_reset_switch(struct switch_dev *dev)
1446 {
1447 struct ar8216_priv *priv = to_ar8216(dev);
1448 int i;
1449
1450 mutex_lock(&priv->reg_mutex);
1451 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1452 offsetof(struct ar8216_priv, vlan));
1453
1454 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1455 priv->vlan_id[i] = i;
1456
1457 /* Configure all ports */
1458 for (i = 0; i < dev->ports; i++)
1459 priv->chip->init_port(priv, i);
1460
1461 priv->chip->init_globals(priv);
1462 mutex_unlock(&priv->reg_mutex);
1463
1464 return ar8216_sw_hw_apply(dev);
1465 }
1466
1467 static int
1468 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1469 const struct switch_attr *attr,
1470 struct switch_val *val)
1471 {
1472 struct ar8216_priv *priv = to_ar8216(dev);
1473 unsigned int len;
1474 int ret;
1475
1476 if (!ar8xxx_has_mib_counters(priv))
1477 return -EOPNOTSUPP;
1478
1479 mutex_lock(&priv->mib_lock);
1480
1481 len = priv->dev.ports * priv->chip->num_mibs *
1482 sizeof(*priv->mib_stats);
1483 memset(priv->mib_stats, '\0', len);
1484 ret = ar8216_mib_flush(priv);
1485 if (ret)
1486 goto unlock;
1487
1488 ret = 0;
1489
1490 unlock:
1491 mutex_unlock(&priv->mib_lock);
1492 return ret;
1493 }
1494
1495 static int
1496 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1497 const struct switch_attr *attr,
1498 struct switch_val *val)
1499 {
1500 struct ar8216_priv *priv = to_ar8216(dev);
1501 int port;
1502 int ret;
1503
1504 if (!ar8xxx_has_mib_counters(priv))
1505 return -EOPNOTSUPP;
1506
1507 port = val->port_vlan;
1508 if (port >= dev->ports)
1509 return -EINVAL;
1510
1511 mutex_lock(&priv->mib_lock);
1512 ret = ar8216_mib_capture(priv);
1513 if (ret)
1514 goto unlock;
1515
1516 ar8216_mib_fetch_port_stat(priv, port, true);
1517
1518 ret = 0;
1519
1520 unlock:
1521 mutex_unlock(&priv->mib_lock);
1522 return ret;
1523 }
1524
1525 static int
1526 ar8216_sw_get_port_mib(struct switch_dev *dev,
1527 const struct switch_attr *attr,
1528 struct switch_val *val)
1529 {
1530 struct ar8216_priv *priv = to_ar8216(dev);
1531 const struct ar8xxx_chip *chip = priv->chip;
1532 u64 *mib_stats;
1533 int port;
1534 int ret;
1535 char *buf = priv->buf;
1536 int i, len = 0;
1537
1538 if (!ar8xxx_has_mib_counters(priv))
1539 return -EOPNOTSUPP;
1540
1541 port = val->port_vlan;
1542 if (port >= dev->ports)
1543 return -EINVAL;
1544
1545 mutex_lock(&priv->mib_lock);
1546 ret = ar8216_mib_capture(priv);
1547 if (ret)
1548 goto unlock;
1549
1550 ar8216_mib_fetch_port_stat(priv, port, false);
1551
1552 len += snprintf(buf + len, sizeof(priv->buf) - len,
1553 "Port %d MIB counters\n",
1554 port);
1555
1556 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1557 for (i = 0; i < chip->num_mibs; i++)
1558 len += snprintf(buf + len, sizeof(priv->buf) - len,
1559 "%-12s: %llu\n",
1560 chip->mib_decs[i].name,
1561 mib_stats[i]);
1562
1563 val->value.s = buf;
1564 val->len = len;
1565
1566 ret = 0;
1567
1568 unlock:
1569 mutex_unlock(&priv->mib_lock);
1570 return ret;
1571 }
1572
1573 static struct switch_attr ar8216_globals[] = {
1574 {
1575 .type = SWITCH_TYPE_INT,
1576 .name = "enable_vlan",
1577 .description = "Enable VLAN mode",
1578 .set = ar8216_sw_set_vlan,
1579 .get = ar8216_sw_get_vlan,
1580 .max = 1
1581 },
1582 {
1583 .type = SWITCH_TYPE_NOVAL,
1584 .name = "reset_mibs",
1585 .description = "Reset all MIB counters",
1586 .set = ar8216_sw_set_reset_mibs,
1587 },
1588
1589 };
1590
1591 static struct switch_attr ar8216_port[] = {
1592 {
1593 .type = SWITCH_TYPE_NOVAL,
1594 .name = "reset_mib",
1595 .description = "Reset single port MIB counters",
1596 .set = ar8216_sw_set_port_reset_mib,
1597 },
1598 {
1599 .type = SWITCH_TYPE_STRING,
1600 .name = "mib",
1601 .description = "Get port's MIB counters",
1602 .set = NULL,
1603 .get = ar8216_sw_get_port_mib,
1604 },
1605 };
1606
1607 static struct switch_attr ar8216_vlan[] = {
1608 {
1609 .type = SWITCH_TYPE_INT,
1610 .name = "vid",
1611 .description = "VLAN ID (0-4094)",
1612 .set = ar8216_sw_set_vid,
1613 .get = ar8216_sw_get_vid,
1614 .max = 4094,
1615 },
1616 };
1617
1618 static const struct switch_dev_ops ar8216_sw_ops = {
1619 .attr_global = {
1620 .attr = ar8216_globals,
1621 .n_attr = ARRAY_SIZE(ar8216_globals),
1622 },
1623 .attr_port = {
1624 .attr = ar8216_port,
1625 .n_attr = ARRAY_SIZE(ar8216_port),
1626 },
1627 .attr_vlan = {
1628 .attr = ar8216_vlan,
1629 .n_attr = ARRAY_SIZE(ar8216_vlan),
1630 },
1631 .get_port_pvid = ar8216_sw_get_pvid,
1632 .set_port_pvid = ar8216_sw_set_pvid,
1633 .get_vlan_ports = ar8216_sw_get_ports,
1634 .set_vlan_ports = ar8216_sw_set_ports,
1635 .apply_config = ar8216_sw_hw_apply,
1636 .reset_switch = ar8216_sw_reset_switch,
1637 .get_port_link = ar8216_sw_get_port_link,
1638 };
1639
1640 static int
1641 ar8216_id_chip(struct ar8216_priv *priv)
1642 {
1643 u32 val;
1644 u16 id;
1645 int i;
1646
1647 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1648 if (val == ~0)
1649 return -ENODEV;
1650
1651 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1652 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1653 u16 t;
1654
1655 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1656 if (val == ~0)
1657 return -ENODEV;
1658
1659 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1660 if (t != id)
1661 return -ENODEV;
1662 }
1663
1664 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1665 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1666
1667 switch (priv->chip_ver) {
1668 case AR8XXX_VER_AR8216:
1669 priv->chip = &ar8216_chip;
1670 break;
1671 case AR8XXX_VER_AR8236:
1672 priv->chip = &ar8236_chip;
1673 break;
1674 case AR8XXX_VER_AR8316:
1675 priv->chip = &ar8316_chip;
1676 break;
1677 case AR8XXX_VER_AR8327:
1678 priv->mii_lo_first = true;
1679 priv->chip = &ar8327_chip;
1680 break;
1681 default:
1682 printk(KERN_DEBUG
1683 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1684 priv->chip_ver, priv->chip_rev,
1685 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1686 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1687
1688 return -ENODEV;
1689 }
1690
1691 return 0;
1692 }
1693
1694 static void
1695 ar8xxx_mib_work_func(struct work_struct *work)
1696 {
1697 struct ar8216_priv *priv;
1698 int err;
1699
1700 priv = container_of(work, struct ar8216_priv, mib_work.work);
1701
1702 mutex_lock(&priv->mib_lock);
1703
1704 err = ar8216_mib_capture(priv);
1705 if (err)
1706 goto next_port;
1707
1708 ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1709
1710 next_port:
1711 priv->mib_next_port++;
1712 if (priv->mib_next_port >= priv->dev.ports)
1713 priv->mib_next_port = 0;
1714
1715 mutex_unlock(&priv->mib_lock);
1716 schedule_delayed_work(&priv->mib_work,
1717 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1718 }
1719
1720 static int
1721 ar8xxx_mib_init(struct ar8216_priv *priv)
1722 {
1723 unsigned int len;
1724
1725 if (!ar8xxx_has_mib_counters(priv))
1726 return 0;
1727
1728 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1729
1730 len = priv->dev.ports * priv->chip->num_mibs *
1731 sizeof(*priv->mib_stats);
1732 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1733
1734 if (!priv->mib_stats)
1735 return -ENOMEM;
1736
1737 mutex_init(&priv->mib_lock);
1738 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1739
1740 return 0;
1741 }
1742
1743 static void
1744 ar8xxx_mib_start(struct ar8216_priv *priv)
1745 {
1746 if (!ar8xxx_has_mib_counters(priv))
1747 return;
1748
1749 schedule_delayed_work(&priv->mib_work,
1750 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1751 }
1752
1753 static void
1754 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1755 {
1756 if (!ar8xxx_has_mib_counters(priv))
1757 return;
1758
1759 cancel_delayed_work(&priv->mib_work);
1760 kfree(priv->mib_stats);
1761 }
1762
1763 static int
1764 ar8216_config_init(struct phy_device *pdev)
1765 {
1766 struct ar8216_priv *priv = pdev->priv;
1767 struct net_device *dev = pdev->attached_dev;
1768 struct switch_dev *swdev;
1769 int ret;
1770
1771 if (!priv) {
1772 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1773 if (priv == NULL)
1774 return -ENOMEM;
1775 }
1776
1777 priv->phy = pdev;
1778
1779 ret = ar8216_id_chip(priv);
1780 if (ret)
1781 goto err_free_priv;
1782
1783 if (pdev->addr != 0) {
1784 if (ar8xxx_has_gige(priv)) {
1785 pdev->supported |= SUPPORTED_1000baseT_Full;
1786 pdev->advertising |= ADVERTISED_1000baseT_Full;
1787 }
1788
1789 if (chip_is_ar8316(priv)) {
1790 /* check if we're attaching to the switch twice */
1791 pdev = pdev->bus->phy_map[0];
1792 if (!pdev) {
1793 kfree(priv);
1794 return 0;
1795 }
1796
1797 /* switch device has not been initialized, reuse priv */
1798 if (!pdev->priv) {
1799 priv->port4_phy = true;
1800 pdev->priv = priv;
1801 return 0;
1802 }
1803
1804 kfree(priv);
1805
1806 /* switch device has been initialized, reinit */
1807 priv = pdev->priv;
1808 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1809 priv->initialized = false;
1810 priv->port4_phy = true;
1811 ar8316_hw_init(priv);
1812 return 0;
1813 }
1814
1815 kfree(priv);
1816 return 0;
1817 }
1818
1819 if (ar8xxx_has_gige(priv))
1820 pdev->supported = SUPPORTED_1000baseT_Full;
1821 else
1822 pdev->supported = SUPPORTED_100baseT_Full;
1823 pdev->advertising = pdev->supported;
1824
1825 mutex_init(&priv->reg_mutex);
1826 priv->read = ar8216_mii_read;
1827 priv->write = ar8216_mii_write;
1828
1829 pdev->priv = priv;
1830
1831 swdev = &priv->dev;
1832 swdev->cpu_port = AR8216_PORT_CPU;
1833 swdev->ops = &ar8216_sw_ops;
1834 swdev->ports = AR8216_NUM_PORTS;
1835
1836 if (chip_is_ar8316(priv)) {
1837 swdev->name = "Atheros AR8316";
1838 swdev->vlans = AR8X16_MAX_VLANS;
1839
1840 if (priv->port4_phy) {
1841 /* port 5 connected to the other mac, therefore unusable */
1842 swdev->ports = (AR8216_NUM_PORTS - 1);
1843 }
1844 } else if (chip_is_ar8236(priv)) {
1845 swdev->name = "Atheros AR8236";
1846 swdev->vlans = AR8216_NUM_VLANS;
1847 swdev->ports = AR8216_NUM_PORTS;
1848 } else if (chip_is_ar8327(priv)) {
1849 swdev->name = "Atheros AR8327";
1850 swdev->vlans = AR8X16_MAX_VLANS;
1851 swdev->ports = AR8327_NUM_PORTS;
1852 } else {
1853 swdev->name = "Atheros AR8216";
1854 swdev->vlans = AR8216_NUM_VLANS;
1855 }
1856
1857 ret = ar8xxx_mib_init(priv);
1858 if (ret)
1859 goto err_free_priv;
1860
1861 ret = register_switch(&priv->dev, pdev->attached_dev);
1862 if (ret)
1863 goto err_cleanup_mib;
1864
1865 printk(KERN_INFO "%s: %s switch driver attached.\n",
1866 pdev->attached_dev->name, swdev->name);
1867
1868 priv->init = true;
1869
1870 ret = priv->chip->hw_init(priv);
1871 if (ret)
1872 goto err_cleanup_mib;
1873
1874 ret = ar8216_sw_reset_switch(&priv->dev);
1875 if (ret)
1876 goto err_cleanup_mib;
1877
1878 dev->phy_ptr = priv;
1879
1880 /* VID fixup only needed on ar8216 */
1881 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1882 dev->priv_flags |= IFF_NO_IP_ALIGN;
1883 dev->eth_mangle_rx = ar8216_mangle_rx;
1884 dev->eth_mangle_tx = ar8216_mangle_tx;
1885 }
1886
1887 priv->init = false;
1888
1889 ar8xxx_mib_start(priv);
1890
1891 return 0;
1892
1893 err_cleanup_mib:
1894 ar8xxx_mib_cleanup(priv);
1895 err_free_priv:
1896 kfree(priv);
1897 return ret;
1898 }
1899
1900 static int
1901 ar8216_read_status(struct phy_device *phydev)
1902 {
1903 struct ar8216_priv *priv = phydev->priv;
1904 struct switch_port_link link;
1905 int ret;
1906
1907 if (phydev->addr != 0)
1908 return genphy_read_status(phydev);
1909
1910 ar8216_read_port_link(priv, phydev->addr, &link);
1911 phydev->link = !!link.link;
1912 if (!phydev->link)
1913 return 0;
1914
1915 switch (link.speed) {
1916 case SWITCH_PORT_SPEED_10:
1917 phydev->speed = SPEED_10;
1918 break;
1919 case SWITCH_PORT_SPEED_100:
1920 phydev->speed = SPEED_100;
1921 break;
1922 case SWITCH_PORT_SPEED_1000:
1923 phydev->speed = SPEED_1000;
1924 break;
1925 default:
1926 phydev->speed = 0;
1927 }
1928 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1929
1930 /* flush the address translation unit */
1931 mutex_lock(&priv->reg_mutex);
1932 ret = priv->chip->atu_flush(priv);
1933 mutex_unlock(&priv->reg_mutex);
1934
1935 phydev->state = PHY_RUNNING;
1936 netif_carrier_on(phydev->attached_dev);
1937 phydev->adjust_link(phydev->attached_dev);
1938
1939 return ret;
1940 }
1941
1942 static int
1943 ar8216_config_aneg(struct phy_device *phydev)
1944 {
1945 if (phydev->addr == 0)
1946 return 0;
1947
1948 return genphy_config_aneg(phydev);
1949 }
1950
1951 static int
1952 ar8216_probe(struct phy_device *pdev)
1953 {
1954 struct ar8216_priv *priv;
1955 int ret;
1956
1957 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1958 if (priv == NULL)
1959 return -ENOMEM;
1960
1961 priv->phy = pdev;
1962
1963 ret = ar8216_id_chip(priv);
1964 kfree(priv);
1965
1966 return ret;
1967 }
1968
1969 static void
1970 ar8216_remove(struct phy_device *pdev)
1971 {
1972 struct ar8216_priv *priv = pdev->priv;
1973 struct net_device *dev = pdev->attached_dev;
1974
1975 if (!priv)
1976 return;
1977
1978 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1979 dev->eth_mangle_rx = NULL;
1980 dev->eth_mangle_tx = NULL;
1981
1982 if (pdev->addr == 0)
1983 unregister_switch(&priv->dev);
1984
1985 ar8xxx_mib_cleanup(priv);
1986 kfree(priv);
1987 }
1988
1989 static struct phy_driver ar8216_driver = {
1990 .phy_id = 0x004d0000,
1991 .name = "Atheros AR8216/AR8236/AR8316",
1992 .phy_id_mask = 0xffff0000,
1993 .features = PHY_BASIC_FEATURES,
1994 .probe = ar8216_probe,
1995 .remove = ar8216_remove,
1996 .config_init = &ar8216_config_init,
1997 .config_aneg = &ar8216_config_aneg,
1998 .read_status = &ar8216_read_status,
1999 .driver = { .owner = THIS_MODULE },
2000 };
2001
2002 int __init
2003 ar8216_init(void)
2004 {
2005 return phy_driver_register(&ar8216_driver);
2006 }
2007
2008 void __exit
2009 ar8216_exit(void)
2010 {
2011 phy_driver_unregister(&ar8216_driver);
2012 }
2013
2014 module_init(ar8216_init);
2015 module_exit(ar8216_exit);
2016 MODULE_LICENSE("GPL");
2017
OpenWrt SVN history