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generic: ar8216: add missing locking calls
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8216_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8216_priv *priv);
67 void (*init_globals)(struct ar8216_priv *priv);
68 void (*init_port)(struct ar8216_priv *priv, int port);
69 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72 int (*atu_flush)(struct ar8216_priv *priv);
73 void (*vtu_flush)(struct ar8216_priv *priv);
74 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8216_priv {
81 struct switch_dev dev;
82 struct phy_device *phy;
83 u32 (*read)(struct ar8216_priv *priv, int reg);
84 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
85 const struct net_device_ops *ndo_old;
86 struct net_device_ops ndo;
87 struct mutex reg_mutex;
88 u8 chip_ver;
89 u8 chip_rev;
90 const struct ar8xxx_chip *chip;
91 bool initialized;
92 bool port4_phy;
93 char buf[2048];
94
95 bool init;
96 bool mii_lo_first;
97
98 struct mutex mib_lock;
99 struct delayed_work mib_work;
100 int mib_next_port;
101 u64 *mib_stats;
102
103 /* all fields below are cleared on reset */
104 bool vlan;
105 u16 vlan_id[AR8X16_MAX_VLANS];
106 u8 vlan_table[AR8X16_MAX_VLANS];
107 u8 vlan_tagged;
108 u16 pvid[AR8X16_MAX_PORTS];
109 };
110
111 #define MIB_DESC(_s , _o, _n) \
112 { \
113 .size = (_s), \
114 .offset = (_o), \
115 .name = (_n), \
116 }
117
118 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
119 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
120 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
121 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
122 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
123 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
124 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
125 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
126 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
127 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
128 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
129 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
130 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
131 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
132 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
133 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
134 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
135 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
136 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
137 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
138 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
139 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
140 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
141 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
142 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
143 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
144 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
145 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
146 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
147 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
148 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
149 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
150 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
151 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
152 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
153 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
154 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
155 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
156 };
157
158 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
159 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
160 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
161 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
162 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
163 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
164 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
165 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
166 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
167 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
168 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
169 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
170 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
172 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
173 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
174 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
175 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
176 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
177 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
178 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
179 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
180 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
181 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
182 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
183 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
184 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
185 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
186 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
188 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
189 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
190 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
191 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
192 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
193 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
194 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
195 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
196 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
197 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
198 };
199
200 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
201
202 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
203 {
204 return priv->chip->caps & AR8XXX_CAP_GIGE;
205 }
206
207 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
208 {
209 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
210 }
211
212 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
213 {
214 return priv->chip_ver == AR8XXX_VER_AR8216;
215 }
216
217 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
218 {
219 return priv->chip_ver == AR8XXX_VER_AR8236;
220 }
221
222 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
223 {
224 return priv->chip_ver == AR8XXX_VER_AR8316;
225 }
226
227 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
228 {
229 return priv->chip_ver == AR8XXX_VER_AR8327;
230 }
231
232 static inline void
233 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
234 {
235 regaddr >>= 1;
236 *r1 = regaddr & 0x1e;
237
238 regaddr >>= 5;
239 *r2 = regaddr & 0x7;
240
241 regaddr >>= 3;
242 *page = regaddr & 0x1ff;
243 }
244
245 static u32
246 ar8216_mii_read(struct ar8216_priv *priv, int reg)
247 {
248 struct phy_device *phy = priv->phy;
249 struct mii_bus *bus = phy->bus;
250 u16 r1, r2, page;
251 u16 lo, hi;
252
253 split_addr((u32) reg, &r1, &r2, &page);
254
255 mutex_lock(&bus->mdio_lock);
256
257 bus->write(bus, 0x18, 0, page);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo = bus->read(bus, 0x10 | r2, r1);
260 hi = bus->read(bus, 0x10 | r2, r1 + 1);
261
262 mutex_unlock(&bus->mdio_lock);
263
264 return (hi << 16) | lo;
265 }
266
267 static void
268 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
269 {
270 struct phy_device *phy = priv->phy;
271 struct mii_bus *bus = phy->bus;
272 u16 r1, r2, r3;
273 u16 lo, hi;
274
275 split_addr((u32) reg, &r1, &r2, &r3);
276 lo = val & 0xffff;
277 hi = (u16) (val >> 16);
278
279 mutex_lock(&bus->mdio_lock);
280
281 bus->write(bus, 0x18, 0, r3);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 if (priv->mii_lo_first) {
284 bus->write(bus, 0x10 | r2, r1, lo);
285 bus->write(bus, 0x10 | r2, r1 + 1, hi);
286 } else {
287 bus->write(bus, 0x10 | r2, r1 + 1, hi);
288 bus->write(bus, 0x10 | r2, r1, lo);
289 }
290
291 mutex_unlock(&bus->mdio_lock);
292 }
293
294 static void
295 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
296 u16 dbg_addr, u16 dbg_data)
297 {
298 struct mii_bus *bus = priv->phy->bus;
299
300 mutex_lock(&bus->mdio_lock);
301 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
302 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
303 mutex_unlock(&bus->mdio_lock);
304 }
305
306 static void
307 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
308 {
309 struct mii_bus *bus = priv->phy->bus;
310
311 mutex_lock(&bus->mdio_lock);
312 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
313 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
314 mutex_unlock(&bus->mdio_lock);
315 }
316
317 static u32
318 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
319 {
320 u32 v;
321
322 lockdep_assert_held(&priv->reg_mutex);
323
324 v = priv->read(priv, reg);
325 v &= ~mask;
326 v |= val;
327 priv->write(priv, reg, v);
328
329 return v;
330 }
331
332 static inline void
333 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
334 {
335 u32 v;
336
337 lockdep_assert_held(&priv->reg_mutex);
338
339 v = priv->read(priv, reg);
340 v |= val;
341 priv->write(priv, reg, v);
342 }
343
344 static int
345 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
346 unsigned timeout)
347 {
348 int i;
349
350 for (i = 0; i < timeout; i++) {
351 u32 t;
352
353 t = priv->read(priv, reg);
354 if ((t & mask) == val)
355 return 0;
356
357 usleep_range(1000, 2000);
358 }
359
360 return -ETIMEDOUT;
361 }
362
363 static int
364 ar8216_mib_capture(struct ar8216_priv *priv)
365 {
366 unsigned mib_func;
367 int ret;
368
369 lockdep_assert_held(&priv->mib_lock);
370
371 if (chip_is_ar8327(priv))
372 mib_func = AR8327_REG_MIB_FUNC;
373 else
374 mib_func = AR8216_REG_MIB_FUNC;
375
376 mutex_lock(&priv->reg_mutex);
377 /* Capture the hardware statistics for all ports */
378 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
379 (AR8216_MIB_FUNC_CAPTURE << AR8216_MIB_FUNC_S));
380 mutex_unlock(&priv->reg_mutex);
381
382 /* Wait for the capturing to complete. */
383 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
384 if (ret)
385 goto out;
386
387 ret = 0;
388
389 out:
390 return ret;
391 }
392
393 static int
394 ar8216_mib_flush(struct ar8216_priv *priv)
395 {
396 unsigned mib_func;
397 int ret;
398
399 lockdep_assert_held(&priv->mib_lock);
400
401 if (chip_is_ar8327(priv))
402 mib_func = AR8327_REG_MIB_FUNC;
403 else
404 mib_func = AR8216_REG_MIB_FUNC;
405
406 /* Flush hardware statistics for all ports */
407 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
408 (AR8216_MIB_FUNC_FLUSH << AR8216_MIB_FUNC_S));
409
410 /* Wait for the capturing to complete. */
411 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
412 if (ret)
413 goto out;
414
415 ret = 0;
416
417 out:
418 return ret;
419 }
420
421 static void
422 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
423 {
424 unsigned int base;
425 u64 *mib_stats;
426 int i;
427
428 lockdep_assert_held(&priv->mib_lock);
429
430 if (chip_is_ar8327(priv))
431 base = AR8327_REG_PORT_STATS_BASE(port);
432 else if (chip_is_ar8236(priv) ||
433 chip_is_ar8316(priv))
434 base = AR8236_REG_PORT_STATS_BASE(port);
435 else
436 base = AR8216_REG_PORT_STATS_BASE(port);
437
438 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
439 for (i = 0; i < priv->chip->num_mibs; i++) {
440 const struct ar8xxx_mib_desc *mib;
441 u64 t;
442
443 mib = &priv->chip->mib_decs[i];
444 t = priv->read(priv, base + mib->offset);
445 if (mib->size == 2) {
446 u64 hi;
447
448 hi = priv->read(priv, base + mib->offset + 4);
449 t |= hi << 32;
450 }
451
452 if (flush)
453 mib_stats[i] = 0;
454 else
455 mib_stats[i] += t;
456 }
457 }
458
459 static void
460 ar8216_read_port_link(struct ar8216_priv *priv, int port,
461 struct switch_port_link *link)
462 {
463 u32 status;
464 u32 speed;
465
466 memset(link, '\0', sizeof(*link));
467
468 status = priv->chip->read_port_status(priv, port);
469
470 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
471 if (link->aneg) {
472 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
473 if (!link->link)
474 return;
475 } else {
476 link->link = true;
477 }
478
479 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
480 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
481 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
482
483 speed = (status & AR8216_PORT_STATUS_SPEED) >>
484 AR8216_PORT_STATUS_SPEED_S;
485
486 switch (speed) {
487 case AR8216_PORT_SPEED_10M:
488 link->speed = SWITCH_PORT_SPEED_10;
489 break;
490 case AR8216_PORT_SPEED_100M:
491 link->speed = SWITCH_PORT_SPEED_100;
492 break;
493 case AR8216_PORT_SPEED_1000M:
494 link->speed = SWITCH_PORT_SPEED_1000;
495 break;
496 default:
497 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
498 break;
499 }
500 }
501
502 static struct sk_buff *
503 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
504 {
505 struct ar8216_priv *priv = dev->phy_ptr;
506 unsigned char *buf;
507
508 if (unlikely(!priv))
509 goto error;
510
511 if (!priv->vlan)
512 goto send;
513
514 if (unlikely(skb_headroom(skb) < 2)) {
515 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
516 goto error;
517 }
518
519 buf = skb_push(skb, 2);
520 buf[0] = 0x10;
521 buf[1] = 0x80;
522
523 send:
524 return skb;
525
526 error:
527 dev_kfree_skb_any(skb);
528 return NULL;
529 }
530
531 static void
532 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
533 {
534 struct ar8216_priv *priv;
535 unsigned char *buf;
536 int port, vlan;
537
538 priv = dev->phy_ptr;
539 if (!priv)
540 return;
541
542 /* don't strip the header if vlan mode is disabled */
543 if (!priv->vlan)
544 return;
545
546 /* strip header, get vlan id */
547 buf = skb->data;
548 skb_pull(skb, 2);
549
550 /* check for vlan header presence */
551 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
552 return;
553
554 port = buf[0] & 0xf;
555
556 /* no need to fix up packets coming from a tagged source */
557 if (priv->vlan_tagged & (1 << port))
558 return;
559
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan = priv->vlan_id[priv->pvid[port]];
562
563 buf[14 + 2] &= 0xf0;
564 buf[14 + 2] |= vlan >> 8;
565 buf[15 + 2] = vlan & 0xff;
566 }
567
568 static int
569 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
570 {
571 int timeout = 20;
572 u32 t = 0;
573
574 while (1) {
575 t = priv->read(priv, reg);
576 if ((t & mask) == val)
577 return 0;
578
579 if (timeout-- <= 0)
580 break;
581
582 udelay(10);
583 }
584
585 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
586 (unsigned int) reg, t, mask, val);
587 return -ETIMEDOUT;
588 }
589
590 static void
591 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
592 {
593 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
594 return;
595 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
596 val &= AR8216_VTUDATA_MEMBER;
597 val |= AR8216_VTUDATA_VALID;
598 priv->write(priv, AR8216_REG_VTU_DATA, val);
599 }
600 op |= AR8216_VTU_ACTIVE;
601 priv->write(priv, AR8216_REG_VTU, op);
602 }
603
604 static void
605 ar8216_vtu_flush(struct ar8216_priv *priv)
606 {
607 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
608 }
609
610 static void
611 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
612 {
613 u32 op;
614
615 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
616 ar8216_vtu_op(priv, op, port_mask);
617 }
618
619 static int
620 ar8216_atu_flush(struct ar8216_priv *priv)
621 {
622 int ret;
623
624 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
625 if (!ret)
626 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
627
628 return ret;
629 }
630
631 static u32
632 ar8216_read_port_status(struct ar8216_priv *priv, int port)
633 {
634 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
635 }
636
637 static void
638 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
639 u32 members, u32 pvid)
640 {
641 u32 header;
642
643 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
644 header = AR8216_PORT_CTRL_HEADER;
645 else
646 header = 0;
647
648 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
649 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
650 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
651 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
652 AR8216_PORT_CTRL_LEARN | header |
653 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
654 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
655
656 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
657 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
658 AR8216_PORT_VLAN_DEFAULT_ID,
659 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
660 (ingress << AR8216_PORT_VLAN_MODE_S) |
661 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
662 }
663
664 static int
665 ar8216_hw_init(struct ar8216_priv *priv)
666 {
667 return 0;
668 }
669
670 static void
671 ar8216_init_globals(struct ar8216_priv *priv)
672 {
673 /* standard atheros magic */
674 priv->write(priv, 0x38, 0xc000050e);
675
676 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
677 AR8216_GCTRL_MTU, 1518 + 8 + 2);
678 }
679
680 static void
681 ar8216_init_port(struct ar8216_priv *priv, int port)
682 {
683 /* Enable port learning and tx */
684 priv->write(priv, AR8216_REG_PORT_CTRL(port),
685 AR8216_PORT_CTRL_LEARN |
686 (4 << AR8216_PORT_CTRL_STATE_S));
687
688 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
689
690 if (port == AR8216_PORT_CPU) {
691 priv->write(priv, AR8216_REG_PORT_STATUS(port),
692 AR8216_PORT_STATUS_LINK_UP |
693 (ar8xxx_has_gige(priv) ?
694 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
695 AR8216_PORT_STATUS_TXMAC |
696 AR8216_PORT_STATUS_RXMAC |
697 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
698 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
699 AR8216_PORT_STATUS_DUPLEX);
700 } else {
701 priv->write(priv, AR8216_REG_PORT_STATUS(port),
702 AR8216_PORT_STATUS_LINK_AUTO);
703 }
704 }
705
706 static const struct ar8xxx_chip ar8216_chip = {
707 .caps = AR8XXX_CAP_MIB_COUNTERS,
708
709 .hw_init = ar8216_hw_init,
710 .init_globals = ar8216_init_globals,
711 .init_port = ar8216_init_port,
712 .setup_port = ar8216_setup_port,
713 .read_port_status = ar8216_read_port_status,
714 .atu_flush = ar8216_atu_flush,
715 .vtu_flush = ar8216_vtu_flush,
716 .vtu_load_vlan = ar8216_vtu_load_vlan,
717
718 .num_mibs = ARRAY_SIZE(ar8216_mibs),
719 .mib_decs = ar8216_mibs,
720 };
721
722 static void
723 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
724 u32 members, u32 pvid)
725 {
726 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
727 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
728 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
729 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
730 AR8216_PORT_CTRL_LEARN |
731 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
732 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
733
734 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
735 AR8236_PORT_VLAN_DEFAULT_ID,
736 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
737
738 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
739 AR8236_PORT_VLAN2_VLAN_MODE |
740 AR8236_PORT_VLAN2_MEMBER,
741 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
742 (members << AR8236_PORT_VLAN2_MEMBER_S));
743 }
744
745 static int
746 ar8236_hw_init(struct ar8216_priv *priv)
747 {
748 int i;
749 struct mii_bus *bus;
750
751 if (priv->initialized)
752 return 0;
753
754 /* Initialize the PHYs */
755 bus = priv->phy->bus;
756 for (i = 0; i < 5; i++) {
757 mdiobus_write(bus, i, MII_ADVERTISE,
758 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
759 ADVERTISE_PAUSE_ASYM);
760 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
761 }
762 msleep(1000);
763
764 priv->initialized = true;
765 return 0;
766 }
767
768 static void
769 ar8236_init_globals(struct ar8216_priv *priv)
770 {
771 /* enable jumbo frames */
772 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
773 AR8316_GCTRL_MTU, 9018 + 8 + 2);
774
775 /* Enable MIB counters */
776 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
777 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
778 AR8236_MIB_EN);
779 }
780
781 static const struct ar8xxx_chip ar8236_chip = {
782 .caps = AR8XXX_CAP_MIB_COUNTERS,
783 .hw_init = ar8236_hw_init,
784 .init_globals = ar8236_init_globals,
785 .init_port = ar8216_init_port,
786 .setup_port = ar8236_setup_port,
787 .read_port_status = ar8216_read_port_status,
788 .atu_flush = ar8216_atu_flush,
789 .vtu_flush = ar8216_vtu_flush,
790 .vtu_load_vlan = ar8216_vtu_load_vlan,
791
792 .num_mibs = ARRAY_SIZE(ar8236_mibs),
793 .mib_decs = ar8236_mibs,
794 };
795
796 static int
797 ar8316_hw_init(struct ar8216_priv *priv)
798 {
799 int i;
800 u32 val, newval;
801 struct mii_bus *bus;
802
803 val = priv->read(priv, 0x8);
804
805 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
806 if (priv->port4_phy) {
807 /* value taken from Ubiquiti RouterStation Pro */
808 newval = 0x81461bea;
809 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
810 } else {
811 newval = 0x01261be2;
812 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
813 }
814 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
815 /* value taken from AVM Fritz!Box 7390 sources */
816 newval = 0x010e5b71;
817 } else {
818 /* no known value for phy interface */
819 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
820 priv->phy->interface);
821 return -EINVAL;
822 }
823
824 if (val == newval)
825 goto out;
826
827 priv->write(priv, 0x8, newval);
828
829 /* Initialize the ports */
830 bus = priv->phy->bus;
831 for (i = 0; i < 5; i++) {
832 if ((i == 4) && priv->port4_phy &&
833 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
834 /* work around for phy4 rgmii mode */
835 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
836 /* rx delay */
837 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
838 /* tx delay */
839 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
840 msleep(1000);
841 }
842
843 /* initialize the port itself */
844 mdiobus_write(bus, i, MII_ADVERTISE,
845 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
846 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
847 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
848 msleep(1000);
849 }
850
851 out:
852 priv->initialized = true;
853 return 0;
854 }
855
856 static void
857 ar8316_init_globals(struct ar8216_priv *priv)
858 {
859 /* standard atheros magic */
860 priv->write(priv, 0x38, 0xc000050e);
861
862 /* enable cpu port to receive multicast and broadcast frames */
863 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
864
865 /* enable jumbo frames */
866 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
867 AR8316_GCTRL_MTU, 9018 + 8 + 2);
868
869 /* Enable MIB counters */
870 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
871 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
872 AR8236_MIB_EN);
873 }
874
875 static const struct ar8xxx_chip ar8316_chip = {
876 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
877 .hw_init = ar8316_hw_init,
878 .init_globals = ar8316_init_globals,
879 .init_port = ar8216_init_port,
880 .setup_port = ar8216_setup_port,
881 .read_port_status = ar8216_read_port_status,
882 .atu_flush = ar8216_atu_flush,
883 .vtu_flush = ar8216_vtu_flush,
884 .vtu_load_vlan = ar8216_vtu_load_vlan,
885
886 .num_mibs = ARRAY_SIZE(ar8236_mibs),
887 .mib_decs = ar8236_mibs,
888 };
889
890 static u32
891 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
892 {
893 u32 t;
894
895 if (!cfg)
896 return 0;
897
898 t = 0;
899 switch (cfg->mode) {
900 case AR8327_PAD_NC:
901 break;
902
903 case AR8327_PAD_MAC2MAC_MII:
904 t = AR8327_PAD_MAC_MII_EN;
905 if (cfg->rxclk_sel)
906 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
907 if (cfg->txclk_sel)
908 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
909 break;
910
911 case AR8327_PAD_MAC2MAC_GMII:
912 t = AR8327_PAD_MAC_GMII_EN;
913 if (cfg->rxclk_sel)
914 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
915 if (cfg->txclk_sel)
916 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
917 break;
918
919 case AR8327_PAD_MAC_SGMII:
920 t = AR8327_PAD_SGMII_EN;
921 break;
922
923 case AR8327_PAD_MAC2PHY_MII:
924 t = AR8327_PAD_PHY_MII_EN;
925 if (cfg->rxclk_sel)
926 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
927 if (cfg->txclk_sel)
928 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
929 break;
930
931 case AR8327_PAD_MAC2PHY_GMII:
932 t = AR8327_PAD_PHY_GMII_EN;
933 if (cfg->pipe_rxclk_sel)
934 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
935 if (cfg->rxclk_sel)
936 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
937 if (cfg->txclk_sel)
938 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
939 break;
940
941 case AR8327_PAD_MAC_RGMII:
942 t = AR8327_PAD_RGMII_EN;
943 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
944 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
945 if (cfg->rxclk_delay_en)
946 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
947 if (cfg->txclk_delay_en)
948 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
949 break;
950
951 case AR8327_PAD_PHY_GMII:
952 t = AR8327_PAD_PHYX_GMII_EN;
953 break;
954
955 case AR8327_PAD_PHY_RGMII:
956 t = AR8327_PAD_PHYX_RGMII_EN;
957 break;
958
959 case AR8327_PAD_PHY_MII:
960 t = AR8327_PAD_PHYX_MII_EN;
961 break;
962 }
963
964 return t;
965 }
966
967 static void
968 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
969 {
970 switch (priv->chip_rev) {
971 case 1:
972 /* For 100M waveform */
973 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
974 /* Turn on Gigabit clock */
975 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
976 break;
977
978 case 2:
979 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
980 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
981 /* fallthrough */
982 case 4:
983 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
984 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
985
986 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
987 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
988 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
989 break;
990 }
991 }
992
993 static int
994 ar8327_hw_init(struct ar8216_priv *priv)
995 {
996 struct ar8327_platform_data *pdata;
997 struct ar8327_led_cfg *led_cfg;
998 struct mii_bus *bus;
999 u32 pos, new_pos;
1000 u32 t;
1001 int i;
1002
1003 pdata = priv->phy->dev.platform_data;
1004 if (!pdata)
1005 return -EINVAL;
1006
1007 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1008 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1009 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1010 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1011 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1012 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1013
1014 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1015 new_pos = pos;
1016
1017 led_cfg = pdata->led_cfg;
1018 if (led_cfg) {
1019 if (led_cfg->open_drain)
1020 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1021 else
1022 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1023
1024 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1025 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1026 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1027 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1028 }
1029
1030 if (new_pos != pos) {
1031 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1032 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1033 }
1034
1035 bus = priv->phy->bus;
1036 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1037 ar8327_phy_fixup(priv, i);
1038
1039 /* start aneg on the PHY */
1040 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1041 ADVERTISE_PAUSE_CAP |
1042 ADVERTISE_PAUSE_ASYM);
1043 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1044 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1045 }
1046
1047 msleep(1000);
1048
1049 return 0;
1050 }
1051
1052 static void
1053 ar8327_init_globals(struct ar8216_priv *priv)
1054 {
1055 u32 t;
1056
1057 /* enable CPU port and disable mirror port */
1058 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1059 AR8327_FWD_CTRL0_MIRROR_PORT;
1060 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1061
1062 /* forward multicast and broadcast frames to CPU */
1063 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1064 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1065 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1066 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1067
1068 /* setup MTU */
1069 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1070 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1071
1072 /* Enable MIB counters */
1073 ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1074 AR8327_MODULE_EN_MIB);
1075 }
1076
1077 static void
1078 ar8327_init_cpuport(struct ar8216_priv *priv)
1079 {
1080 struct ar8327_platform_data *pdata;
1081 struct ar8327_port_cfg *cfg;
1082 u32 t;
1083
1084 pdata = priv->phy->dev.platform_data;
1085 if (!pdata)
1086 return;
1087
1088 cfg = &pdata->cpuport_cfg;
1089 if (!cfg->force_link) {
1090 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
1091 AR8216_PORT_STATUS_LINK_AUTO);
1092 return;
1093 }
1094
1095 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1096 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1097 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1098 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1099 switch (cfg->speed) {
1100 case AR8327_PORT_SPEED_10:
1101 t |= AR8216_PORT_SPEED_10M;
1102 break;
1103 case AR8327_PORT_SPEED_100:
1104 t |= AR8216_PORT_SPEED_100M;
1105 break;
1106 case AR8327_PORT_SPEED_1000:
1107 t |= AR8216_PORT_SPEED_1000M;
1108 break;
1109 }
1110
1111 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
1112 }
1113
1114 static void
1115 ar8327_init_port(struct ar8216_priv *priv, int port)
1116 {
1117 u32 t;
1118
1119 if (port == AR8216_PORT_CPU) {
1120 ar8327_init_cpuport(priv);
1121 } else {
1122 t = AR8216_PORT_STATUS_LINK_AUTO;
1123 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1124 }
1125
1126 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1127
1128 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
1129
1130 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1131 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1132
1133 t = AR8327_PORT_LOOKUP_LEARN;
1134 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1135 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1136 }
1137
1138 static u32
1139 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1140 {
1141 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1142 }
1143
1144 static int
1145 ar8327_atu_flush(struct ar8216_priv *priv)
1146 {
1147 int ret;
1148
1149 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1150 AR8327_ATU_FUNC_BUSY, 0);
1151 if (!ret)
1152 priv->write(priv, AR8327_REG_ATU_FUNC,
1153 AR8327_ATU_FUNC_OP_FLUSH);
1154
1155 return ret;
1156 }
1157
1158 static void
1159 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1160 {
1161 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1162 AR8327_VTU_FUNC1_BUSY, 0))
1163 return;
1164
1165 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1166 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1167
1168 op |= AR8327_VTU_FUNC1_BUSY;
1169 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1170 }
1171
1172 static void
1173 ar8327_vtu_flush(struct ar8216_priv *priv)
1174 {
1175 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1176 }
1177
1178 static void
1179 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1180 {
1181 u32 op;
1182 u32 val;
1183 int i;
1184
1185 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1186 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1187 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1188 u32 mode;
1189
1190 if ((port_mask & BIT(i)) == 0)
1191 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1192 else if (priv->vlan == 0)
1193 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1194 else if (priv->vlan_tagged & BIT(i))
1195 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1196 else
1197 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1198
1199 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1200 }
1201 ar8327_vtu_op(priv, op, val);
1202 }
1203
1204 static void
1205 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1206 u32 members, u32 pvid)
1207 {
1208 u32 t;
1209 u32 mode;
1210
1211 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1212 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1213 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1214
1215 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1216 switch (egress) {
1217 case AR8216_OUT_KEEP:
1218 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1219 break;
1220 case AR8216_OUT_STRIP_VLAN:
1221 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1222 break;
1223 case AR8216_OUT_ADD_VLAN:
1224 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1225 break;
1226 }
1227
1228 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1229 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1230 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1231
1232 t = members;
1233 t |= AR8327_PORT_LOOKUP_LEARN;
1234 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1235 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1236 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1237 }
1238
1239 static const struct ar8xxx_chip ar8327_chip = {
1240 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1241 .hw_init = ar8327_hw_init,
1242 .init_globals = ar8327_init_globals,
1243 .init_port = ar8327_init_port,
1244 .setup_port = ar8327_setup_port,
1245 .read_port_status = ar8327_read_port_status,
1246 .atu_flush = ar8327_atu_flush,
1247 .vtu_flush = ar8327_vtu_flush,
1248 .vtu_load_vlan = ar8327_vtu_load_vlan,
1249
1250 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1251 .mib_decs = ar8236_mibs,
1252 };
1253
1254 static int
1255 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1256 struct switch_val *val)
1257 {
1258 struct ar8216_priv *priv = to_ar8216(dev);
1259 priv->vlan = !!val->value.i;
1260 return 0;
1261 }
1262
1263 static int
1264 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1265 struct switch_val *val)
1266 {
1267 struct ar8216_priv *priv = to_ar8216(dev);
1268 val->value.i = priv->vlan;
1269 return 0;
1270 }
1271
1272
1273 static int
1274 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1275 {
1276 struct ar8216_priv *priv = to_ar8216(dev);
1277
1278 /* make sure no invalid PVIDs get set */
1279
1280 if (vlan >= dev->vlans)
1281 return -EINVAL;
1282
1283 priv->pvid[port] = vlan;
1284 return 0;
1285 }
1286
1287 static int
1288 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1289 {
1290 struct ar8216_priv *priv = to_ar8216(dev);
1291 *vlan = priv->pvid[port];
1292 return 0;
1293 }
1294
1295 static int
1296 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1297 struct switch_val *val)
1298 {
1299 struct ar8216_priv *priv = to_ar8216(dev);
1300 priv->vlan_id[val->port_vlan] = val->value.i;
1301 return 0;
1302 }
1303
1304 static int
1305 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1306 struct switch_val *val)
1307 {
1308 struct ar8216_priv *priv = to_ar8216(dev);
1309 val->value.i = priv->vlan_id[val->port_vlan];
1310 return 0;
1311 }
1312
1313 static int
1314 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1315 struct switch_port_link *link)
1316 {
1317 struct ar8216_priv *priv = to_ar8216(dev);
1318
1319 ar8216_read_port_link(priv, port, link);
1320 return 0;
1321 }
1322
1323 static int
1324 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1325 {
1326 struct ar8216_priv *priv = to_ar8216(dev);
1327 u8 ports = priv->vlan_table[val->port_vlan];
1328 int i;
1329
1330 val->len = 0;
1331 for (i = 0; i < dev->ports; i++) {
1332 struct switch_port *p;
1333
1334 if (!(ports & (1 << i)))
1335 continue;
1336
1337 p = &val->value.ports[val->len++];
1338 p->id = i;
1339 if (priv->vlan_tagged & (1 << i))
1340 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1341 else
1342 p->flags = 0;
1343 }
1344 return 0;
1345 }
1346
1347 static int
1348 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1349 {
1350 struct ar8216_priv *priv = to_ar8216(dev);
1351 u8 *vt = &priv->vlan_table[val->port_vlan];
1352 int i, j;
1353
1354 *vt = 0;
1355 for (i = 0; i < val->len; i++) {
1356 struct switch_port *p = &val->value.ports[i];
1357
1358 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1359 priv->vlan_tagged |= (1 << p->id);
1360 } else {
1361 priv->vlan_tagged &= ~(1 << p->id);
1362 priv->pvid[p->id] = val->port_vlan;
1363
1364 /* make sure that an untagged port does not
1365 * appear in other vlans */
1366 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1367 if (j == val->port_vlan)
1368 continue;
1369 priv->vlan_table[j] &= ~(1 << p->id);
1370 }
1371 }
1372
1373 *vt |= 1 << p->id;
1374 }
1375 return 0;
1376 }
1377
1378 static int
1379 ar8216_sw_hw_apply(struct switch_dev *dev)
1380 {
1381 struct ar8216_priv *priv = to_ar8216(dev);
1382 u8 portmask[AR8X16_MAX_PORTS];
1383 int i, j;
1384
1385 mutex_lock(&priv->reg_mutex);
1386 /* flush all vlan translation unit entries */
1387 priv->chip->vtu_flush(priv);
1388
1389 memset(portmask, 0, sizeof(portmask));
1390 if (!priv->init) {
1391 /* calculate the port destination masks and load vlans
1392 * into the vlan translation unit */
1393 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1394 u8 vp = priv->vlan_table[j];
1395
1396 if (!vp)
1397 continue;
1398
1399 for (i = 0; i < dev->ports; i++) {
1400 u8 mask = (1 << i);
1401 if (vp & mask)
1402 portmask[i] |= vp & ~mask;
1403 }
1404
1405 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1406 priv->vlan_table[j]);
1407 }
1408 } else {
1409 /* vlan disabled:
1410 * isolate all ports, but connect them to the cpu port */
1411 for (i = 0; i < dev->ports; i++) {
1412 if (i == AR8216_PORT_CPU)
1413 continue;
1414
1415 portmask[i] = 1 << AR8216_PORT_CPU;
1416 portmask[AR8216_PORT_CPU] |= (1 << i);
1417 }
1418 }
1419
1420 /* update the port destination mask registers and tag settings */
1421 for (i = 0; i < dev->ports; i++) {
1422 int egress, ingress;
1423 int pvid;
1424
1425 if (priv->vlan) {
1426 pvid = priv->vlan_id[priv->pvid[i]];
1427 if (priv->vlan_tagged & (1 << i))
1428 egress = AR8216_OUT_ADD_VLAN;
1429 else
1430 egress = AR8216_OUT_STRIP_VLAN;
1431 ingress = AR8216_IN_SECURE;
1432 } else {
1433 pvid = i;
1434 egress = AR8216_OUT_KEEP;
1435 ingress = AR8216_IN_PORT_ONLY;
1436 }
1437
1438 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1439 pvid);
1440 }
1441 mutex_unlock(&priv->reg_mutex);
1442 return 0;
1443 }
1444
1445 static int
1446 ar8216_sw_reset_switch(struct switch_dev *dev)
1447 {
1448 struct ar8216_priv *priv = to_ar8216(dev);
1449 int i;
1450
1451 mutex_lock(&priv->reg_mutex);
1452 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1453 offsetof(struct ar8216_priv, vlan));
1454
1455 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1456 priv->vlan_id[i] = i;
1457
1458 /* Configure all ports */
1459 for (i = 0; i < dev->ports; i++)
1460 priv->chip->init_port(priv, i);
1461
1462 priv->chip->init_globals(priv);
1463 mutex_unlock(&priv->reg_mutex);
1464
1465 return ar8216_sw_hw_apply(dev);
1466 }
1467
1468 static int
1469 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1470 const struct switch_attr *attr,
1471 struct switch_val *val)
1472 {
1473 struct ar8216_priv *priv = to_ar8216(dev);
1474 unsigned int len;
1475 int ret;
1476
1477 if (!ar8xxx_has_mib_counters(priv))
1478 return -EOPNOTSUPP;
1479
1480 mutex_lock(&priv->mib_lock);
1481
1482 len = priv->dev.ports * priv->chip->num_mibs *
1483 sizeof(*priv->mib_stats);
1484 memset(priv->mib_stats, '\0', len);
1485 ret = ar8216_mib_flush(priv);
1486 if (ret)
1487 goto unlock;
1488
1489 ret = 0;
1490
1491 unlock:
1492 mutex_unlock(&priv->mib_lock);
1493 return ret;
1494 }
1495
1496 static int
1497 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1498 const struct switch_attr *attr,
1499 struct switch_val *val)
1500 {
1501 struct ar8216_priv *priv = to_ar8216(dev);
1502 int port;
1503 int ret;
1504
1505 if (!ar8xxx_has_mib_counters(priv))
1506 return -EOPNOTSUPP;
1507
1508 port = val->port_vlan;
1509 if (port >= dev->ports)
1510 return -EINVAL;
1511
1512 mutex_lock(&priv->mib_lock);
1513 ret = ar8216_mib_capture(priv);
1514 if (ret)
1515 goto unlock;
1516
1517 ar8216_mib_fetch_port_stat(priv, port, true);
1518
1519 ret = 0;
1520
1521 unlock:
1522 mutex_unlock(&priv->mib_lock);
1523 return ret;
1524 }
1525
1526 static int
1527 ar8216_sw_get_port_mib(struct switch_dev *dev,
1528 const struct switch_attr *attr,
1529 struct switch_val *val)
1530 {
1531 struct ar8216_priv *priv = to_ar8216(dev);
1532 const struct ar8xxx_chip *chip = priv->chip;
1533 u64 *mib_stats;
1534 int port;
1535 int ret;
1536 char *buf = priv->buf;
1537 int i, len = 0;
1538
1539 if (!ar8xxx_has_mib_counters(priv))
1540 return -EOPNOTSUPP;
1541
1542 port = val->port_vlan;
1543 if (port >= dev->ports)
1544 return -EINVAL;
1545
1546 mutex_lock(&priv->mib_lock);
1547 ret = ar8216_mib_capture(priv);
1548 if (ret)
1549 goto unlock;
1550
1551 ar8216_mib_fetch_port_stat(priv, port, false);
1552 mutex_unlock(&priv->mib_lock);
1553
1554 len += snprintf(buf + len, sizeof(priv->buf) - len,
1555 "Port %d MIB counters\n",
1556 port);
1557
1558 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1559 for (i = 0; i < chip->num_mibs; i++)
1560 len += snprintf(buf + len, sizeof(priv->buf) - len,
1561 "%-12s: %llu\n",
1562 chip->mib_decs[i].name,
1563 mib_stats[i]);
1564
1565 val->value.s = buf;
1566 val->len = len;
1567
1568 ret = 0;
1569
1570 unlock:
1571 mutex_unlock(&priv->mib_lock);
1572 return ret;
1573 }
1574
1575 static struct switch_attr ar8216_globals[] = {
1576 {
1577 .type = SWITCH_TYPE_INT,
1578 .name = "enable_vlan",
1579 .description = "Enable VLAN mode",
1580 .set = ar8216_sw_set_vlan,
1581 .get = ar8216_sw_get_vlan,
1582 .max = 1
1583 },
1584 {
1585 .type = SWITCH_TYPE_NOVAL,
1586 .name = "reset_mibs",
1587 .description = "Reset all MIB counters",
1588 .set = ar8216_sw_set_reset_mibs,
1589 },
1590
1591 };
1592
1593 static struct switch_attr ar8216_port[] = {
1594 {
1595 .type = SWITCH_TYPE_NOVAL,
1596 .name = "reset_mib",
1597 .description = "Reset single port MIB counters",
1598 .set = ar8216_sw_set_port_reset_mib,
1599 },
1600 {
1601 .type = SWITCH_TYPE_STRING,
1602 .name = "mib",
1603 .description = "Get port's MIB counters",
1604 .set = NULL,
1605 .get = ar8216_sw_get_port_mib,
1606 },
1607 };
1608
1609 static struct switch_attr ar8216_vlan[] = {
1610 {
1611 .type = SWITCH_TYPE_INT,
1612 .name = "vid",
1613 .description = "VLAN ID (0-4094)",
1614 .set = ar8216_sw_set_vid,
1615 .get = ar8216_sw_get_vid,
1616 .max = 4094,
1617 },
1618 };
1619
1620 static const struct switch_dev_ops ar8216_sw_ops = {
1621 .attr_global = {
1622 .attr = ar8216_globals,
1623 .n_attr = ARRAY_SIZE(ar8216_globals),
1624 },
1625 .attr_port = {
1626 .attr = ar8216_port,
1627 .n_attr = ARRAY_SIZE(ar8216_port),
1628 },
1629 .attr_vlan = {
1630 .attr = ar8216_vlan,
1631 .n_attr = ARRAY_SIZE(ar8216_vlan),
1632 },
1633 .get_port_pvid = ar8216_sw_get_pvid,
1634 .set_port_pvid = ar8216_sw_set_pvid,
1635 .get_vlan_ports = ar8216_sw_get_ports,
1636 .set_vlan_ports = ar8216_sw_set_ports,
1637 .apply_config = ar8216_sw_hw_apply,
1638 .reset_switch = ar8216_sw_reset_switch,
1639 .get_port_link = ar8216_sw_get_port_link,
1640 };
1641
1642 static int
1643 ar8216_id_chip(struct ar8216_priv *priv)
1644 {
1645 u32 val;
1646 u16 id;
1647 int i;
1648
1649 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1650 if (val == ~0)
1651 return -ENODEV;
1652
1653 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1654 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1655 u16 t;
1656
1657 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1658 if (val == ~0)
1659 return -ENODEV;
1660
1661 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1662 if (t != id)
1663 return -ENODEV;
1664 }
1665
1666 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1667 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1668
1669 switch (priv->chip_ver) {
1670 case AR8XXX_VER_AR8216:
1671 priv->chip = &ar8216_chip;
1672 break;
1673 case AR8XXX_VER_AR8236:
1674 priv->chip = &ar8236_chip;
1675 break;
1676 case AR8XXX_VER_AR8316:
1677 priv->chip = &ar8316_chip;
1678 break;
1679 case AR8XXX_VER_AR8327:
1680 priv->mii_lo_first = true;
1681 priv->chip = &ar8327_chip;
1682 break;
1683 default:
1684 printk(KERN_DEBUG
1685 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1686 priv->chip_ver, priv->chip_rev,
1687 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1688 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1689
1690 return -ENODEV;
1691 }
1692
1693 return 0;
1694 }
1695
1696 static void
1697 ar8xxx_mib_work_func(struct work_struct *work)
1698 {
1699 struct ar8216_priv *priv;
1700 int err;
1701
1702 priv = container_of(work, struct ar8216_priv, mib_work.work);
1703
1704 mutex_lock(&priv->mib_lock);
1705
1706 err = ar8216_mib_capture(priv);
1707 if (err)
1708 goto next_port;
1709
1710 ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1711
1712 next_port:
1713 priv->mib_next_port++;
1714 if (priv->mib_next_port > priv->dev.ports)
1715 priv->mib_next_port = 0;
1716
1717 mutex_unlock(&priv->mib_lock);
1718 schedule_delayed_work(&priv->mib_work,
1719 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1720 }
1721
1722 static int
1723 ar8xxx_mib_init(struct ar8216_priv *priv)
1724 {
1725 unsigned int len;
1726
1727 if (!ar8xxx_has_mib_counters(priv))
1728 return 0;
1729
1730 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1731
1732 len = priv->dev.ports * priv->chip->num_mibs *
1733 sizeof(*priv->mib_stats);
1734 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1735
1736 if (!priv->mib_stats)
1737 return -ENOMEM;
1738
1739 mutex_init(&priv->mib_lock);
1740 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1741
1742 return 0;
1743 }
1744
1745 static void
1746 ar8xxx_mib_start(struct ar8216_priv *priv)
1747 {
1748 if (!ar8xxx_has_mib_counters(priv))
1749 return;
1750
1751 schedule_delayed_work(&priv->mib_work,
1752 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1753 }
1754
1755 static void
1756 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1757 {
1758 if (!ar8xxx_has_mib_counters(priv))
1759 return;
1760
1761 cancel_delayed_work(&priv->mib_work);
1762 kfree(priv->mib_stats);
1763 }
1764
1765 static int
1766 ar8216_config_init(struct phy_device *pdev)
1767 {
1768 struct ar8216_priv *priv = pdev->priv;
1769 struct net_device *dev = pdev->attached_dev;
1770 struct switch_dev *swdev;
1771 int ret;
1772
1773 if (!priv) {
1774 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1775 if (priv == NULL)
1776 return -ENOMEM;
1777 }
1778
1779 priv->phy = pdev;
1780
1781 ret = ar8216_id_chip(priv);
1782 if (ret)
1783 goto err_free_priv;
1784
1785 if (pdev->addr != 0) {
1786 if (ar8xxx_has_gige(priv)) {
1787 pdev->supported |= SUPPORTED_1000baseT_Full;
1788 pdev->advertising |= ADVERTISED_1000baseT_Full;
1789 }
1790
1791 if (chip_is_ar8316(priv)) {
1792 /* check if we're attaching to the switch twice */
1793 pdev = pdev->bus->phy_map[0];
1794 if (!pdev) {
1795 kfree(priv);
1796 return 0;
1797 }
1798
1799 /* switch device has not been initialized, reuse priv */
1800 if (!pdev->priv) {
1801 priv->port4_phy = true;
1802 pdev->priv = priv;
1803 return 0;
1804 }
1805
1806 kfree(priv);
1807
1808 /* switch device has been initialized, reinit */
1809 priv = pdev->priv;
1810 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1811 priv->initialized = false;
1812 priv->port4_phy = true;
1813 ar8316_hw_init(priv);
1814 return 0;
1815 }
1816
1817 kfree(priv);
1818 return 0;
1819 }
1820
1821 if (ar8xxx_has_gige(priv))
1822 pdev->supported = SUPPORTED_1000baseT_Full;
1823 else
1824 pdev->supported = SUPPORTED_100baseT_Full;
1825 pdev->advertising = pdev->supported;
1826
1827 mutex_init(&priv->reg_mutex);
1828 priv->read = ar8216_mii_read;
1829 priv->write = ar8216_mii_write;
1830
1831 pdev->priv = priv;
1832
1833 swdev = &priv->dev;
1834 swdev->cpu_port = AR8216_PORT_CPU;
1835 swdev->ops = &ar8216_sw_ops;
1836 swdev->ports = AR8216_NUM_PORTS;
1837
1838 if (chip_is_ar8316(priv)) {
1839 swdev->name = "Atheros AR8316";
1840 swdev->vlans = AR8X16_MAX_VLANS;
1841
1842 if (priv->port4_phy) {
1843 /* port 5 connected to the other mac, therefore unusable */
1844 swdev->ports = (AR8216_NUM_PORTS - 1);
1845 }
1846 } else if (chip_is_ar8236(priv)) {
1847 swdev->name = "Atheros AR8236";
1848 swdev->vlans = AR8216_NUM_VLANS;
1849 swdev->ports = AR8216_NUM_PORTS;
1850 } else if (chip_is_ar8327(priv)) {
1851 swdev->name = "Atheros AR8327";
1852 swdev->vlans = AR8X16_MAX_VLANS;
1853 swdev->ports = AR8327_NUM_PORTS;
1854 } else {
1855 swdev->name = "Atheros AR8216";
1856 swdev->vlans = AR8216_NUM_VLANS;
1857 }
1858
1859 ret = ar8xxx_mib_init(priv);
1860 if (ret)
1861 goto err_free_priv;
1862
1863 ret = register_switch(&priv->dev, pdev->attached_dev);
1864 if (ret)
1865 goto err_cleanup_mib;
1866
1867 printk(KERN_INFO "%s: %s switch driver attached.\n",
1868 pdev->attached_dev->name, swdev->name);
1869
1870 priv->init = true;
1871
1872 ret = priv->chip->hw_init(priv);
1873 if (ret)
1874 goto err_cleanup_mib;
1875
1876 ret = ar8216_sw_reset_switch(&priv->dev);
1877 if (ret)
1878 goto err_cleanup_mib;
1879
1880 dev->phy_ptr = priv;
1881
1882 /* VID fixup only needed on ar8216 */
1883 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1884 dev->priv_flags |= IFF_NO_IP_ALIGN;
1885 dev->eth_mangle_rx = ar8216_mangle_rx;
1886 dev->eth_mangle_tx = ar8216_mangle_tx;
1887 }
1888
1889 priv->init = false;
1890
1891 ar8xxx_mib_start(priv);
1892
1893 return 0;
1894
1895 err_cleanup_mib:
1896 ar8xxx_mib_cleanup(priv);
1897 err_free_priv:
1898 kfree(priv);
1899 return ret;
1900 }
1901
1902 static int
1903 ar8216_read_status(struct phy_device *phydev)
1904 {
1905 struct ar8216_priv *priv = phydev->priv;
1906 struct switch_port_link link;
1907 int ret;
1908
1909 if (phydev->addr != 0)
1910 return genphy_read_status(phydev);
1911
1912 ar8216_read_port_link(priv, phydev->addr, &link);
1913 phydev->link = !!link.link;
1914 if (!phydev->link)
1915 return 0;
1916
1917 switch (link.speed) {
1918 case SWITCH_PORT_SPEED_10:
1919 phydev->speed = SPEED_10;
1920 break;
1921 case SWITCH_PORT_SPEED_100:
1922 phydev->speed = SPEED_100;
1923 break;
1924 case SWITCH_PORT_SPEED_1000:
1925 phydev->speed = SPEED_1000;
1926 break;
1927 default:
1928 phydev->speed = 0;
1929 }
1930 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1931
1932 /* flush the address translation unit */
1933 mutex_lock(&priv->reg_mutex);
1934 ret = priv->chip->atu_flush(priv);
1935 mutex_unlock(&priv->reg_mutex);
1936
1937 phydev->state = PHY_RUNNING;
1938 netif_carrier_on(phydev->attached_dev);
1939 phydev->adjust_link(phydev->attached_dev);
1940
1941 return ret;
1942 }
1943
1944 static int
1945 ar8216_config_aneg(struct phy_device *phydev)
1946 {
1947 if (phydev->addr == 0)
1948 return 0;
1949
1950 return genphy_config_aneg(phydev);
1951 }
1952
1953 static int
1954 ar8216_probe(struct phy_device *pdev)
1955 {
1956 struct ar8216_priv *priv;
1957 int ret;
1958
1959 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1960 if (priv == NULL)
1961 return -ENOMEM;
1962
1963 priv->phy = pdev;
1964
1965 ret = ar8216_id_chip(priv);
1966 kfree(priv);
1967
1968 return ret;
1969 }
1970
1971 static void
1972 ar8216_remove(struct phy_device *pdev)
1973 {
1974 struct ar8216_priv *priv = pdev->priv;
1975 struct net_device *dev = pdev->attached_dev;
1976
1977 if (!priv)
1978 return;
1979
1980 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1981 dev->eth_mangle_rx = NULL;
1982 dev->eth_mangle_tx = NULL;
1983
1984 if (pdev->addr == 0)
1985 unregister_switch(&priv->dev);
1986
1987 ar8xxx_mib_cleanup(priv);
1988 kfree(priv);
1989 }
1990
1991 static struct phy_driver ar8216_driver = {
1992 .phy_id = 0x004d0000,
1993 .name = "Atheros AR8216/AR8236/AR8316",
1994 .phy_id_mask = 0xffff0000,
1995 .features = PHY_BASIC_FEATURES,
1996 .probe = ar8216_probe,
1997 .remove = ar8216_remove,
1998 .config_init = &ar8216_config_init,
1999 .config_aneg = &ar8216_config_aneg,
2000 .read_status = &ar8216_read_status,
2001 .driver = { .owner = THIS_MODULE },
2002 };
2003
2004 int __init
2005 ar8216_init(void)
2006 {
2007 return phy_driver_register(&ar8216_driver);
2008 }
2009
2010 void __exit
2011 ar8216_exit(void)
2012 {
2013 phy_driver_unregister(&ar8216_driver);
2014 }
2015
2016 module_init(ar8216_init);
2017 module_exit(ar8216_exit);
2018 MODULE_LICENSE("GPL");
2019
OpenWrt SVN history