projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
generic: ar8216: fix PHY features setup
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8216_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8216_priv *priv);
67 void (*init_globals)(struct ar8216_priv *priv);
68 void (*init_port)(struct ar8216_priv *priv, int port);
69 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72 int (*atu_flush)(struct ar8216_priv *priv);
73 void (*vtu_flush)(struct ar8216_priv *priv);
74 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8216_priv {
81 struct switch_dev dev;
82 struct mii_bus *mii_bus;
83 struct phy_device *phy;
84 u32 (*read)(struct ar8216_priv *priv, int reg);
85 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
86 const struct net_device_ops *ndo_old;
87 struct net_device_ops ndo;
88 struct mutex reg_mutex;
89 u8 chip_ver;
90 u8 chip_rev;
91 const struct ar8xxx_chip *chip;
92 bool initialized;
93 bool port4_phy;
94 char buf[2048];
95
96 bool init;
97 bool mii_lo_first;
98
99 struct mutex mib_lock;
100 struct delayed_work mib_work;
101 int mib_next_port;
102 u64 *mib_stats;
103
104 /* all fields below are cleared on reset */
105 bool vlan;
106 u16 vlan_id[AR8X16_MAX_VLANS];
107 u8 vlan_table[AR8X16_MAX_VLANS];
108 u8 vlan_tagged;
109 u16 pvid[AR8X16_MAX_PORTS];
110 };
111
112 #define MIB_DESC(_s , _o, _n) \
113 { \
114 .size = (_s), \
115 .offset = (_o), \
116 .name = (_n), \
117 }
118
119 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
120 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
121 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
122 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
123 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
124 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
125 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
126 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
127 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
128 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
129 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
130 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
131 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
132 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
133 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
134 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
135 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
136 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
137 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
138 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
139 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
140 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
141 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
142 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
143 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
144 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
145 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
146 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
147 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
148 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
149 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
150 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
151 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
152 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
153 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
154 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
155 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
156 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
157 };
158
159 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
160 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
161 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
162 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
163 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
164 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
165 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
166 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
167 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
168 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
169 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
170 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
172 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
173 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
174 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
175 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
176 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
177 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
178 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
179 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
180 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
181 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
182 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
183 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
184 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
185 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
186 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
188 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
189 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
190 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
191 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
192 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
193 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
194 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
195 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
196 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
197 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
198 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
199 };
200
201 static inline struct ar8216_priv *
202 swdev_to_ar8216(struct switch_dev *swdev)
203 {
204 return container_of(swdev, struct ar8216_priv, dev);
205 }
206
207 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
208 {
209 return priv->chip->caps & AR8XXX_CAP_GIGE;
210 }
211
212 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
213 {
214 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
215 }
216
217 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
218 {
219 return priv->chip_ver == AR8XXX_VER_AR8216;
220 }
221
222 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
223 {
224 return priv->chip_ver == AR8XXX_VER_AR8236;
225 }
226
227 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
228 {
229 return priv->chip_ver == AR8XXX_VER_AR8316;
230 }
231
232 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
233 {
234 return priv->chip_ver == AR8XXX_VER_AR8327;
235 }
236
237 static inline void
238 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
239 {
240 regaddr >>= 1;
241 *r1 = regaddr & 0x1e;
242
243 regaddr >>= 5;
244 *r2 = regaddr & 0x7;
245
246 regaddr >>= 3;
247 *page = regaddr & 0x1ff;
248 }
249
250 static u32
251 ar8216_mii_read(struct ar8216_priv *priv, int reg)
252 {
253 struct mii_bus *bus = priv->mii_bus;
254 u16 r1, r2, page;
255 u16 lo, hi;
256
257 split_addr((u32) reg, &r1, &r2, &page);
258
259 mutex_lock(&bus->mdio_lock);
260
261 bus->write(bus, 0x18, 0, page);
262 usleep_range(1000, 2000); /* wait for the page switch to propagate */
263 lo = bus->read(bus, 0x10 | r2, r1);
264 hi = bus->read(bus, 0x10 | r2, r1 + 1);
265
266 mutex_unlock(&bus->mdio_lock);
267
268 return (hi << 16) | lo;
269 }
270
271 static void
272 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
273 {
274 struct mii_bus *bus = priv->mii_bus;
275 u16 r1, r2, r3;
276 u16 lo, hi;
277
278 split_addr((u32) reg, &r1, &r2, &r3);
279 lo = val & 0xffff;
280 hi = (u16) (val >> 16);
281
282 mutex_lock(&bus->mdio_lock);
283
284 bus->write(bus, 0x18, 0, r3);
285 usleep_range(1000, 2000); /* wait for the page switch to propagate */
286 if (priv->mii_lo_first) {
287 bus->write(bus, 0x10 | r2, r1, lo);
288 bus->write(bus, 0x10 | r2, r1 + 1, hi);
289 } else {
290 bus->write(bus, 0x10 | r2, r1 + 1, hi);
291 bus->write(bus, 0x10 | r2, r1, lo);
292 }
293
294 mutex_unlock(&bus->mdio_lock);
295 }
296
297 static void
298 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
299 u16 dbg_addr, u16 dbg_data)
300 {
301 struct mii_bus *bus = priv->mii_bus;
302
303 mutex_lock(&bus->mdio_lock);
304 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
305 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
306 mutex_unlock(&bus->mdio_lock);
307 }
308
309 static void
310 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
311 {
312 struct mii_bus *bus = priv->mii_bus;
313
314 mutex_lock(&bus->mdio_lock);
315 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
316 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
317 mutex_unlock(&bus->mdio_lock);
318 }
319
320 static u32
321 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
322 {
323 u32 v;
324
325 lockdep_assert_held(&priv->reg_mutex);
326
327 v = priv->read(priv, reg);
328 v &= ~mask;
329 v |= val;
330 priv->write(priv, reg, v);
331
332 return v;
333 }
334
335 static inline void
336 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
337 {
338 u32 v;
339
340 lockdep_assert_held(&priv->reg_mutex);
341
342 v = priv->read(priv, reg);
343 v |= val;
344 priv->write(priv, reg, v);
345 }
346
347 static int
348 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
349 unsigned timeout)
350 {
351 int i;
352
353 for (i = 0; i < timeout; i++) {
354 u32 t;
355
356 t = priv->read(priv, reg);
357 if ((t & mask) == val)
358 return 0;
359
360 usleep_range(1000, 2000);
361 }
362
363 return -ETIMEDOUT;
364 }
365
366 static int
367 ar8216_mib_op(struct ar8216_priv *priv, u32 op)
368 {
369 unsigned mib_func;
370 int ret;
371
372 lockdep_assert_held(&priv->mib_lock);
373
374 if (chip_is_ar8327(priv))
375 mib_func = AR8327_REG_MIB_FUNC;
376 else
377 mib_func = AR8216_REG_MIB_FUNC;
378
379 mutex_lock(&priv->reg_mutex);
380 /* Capture the hardware statistics for all ports */
381 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
382 mutex_unlock(&priv->reg_mutex);
383
384 /* Wait for the capturing to complete. */
385 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
386 if (ret)
387 goto out;
388
389 ret = 0;
390
391 out:
392 return ret;
393 }
394
395 static int
396 ar8216_mib_capture(struct ar8216_priv *priv)
397 {
398 return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
399 }
400
401 static int
402 ar8216_mib_flush(struct ar8216_priv *priv)
403 {
404 return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
405 }
406
407 static void
408 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
409 {
410 unsigned int base;
411 u64 *mib_stats;
412 int i;
413
414 WARN_ON(port >= priv->dev.ports);
415
416 lockdep_assert_held(&priv->mib_lock);
417
418 if (chip_is_ar8327(priv))
419 base = AR8327_REG_PORT_STATS_BASE(port);
420 else if (chip_is_ar8236(priv) ||
421 chip_is_ar8316(priv))
422 base = AR8236_REG_PORT_STATS_BASE(port);
423 else
424 base = AR8216_REG_PORT_STATS_BASE(port);
425
426 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
427 for (i = 0; i < priv->chip->num_mibs; i++) {
428 const struct ar8xxx_mib_desc *mib;
429 u64 t;
430
431 mib = &priv->chip->mib_decs[i];
432 t = priv->read(priv, base + mib->offset);
433 if (mib->size == 2) {
434 u64 hi;
435
436 hi = priv->read(priv, base + mib->offset + 4);
437 t |= hi << 32;
438 }
439
440 if (flush)
441 mib_stats[i] = 0;
442 else
443 mib_stats[i] += t;
444 }
445 }
446
447 static void
448 ar8216_read_port_link(struct ar8216_priv *priv, int port,
449 struct switch_port_link *link)
450 {
451 u32 status;
452 u32 speed;
453
454 memset(link, '\0', sizeof(*link));
455
456 status = priv->chip->read_port_status(priv, port);
457
458 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
459 if (link->aneg) {
460 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
461 if (!link->link)
462 return;
463 } else {
464 link->link = true;
465 }
466
467 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
468 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
469 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
470
471 speed = (status & AR8216_PORT_STATUS_SPEED) >>
472 AR8216_PORT_STATUS_SPEED_S;
473
474 switch (speed) {
475 case AR8216_PORT_SPEED_10M:
476 link->speed = SWITCH_PORT_SPEED_10;
477 break;
478 case AR8216_PORT_SPEED_100M:
479 link->speed = SWITCH_PORT_SPEED_100;
480 break;
481 case AR8216_PORT_SPEED_1000M:
482 link->speed = SWITCH_PORT_SPEED_1000;
483 break;
484 default:
485 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
486 break;
487 }
488 }
489
490 static struct sk_buff *
491 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
492 {
493 struct ar8216_priv *priv = dev->phy_ptr;
494 unsigned char *buf;
495
496 if (unlikely(!priv))
497 goto error;
498
499 if (!priv->vlan)
500 goto send;
501
502 if (unlikely(skb_headroom(skb) < 2)) {
503 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
504 goto error;
505 }
506
507 buf = skb_push(skb, 2);
508 buf[0] = 0x10;
509 buf[1] = 0x80;
510
511 send:
512 return skb;
513
514 error:
515 dev_kfree_skb_any(skb);
516 return NULL;
517 }
518
519 static void
520 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
521 {
522 struct ar8216_priv *priv;
523 unsigned char *buf;
524 int port, vlan;
525
526 priv = dev->phy_ptr;
527 if (!priv)
528 return;
529
530 /* don't strip the header if vlan mode is disabled */
531 if (!priv->vlan)
532 return;
533
534 /* strip header, get vlan id */
535 buf = skb->data;
536 skb_pull(skb, 2);
537
538 /* check for vlan header presence */
539 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
540 return;
541
542 port = buf[0] & 0xf;
543
544 /* no need to fix up packets coming from a tagged source */
545 if (priv->vlan_tagged & (1 << port))
546 return;
547
548 /* lookup port vid from local table, the switch passes an invalid vlan id */
549 vlan = priv->vlan_id[priv->pvid[port]];
550
551 buf[14 + 2] &= 0xf0;
552 buf[14 + 2] |= vlan >> 8;
553 buf[15 + 2] = vlan & 0xff;
554 }
555
556 static int
557 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
558 {
559 int timeout = 20;
560 u32 t = 0;
561
562 while (1) {
563 t = priv->read(priv, reg);
564 if ((t & mask) == val)
565 return 0;
566
567 if (timeout-- <= 0)
568 break;
569
570 udelay(10);
571 }
572
573 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
574 (unsigned int) reg, t, mask, val);
575 return -ETIMEDOUT;
576 }
577
578 static void
579 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
580 {
581 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
582 return;
583 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
584 val &= AR8216_VTUDATA_MEMBER;
585 val |= AR8216_VTUDATA_VALID;
586 priv->write(priv, AR8216_REG_VTU_DATA, val);
587 }
588 op |= AR8216_VTU_ACTIVE;
589 priv->write(priv, AR8216_REG_VTU, op);
590 }
591
592 static void
593 ar8216_vtu_flush(struct ar8216_priv *priv)
594 {
595 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
596 }
597
598 static void
599 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
600 {
601 u32 op;
602
603 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
604 ar8216_vtu_op(priv, op, port_mask);
605 }
606
607 static int
608 ar8216_atu_flush(struct ar8216_priv *priv)
609 {
610 int ret;
611
612 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
613 if (!ret)
614 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
615
616 return ret;
617 }
618
619 static u32
620 ar8216_read_port_status(struct ar8216_priv *priv, int port)
621 {
622 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
623 }
624
625 static void
626 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
627 u32 members, u32 pvid)
628 {
629 u32 header;
630
631 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
632 header = AR8216_PORT_CTRL_HEADER;
633 else
634 header = 0;
635
636 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
637 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
638 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
639 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
640 AR8216_PORT_CTRL_LEARN | header |
641 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
642 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
643
644 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
645 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
646 AR8216_PORT_VLAN_DEFAULT_ID,
647 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
648 (ingress << AR8216_PORT_VLAN_MODE_S) |
649 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
650 }
651
652 static int
653 ar8216_hw_init(struct ar8216_priv *priv)
654 {
655 return 0;
656 }
657
658 static void
659 ar8216_init_globals(struct ar8216_priv *priv)
660 {
661 /* standard atheros magic */
662 priv->write(priv, 0x38, 0xc000050e);
663
664 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
665 AR8216_GCTRL_MTU, 1518 + 8 + 2);
666 }
667
668 static void
669 ar8216_init_port(struct ar8216_priv *priv, int port)
670 {
671 /* Enable port learning and tx */
672 priv->write(priv, AR8216_REG_PORT_CTRL(port),
673 AR8216_PORT_CTRL_LEARN |
674 (4 << AR8216_PORT_CTRL_STATE_S));
675
676 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
677
678 if (port == AR8216_PORT_CPU) {
679 priv->write(priv, AR8216_REG_PORT_STATUS(port),
680 AR8216_PORT_STATUS_LINK_UP |
681 (ar8xxx_has_gige(priv) ?
682 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
683 AR8216_PORT_STATUS_TXMAC |
684 AR8216_PORT_STATUS_RXMAC |
685 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
686 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
687 AR8216_PORT_STATUS_DUPLEX);
688 } else {
689 priv->write(priv, AR8216_REG_PORT_STATUS(port),
690 AR8216_PORT_STATUS_LINK_AUTO);
691 }
692 }
693
694 static const struct ar8xxx_chip ar8216_chip = {
695 .caps = AR8XXX_CAP_MIB_COUNTERS,
696
697 .hw_init = ar8216_hw_init,
698 .init_globals = ar8216_init_globals,
699 .init_port = ar8216_init_port,
700 .setup_port = ar8216_setup_port,
701 .read_port_status = ar8216_read_port_status,
702 .atu_flush = ar8216_atu_flush,
703 .vtu_flush = ar8216_vtu_flush,
704 .vtu_load_vlan = ar8216_vtu_load_vlan,
705
706 .num_mibs = ARRAY_SIZE(ar8216_mibs),
707 .mib_decs = ar8216_mibs,
708 };
709
710 static void
711 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
712 u32 members, u32 pvid)
713 {
714 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
715 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
716 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
717 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
718 AR8216_PORT_CTRL_LEARN |
719 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
720 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
721
722 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
723 AR8236_PORT_VLAN_DEFAULT_ID,
724 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
725
726 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
727 AR8236_PORT_VLAN2_VLAN_MODE |
728 AR8236_PORT_VLAN2_MEMBER,
729 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
730 (members << AR8236_PORT_VLAN2_MEMBER_S));
731 }
732
733 static int
734 ar8236_hw_init(struct ar8216_priv *priv)
735 {
736 int i;
737 struct mii_bus *bus;
738
739 if (priv->initialized)
740 return 0;
741
742 /* Initialize the PHYs */
743 bus = priv->mii_bus;
744 for (i = 0; i < 5; i++) {
745 mdiobus_write(bus, i, MII_ADVERTISE,
746 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
747 ADVERTISE_PAUSE_ASYM);
748 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
749 }
750 msleep(1000);
751
752 priv->initialized = true;
753 return 0;
754 }
755
756 static void
757 ar8236_init_globals(struct ar8216_priv *priv)
758 {
759 /* enable jumbo frames */
760 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
761 AR8316_GCTRL_MTU, 9018 + 8 + 2);
762
763 /* Enable MIB counters */
764 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
765 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
766 AR8236_MIB_EN);
767 }
768
769 static const struct ar8xxx_chip ar8236_chip = {
770 .caps = AR8XXX_CAP_MIB_COUNTERS,
771 .hw_init = ar8236_hw_init,
772 .init_globals = ar8236_init_globals,
773 .init_port = ar8216_init_port,
774 .setup_port = ar8236_setup_port,
775 .read_port_status = ar8216_read_port_status,
776 .atu_flush = ar8216_atu_flush,
777 .vtu_flush = ar8216_vtu_flush,
778 .vtu_load_vlan = ar8216_vtu_load_vlan,
779
780 .num_mibs = ARRAY_SIZE(ar8236_mibs),
781 .mib_decs = ar8236_mibs,
782 };
783
784 static int
785 ar8316_hw_init(struct ar8216_priv *priv)
786 {
787 int i;
788 u32 val, newval;
789 struct mii_bus *bus;
790
791 val = priv->read(priv, AR8316_REG_POSTRIP);
792
793 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
794 if (priv->port4_phy) {
795 /* value taken from Ubiquiti RouterStation Pro */
796 newval = 0x81461bea;
797 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
798 } else {
799 newval = 0x01261be2;
800 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
801 }
802 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
803 /* value taken from AVM Fritz!Box 7390 sources */
804 newval = 0x010e5b71;
805 } else {
806 /* no known value for phy interface */
807 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
808 priv->phy->interface);
809 return -EINVAL;
810 }
811
812 if (val == newval)
813 goto out;
814
815 priv->write(priv, AR8316_REG_POSTRIP, newval);
816
817 /* Initialize the ports */
818 bus = priv->mii_bus;
819 for (i = 0; i < 5; i++) {
820 if ((i == 4) && priv->port4_phy &&
821 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
822 /* work around for phy4 rgmii mode */
823 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
824 /* rx delay */
825 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
826 /* tx delay */
827 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
828 msleep(1000);
829 }
830
831 /* initialize the port itself */
832 mdiobus_write(bus, i, MII_ADVERTISE,
833 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
834 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
835 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
836 }
837
838 msleep(1000);
839
840 out:
841 priv->initialized = true;
842 return 0;
843 }
844
845 static void
846 ar8316_init_globals(struct ar8216_priv *priv)
847 {
848 /* standard atheros magic */
849 priv->write(priv, 0x38, 0xc000050e);
850
851 /* enable cpu port to receive multicast and broadcast frames */
852 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
853
854 /* enable jumbo frames */
855 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
856 AR8316_GCTRL_MTU, 9018 + 8 + 2);
857
858 /* Enable MIB counters */
859 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
860 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
861 AR8236_MIB_EN);
862 }
863
864 static const struct ar8xxx_chip ar8316_chip = {
865 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
866 .hw_init = ar8316_hw_init,
867 .init_globals = ar8316_init_globals,
868 .init_port = ar8216_init_port,
869 .setup_port = ar8216_setup_port,
870 .read_port_status = ar8216_read_port_status,
871 .atu_flush = ar8216_atu_flush,
872 .vtu_flush = ar8216_vtu_flush,
873 .vtu_load_vlan = ar8216_vtu_load_vlan,
874
875 .num_mibs = ARRAY_SIZE(ar8236_mibs),
876 .mib_decs = ar8236_mibs,
877 };
878
879 static u32
880 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
881 {
882 u32 t;
883
884 if (!cfg)
885 return 0;
886
887 t = 0;
888 switch (cfg->mode) {
889 case AR8327_PAD_NC:
890 break;
891
892 case AR8327_PAD_MAC2MAC_MII:
893 t = AR8327_PAD_MAC_MII_EN;
894 if (cfg->rxclk_sel)
895 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
896 if (cfg->txclk_sel)
897 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
898 break;
899
900 case AR8327_PAD_MAC2MAC_GMII:
901 t = AR8327_PAD_MAC_GMII_EN;
902 if (cfg->rxclk_sel)
903 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
904 if (cfg->txclk_sel)
905 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
906 break;
907
908 case AR8327_PAD_MAC_SGMII:
909 t = AR8327_PAD_SGMII_EN;
910
911 /*
912 * WAR for the QUalcomm Atheros AP136 board.
913 * It seems that RGMII TX/RX delay settings needs to be
914 * applied for SGMII mode as well, The ethernet is not
915 * reliable without this.
916 */
917 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
918 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
919 if (cfg->rxclk_delay_en)
920 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
921 if (cfg->txclk_delay_en)
922 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
923
924 if (cfg->sgmii_delay_en)
925 t |= AR8327_PAD_SGMII_DELAY_EN;
926
927 break;
928
929 case AR8327_PAD_MAC2PHY_MII:
930 t = AR8327_PAD_PHY_MII_EN;
931 if (cfg->rxclk_sel)
932 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
933 if (cfg->txclk_sel)
934 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
935 break;
936
937 case AR8327_PAD_MAC2PHY_GMII:
938 t = AR8327_PAD_PHY_GMII_EN;
939 if (cfg->pipe_rxclk_sel)
940 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
941 if (cfg->rxclk_sel)
942 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
943 if (cfg->txclk_sel)
944 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
945 break;
946
947 case AR8327_PAD_MAC_RGMII:
948 t = AR8327_PAD_RGMII_EN;
949 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
950 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
951 if (cfg->rxclk_delay_en)
952 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
953 if (cfg->txclk_delay_en)
954 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
955 break;
956
957 case AR8327_PAD_PHY_GMII:
958 t = AR8327_PAD_PHYX_GMII_EN;
959 break;
960
961 case AR8327_PAD_PHY_RGMII:
962 t = AR8327_PAD_PHYX_RGMII_EN;
963 break;
964
965 case AR8327_PAD_PHY_MII:
966 t = AR8327_PAD_PHYX_MII_EN;
967 break;
968 }
969
970 return t;
971 }
972
973 static void
974 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
975 {
976 switch (priv->chip_rev) {
977 case 1:
978 /* For 100M waveform */
979 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
980 /* Turn on Gigabit clock */
981 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
982 break;
983
984 case 2:
985 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
986 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
987 /* fallthrough */
988 case 4:
989 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
990 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
991
992 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
993 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
994 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
995 break;
996 }
997 }
998
999 static int
1000 ar8327_hw_init(struct ar8216_priv *priv)
1001 {
1002 struct ar8327_platform_data *pdata;
1003 struct ar8327_led_cfg *led_cfg;
1004 struct mii_bus *bus;
1005 u32 pos, new_pos;
1006 u32 t;
1007 int i;
1008
1009 pdata = priv->phy->dev.platform_data;
1010 if (!pdata)
1011 return -EINVAL;
1012
1013 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1014 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1015 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1016 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1017 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1018 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1019
1020 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1021 new_pos = pos;
1022
1023 led_cfg = pdata->led_cfg;
1024 if (led_cfg) {
1025 if (led_cfg->open_drain)
1026 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1027 else
1028 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1029
1030 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1031 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1032 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1033 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1034 }
1035
1036 if (new_pos != pos) {
1037 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1038 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1039 }
1040
1041 bus = priv->mii_bus;
1042 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1043 ar8327_phy_fixup(priv, i);
1044
1045 /* start aneg on the PHY */
1046 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1047 ADVERTISE_PAUSE_CAP |
1048 ADVERTISE_PAUSE_ASYM);
1049 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1050 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1051 }
1052
1053 msleep(1000);
1054
1055 return 0;
1056 }
1057
1058 static void
1059 ar8327_init_globals(struct ar8216_priv *priv)
1060 {
1061 u32 t;
1062
1063 /* enable CPU port and disable mirror port */
1064 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1065 AR8327_FWD_CTRL0_MIRROR_PORT;
1066 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1067
1068 /* forward multicast and broadcast frames to CPU */
1069 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1070 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1071 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1072 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1073
1074 /* setup MTU */
1075 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1076 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1077
1078 /* Enable MIB counters */
1079 ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1080 AR8327_MODULE_EN_MIB);
1081 }
1082
1083 static void
1084 ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
1085 struct ar8327_port_cfg *cfg)
1086 {
1087 u32 t;
1088
1089 if (!cfg || !cfg->force_link) {
1090 priv->write(priv, AR8327_REG_PORT_STATUS(port),
1091 AR8216_PORT_STATUS_LINK_AUTO);
1092 return;
1093 }
1094
1095 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1096 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1097 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1098 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1099
1100 switch (cfg->speed) {
1101 case AR8327_PORT_SPEED_10:
1102 t |= AR8216_PORT_SPEED_10M;
1103 break;
1104 case AR8327_PORT_SPEED_100:
1105 t |= AR8216_PORT_SPEED_100M;
1106 break;
1107 case AR8327_PORT_SPEED_1000:
1108 t |= AR8216_PORT_SPEED_1000M;
1109 break;
1110 }
1111
1112 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1113 }
1114
1115 static void
1116 ar8327_init_port(struct ar8216_priv *priv, int port)
1117 {
1118 struct ar8327_platform_data *pdata;
1119 struct ar8327_port_cfg *cfg;
1120 u32 t;
1121
1122 pdata = priv->phy->dev.platform_data;
1123
1124 if (pdata && port == AR8216_PORT_CPU)
1125 cfg = &pdata->port0_cfg;
1126 else if (pdata && port == 6)
1127 cfg = &pdata->port6_cfg;
1128 else
1129 cfg = NULL;
1130
1131 ar8327_config_port(priv, port, cfg);
1132
1133 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1134
1135 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1136 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1137 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1138
1139 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1140 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1141
1142 t = AR8327_PORT_LOOKUP_LEARN;
1143 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1144 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1145 }
1146
1147 static u32
1148 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1149 {
1150 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1151 }
1152
1153 static int
1154 ar8327_atu_flush(struct ar8216_priv *priv)
1155 {
1156 int ret;
1157
1158 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1159 AR8327_ATU_FUNC_BUSY, 0);
1160 if (!ret)
1161 priv->write(priv, AR8327_REG_ATU_FUNC,
1162 AR8327_ATU_FUNC_OP_FLUSH);
1163
1164 return ret;
1165 }
1166
1167 static void
1168 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1169 {
1170 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1171 AR8327_VTU_FUNC1_BUSY, 0))
1172 return;
1173
1174 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1175 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1176
1177 op |= AR8327_VTU_FUNC1_BUSY;
1178 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1179 }
1180
1181 static void
1182 ar8327_vtu_flush(struct ar8216_priv *priv)
1183 {
1184 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1185 }
1186
1187 static void
1188 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1189 {
1190 u32 op;
1191 u32 val;
1192 int i;
1193
1194 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1195 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1196 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1197 u32 mode;
1198
1199 if ((port_mask & BIT(i)) == 0)
1200 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1201 else if (priv->vlan == 0)
1202 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1203 else if (priv->vlan_tagged & BIT(i))
1204 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1205 else
1206 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1207
1208 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1209 }
1210 ar8327_vtu_op(priv, op, val);
1211 }
1212
1213 static void
1214 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1215 u32 members, u32 pvid)
1216 {
1217 u32 t;
1218 u32 mode;
1219
1220 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1221 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1222 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1223
1224 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1225 switch (egress) {
1226 case AR8216_OUT_KEEP:
1227 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1228 break;
1229 case AR8216_OUT_STRIP_VLAN:
1230 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1231 break;
1232 case AR8216_OUT_ADD_VLAN:
1233 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1234 break;
1235 }
1236
1237 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1238 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1239 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1240
1241 t = members;
1242 t |= AR8327_PORT_LOOKUP_LEARN;
1243 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1244 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1245 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1246 }
1247
1248 static const struct ar8xxx_chip ar8327_chip = {
1249 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1250 .hw_init = ar8327_hw_init,
1251 .init_globals = ar8327_init_globals,
1252 .init_port = ar8327_init_port,
1253 .setup_port = ar8327_setup_port,
1254 .read_port_status = ar8327_read_port_status,
1255 .atu_flush = ar8327_atu_flush,
1256 .vtu_flush = ar8327_vtu_flush,
1257 .vtu_load_vlan = ar8327_vtu_load_vlan,
1258
1259 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1260 .mib_decs = ar8236_mibs,
1261 };
1262
1263 static int
1264 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1265 struct switch_val *val)
1266 {
1267 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1268 priv->vlan = !!val->value.i;
1269 return 0;
1270 }
1271
1272 static int
1273 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1274 struct switch_val *val)
1275 {
1276 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1277 val->value.i = priv->vlan;
1278 return 0;
1279 }
1280
1281
1282 static int
1283 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1284 {
1285 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1286
1287 /* make sure no invalid PVIDs get set */
1288
1289 if (vlan >= dev->vlans)
1290 return -EINVAL;
1291
1292 priv->pvid[port] = vlan;
1293 return 0;
1294 }
1295
1296 static int
1297 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1298 {
1299 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1300 *vlan = priv->pvid[port];
1301 return 0;
1302 }
1303
1304 static int
1305 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1306 struct switch_val *val)
1307 {
1308 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1309 priv->vlan_id[val->port_vlan] = val->value.i;
1310 return 0;
1311 }
1312
1313 static int
1314 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1315 struct switch_val *val)
1316 {
1317 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1318 val->value.i = priv->vlan_id[val->port_vlan];
1319 return 0;
1320 }
1321
1322 static int
1323 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1324 struct switch_port_link *link)
1325 {
1326 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1327
1328 ar8216_read_port_link(priv, port, link);
1329 return 0;
1330 }
1331
1332 static int
1333 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1334 {
1335 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1336 u8 ports = priv->vlan_table[val->port_vlan];
1337 int i;
1338
1339 val->len = 0;
1340 for (i = 0; i < dev->ports; i++) {
1341 struct switch_port *p;
1342
1343 if (!(ports & (1 << i)))
1344 continue;
1345
1346 p = &val->value.ports[val->len++];
1347 p->id = i;
1348 if (priv->vlan_tagged & (1 << i))
1349 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1350 else
1351 p->flags = 0;
1352 }
1353 return 0;
1354 }
1355
1356 static int
1357 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1358 {
1359 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1360 u8 *vt = &priv->vlan_table[val->port_vlan];
1361 int i, j;
1362
1363 *vt = 0;
1364 for (i = 0; i < val->len; i++) {
1365 struct switch_port *p = &val->value.ports[i];
1366
1367 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1368 priv->vlan_tagged |= (1 << p->id);
1369 } else {
1370 priv->vlan_tagged &= ~(1 << p->id);
1371 priv->pvid[p->id] = val->port_vlan;
1372
1373 /* make sure that an untagged port does not
1374 * appear in other vlans */
1375 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1376 if (j == val->port_vlan)
1377 continue;
1378 priv->vlan_table[j] &= ~(1 << p->id);
1379 }
1380 }
1381
1382 *vt |= 1 << p->id;
1383 }
1384 return 0;
1385 }
1386
1387 static int
1388 ar8216_sw_hw_apply(struct switch_dev *dev)
1389 {
1390 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1391 u8 portmask[AR8X16_MAX_PORTS];
1392 int i, j;
1393
1394 mutex_lock(&priv->reg_mutex);
1395 /* flush all vlan translation unit entries */
1396 priv->chip->vtu_flush(priv);
1397
1398 memset(portmask, 0, sizeof(portmask));
1399 if (!priv->init) {
1400 /* calculate the port destination masks and load vlans
1401 * into the vlan translation unit */
1402 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1403 u8 vp = priv->vlan_table[j];
1404
1405 if (!vp)
1406 continue;
1407
1408 for (i = 0; i < dev->ports; i++) {
1409 u8 mask = (1 << i);
1410 if (vp & mask)
1411 portmask[i] |= vp & ~mask;
1412 }
1413
1414 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1415 priv->vlan_table[j]);
1416 }
1417 } else {
1418 /* vlan disabled:
1419 * isolate all ports, but connect them to the cpu port */
1420 for (i = 0; i < dev->ports; i++) {
1421 if (i == AR8216_PORT_CPU)
1422 continue;
1423
1424 portmask[i] = 1 << AR8216_PORT_CPU;
1425 portmask[AR8216_PORT_CPU] |= (1 << i);
1426 }
1427 }
1428
1429 /* update the port destination mask registers and tag settings */
1430 for (i = 0; i < dev->ports; i++) {
1431 int egress, ingress;
1432 int pvid;
1433
1434 if (priv->vlan) {
1435 pvid = priv->vlan_id[priv->pvid[i]];
1436 if (priv->vlan_tagged & (1 << i))
1437 egress = AR8216_OUT_ADD_VLAN;
1438 else
1439 egress = AR8216_OUT_STRIP_VLAN;
1440 ingress = AR8216_IN_SECURE;
1441 } else {
1442 pvid = i;
1443 egress = AR8216_OUT_KEEP;
1444 ingress = AR8216_IN_PORT_ONLY;
1445 }
1446
1447 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1448 pvid);
1449 }
1450 mutex_unlock(&priv->reg_mutex);
1451 return 0;
1452 }
1453
1454 static int
1455 ar8216_sw_reset_switch(struct switch_dev *dev)
1456 {
1457 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1458 int i;
1459
1460 mutex_lock(&priv->reg_mutex);
1461 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1462 offsetof(struct ar8216_priv, vlan));
1463
1464 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1465 priv->vlan_id[i] = i;
1466
1467 /* Configure all ports */
1468 for (i = 0; i < dev->ports; i++)
1469 priv->chip->init_port(priv, i);
1470
1471 priv->chip->init_globals(priv);
1472 mutex_unlock(&priv->reg_mutex);
1473
1474 return ar8216_sw_hw_apply(dev);
1475 }
1476
1477 static int
1478 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1479 const struct switch_attr *attr,
1480 struct switch_val *val)
1481 {
1482 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1483 unsigned int len;
1484 int ret;
1485
1486 if (!ar8xxx_has_mib_counters(priv))
1487 return -EOPNOTSUPP;
1488
1489 mutex_lock(&priv->mib_lock);
1490
1491 len = priv->dev.ports * priv->chip->num_mibs *
1492 sizeof(*priv->mib_stats);
1493 memset(priv->mib_stats, '\0', len);
1494 ret = ar8216_mib_flush(priv);
1495 if (ret)
1496 goto unlock;
1497
1498 ret = 0;
1499
1500 unlock:
1501 mutex_unlock(&priv->mib_lock);
1502 return ret;
1503 }
1504
1505 static int
1506 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1507 const struct switch_attr *attr,
1508 struct switch_val *val)
1509 {
1510 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1511 int port;
1512 int ret;
1513
1514 if (!ar8xxx_has_mib_counters(priv))
1515 return -EOPNOTSUPP;
1516
1517 port = val->port_vlan;
1518 if (port >= dev->ports)
1519 return -EINVAL;
1520
1521 mutex_lock(&priv->mib_lock);
1522 ret = ar8216_mib_capture(priv);
1523 if (ret)
1524 goto unlock;
1525
1526 ar8216_mib_fetch_port_stat(priv, port, true);
1527
1528 ret = 0;
1529
1530 unlock:
1531 mutex_unlock(&priv->mib_lock);
1532 return ret;
1533 }
1534
1535 static int
1536 ar8216_sw_get_port_mib(struct switch_dev *dev,
1537 const struct switch_attr *attr,
1538 struct switch_val *val)
1539 {
1540 struct ar8216_priv *priv = swdev_to_ar8216(dev);
1541 const struct ar8xxx_chip *chip = priv->chip;
1542 u64 *mib_stats;
1543 int port;
1544 int ret;
1545 char *buf = priv->buf;
1546 int i, len = 0;
1547
1548 if (!ar8xxx_has_mib_counters(priv))
1549 return -EOPNOTSUPP;
1550
1551 port = val->port_vlan;
1552 if (port >= dev->ports)
1553 return -EINVAL;
1554
1555 mutex_lock(&priv->mib_lock);
1556 ret = ar8216_mib_capture(priv);
1557 if (ret)
1558 goto unlock;
1559
1560 ar8216_mib_fetch_port_stat(priv, port, false);
1561
1562 len += snprintf(buf + len, sizeof(priv->buf) - len,
1563 "Port %d MIB counters\n",
1564 port);
1565
1566 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1567 for (i = 0; i < chip->num_mibs; i++)
1568 len += snprintf(buf + len, sizeof(priv->buf) - len,
1569 "%-12s: %llu\n",
1570 chip->mib_decs[i].name,
1571 mib_stats[i]);
1572
1573 val->value.s = buf;
1574 val->len = len;
1575
1576 ret = 0;
1577
1578 unlock:
1579 mutex_unlock(&priv->mib_lock);
1580 return ret;
1581 }
1582
1583 static struct switch_attr ar8216_globals[] = {
1584 {
1585 .type = SWITCH_TYPE_INT,
1586 .name = "enable_vlan",
1587 .description = "Enable VLAN mode",
1588 .set = ar8216_sw_set_vlan,
1589 .get = ar8216_sw_get_vlan,
1590 .max = 1
1591 },
1592 {
1593 .type = SWITCH_TYPE_NOVAL,
1594 .name = "reset_mibs",
1595 .description = "Reset all MIB counters",
1596 .set = ar8216_sw_set_reset_mibs,
1597 },
1598
1599 };
1600
1601 static struct switch_attr ar8216_port[] = {
1602 {
1603 .type = SWITCH_TYPE_NOVAL,
1604 .name = "reset_mib",
1605 .description = "Reset single port MIB counters",
1606 .set = ar8216_sw_set_port_reset_mib,
1607 },
1608 {
1609 .type = SWITCH_TYPE_STRING,
1610 .name = "mib",
1611 .description = "Get port's MIB counters",
1612 .set = NULL,
1613 .get = ar8216_sw_get_port_mib,
1614 },
1615 };
1616
1617 static struct switch_attr ar8216_vlan[] = {
1618 {
1619 .type = SWITCH_TYPE_INT,
1620 .name = "vid",
1621 .description = "VLAN ID (0-4094)",
1622 .set = ar8216_sw_set_vid,
1623 .get = ar8216_sw_get_vid,
1624 .max = 4094,
1625 },
1626 };
1627
1628 static const struct switch_dev_ops ar8216_sw_ops = {
1629 .attr_global = {
1630 .attr = ar8216_globals,
1631 .n_attr = ARRAY_SIZE(ar8216_globals),
1632 },
1633 .attr_port = {
1634 .attr = ar8216_port,
1635 .n_attr = ARRAY_SIZE(ar8216_port),
1636 },
1637 .attr_vlan = {
1638 .attr = ar8216_vlan,
1639 .n_attr = ARRAY_SIZE(ar8216_vlan),
1640 },
1641 .get_port_pvid = ar8216_sw_get_pvid,
1642 .set_port_pvid = ar8216_sw_set_pvid,
1643 .get_vlan_ports = ar8216_sw_get_ports,
1644 .set_vlan_ports = ar8216_sw_set_ports,
1645 .apply_config = ar8216_sw_hw_apply,
1646 .reset_switch = ar8216_sw_reset_switch,
1647 .get_port_link = ar8216_sw_get_port_link,
1648 };
1649
1650 static int
1651 ar8216_id_chip(struct ar8216_priv *priv)
1652 {
1653 u32 val;
1654 u16 id;
1655 int i;
1656
1657 val = priv->read(priv, AR8216_REG_CTRL);
1658 if (val == ~0)
1659 return -ENODEV;
1660
1661 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1662 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1663 u16 t;
1664
1665 val = priv->read(priv, AR8216_REG_CTRL);
1666 if (val == ~0)
1667 return -ENODEV;
1668
1669 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1670 if (t != id)
1671 return -ENODEV;
1672 }
1673
1674 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1675 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1676
1677 switch (priv->chip_ver) {
1678 case AR8XXX_VER_AR8216:
1679 priv->chip = &ar8216_chip;
1680 break;
1681 case AR8XXX_VER_AR8236:
1682 priv->chip = &ar8236_chip;
1683 break;
1684 case AR8XXX_VER_AR8316:
1685 priv->chip = &ar8316_chip;
1686 break;
1687 case AR8XXX_VER_AR8327:
1688 priv->mii_lo_first = true;
1689 priv->chip = &ar8327_chip;
1690 break;
1691 default:
1692 printk(KERN_DEBUG
1693 "ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1694 priv->chip_ver, priv->chip_rev);
1695
1696 return -ENODEV;
1697 }
1698
1699 return 0;
1700 }
1701
1702 static void
1703 ar8xxx_mib_work_func(struct work_struct *work)
1704 {
1705 struct ar8216_priv *priv;
1706 int err;
1707
1708 priv = container_of(work, struct ar8216_priv, mib_work.work);
1709
1710 mutex_lock(&priv->mib_lock);
1711
1712 err = ar8216_mib_capture(priv);
1713 if (err)
1714 goto next_port;
1715
1716 ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1717
1718 next_port:
1719 priv->mib_next_port++;
1720 if (priv->mib_next_port >= priv->dev.ports)
1721 priv->mib_next_port = 0;
1722
1723 mutex_unlock(&priv->mib_lock);
1724 schedule_delayed_work(&priv->mib_work,
1725 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1726 }
1727
1728 static int
1729 ar8xxx_mib_init(struct ar8216_priv *priv)
1730 {
1731 unsigned int len;
1732
1733 if (!ar8xxx_has_mib_counters(priv))
1734 return 0;
1735
1736 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1737
1738 len = priv->dev.ports * priv->chip->num_mibs *
1739 sizeof(*priv->mib_stats);
1740 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1741
1742 if (!priv->mib_stats)
1743 return -ENOMEM;
1744
1745 return 0;
1746 }
1747
1748 static void
1749 ar8xxx_mib_start(struct ar8216_priv *priv)
1750 {
1751 if (!ar8xxx_has_mib_counters(priv))
1752 return;
1753
1754 schedule_delayed_work(&priv->mib_work,
1755 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1756 }
1757
1758 static void
1759 ar8xxx_mib_stop(struct ar8216_priv *priv)
1760 {
1761 if (!ar8xxx_has_mib_counters(priv))
1762 return;
1763
1764 cancel_delayed_work(&priv->mib_work);
1765 }
1766
1767 static struct ar8216_priv *
1768 ar8xxx_create(void)
1769 {
1770 struct ar8216_priv *priv;
1771
1772 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1773 if (priv == NULL)
1774 return NULL;
1775
1776 mutex_init(&priv->reg_mutex);
1777 mutex_init(&priv->mib_lock);
1778 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1779
1780 return priv;
1781 }
1782
1783 static void
1784 ar8xxx_free(struct ar8216_priv *priv)
1785 {
1786 kfree(priv->mib_stats);
1787 kfree(priv);
1788 }
1789
1790 static struct ar8216_priv *
1791 ar8xxx_create_mii(struct mii_bus *bus)
1792 {
1793 struct ar8216_priv *priv;
1794
1795 priv = ar8xxx_create();
1796 if (priv) {
1797 priv->mii_bus = bus;
1798 priv->read = ar8216_mii_read;
1799 priv->write = ar8216_mii_write;
1800 }
1801
1802 return priv;
1803 }
1804
1805 static int
1806 ar8xxx_probe_switch(struct ar8216_priv *priv)
1807 {
1808 struct switch_dev *swdev;
1809 int ret;
1810
1811 ret = ar8216_id_chip(priv);
1812 if (ret)
1813 return ret;
1814
1815 swdev = &priv->dev;
1816 swdev->cpu_port = AR8216_PORT_CPU;
1817 swdev->ops = &ar8216_sw_ops;
1818
1819 if (chip_is_ar8316(priv)) {
1820 swdev->name = "Atheros AR8316";
1821 swdev->vlans = AR8X16_MAX_VLANS;
1822 swdev->ports = AR8216_NUM_PORTS;
1823 } else if (chip_is_ar8236(priv)) {
1824 swdev->name = "Atheros AR8236";
1825 swdev->vlans = AR8216_NUM_VLANS;
1826 swdev->ports = AR8216_NUM_PORTS;
1827 } else if (chip_is_ar8327(priv)) {
1828 swdev->name = "Atheros AR8327";
1829 swdev->vlans = AR8X16_MAX_VLANS;
1830 swdev->ports = AR8327_NUM_PORTS;
1831 } else {
1832 swdev->name = "Atheros AR8216";
1833 swdev->vlans = AR8216_NUM_VLANS;
1834 swdev->ports = AR8216_NUM_PORTS;
1835 }
1836
1837 ret = ar8xxx_mib_init(priv);
1838 if (ret)
1839 return ret;
1840
1841 return 0;
1842 }
1843
1844 static int
1845 ar8216_config_init(struct phy_device *pdev)
1846 {
1847 struct ar8216_priv *priv = pdev->priv;
1848 struct net_device *dev = pdev->attached_dev;
1849 struct switch_dev *swdev;
1850 int ret;
1851
1852 if (!priv) {
1853 priv = ar8xxx_create_mii(pdev->bus);
1854 if (priv == NULL)
1855 return -ENOMEM;
1856
1857 ret = ar8xxx_probe_switch(priv);
1858 if (ret)
1859 goto err_free_priv;
1860 }
1861
1862 priv->phy = pdev;
1863
1864 if (pdev->addr != 0) {
1865 if (chip_is_ar8316(priv)) {
1866 /* check if we're attaching to the switch twice */
1867 pdev = pdev->bus->phy_map[0];
1868 if (!pdev) {
1869 ar8xxx_free(priv);
1870 return 0;
1871 }
1872
1873 /* switch device has not been initialized, reuse priv */
1874 if (!pdev->priv) {
1875 priv->port4_phy = true;
1876 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1877 pdev->priv = priv;
1878 return 0;
1879 }
1880
1881 ar8xxx_free(priv);
1882
1883 /* switch device has been initialized, reinit */
1884 priv = pdev->priv;
1885 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1886 priv->initialized = false;
1887 priv->port4_phy = true;
1888 ar8316_hw_init(priv);
1889 return 0;
1890 }
1891
1892 ar8xxx_free(priv);
1893 return 0;
1894 }
1895
1896 pdev->priv = priv;
1897
1898 swdev = &priv->dev;
1899 ret = register_switch(swdev, pdev->attached_dev);
1900 if (ret)
1901 goto err_free_priv;
1902
1903 printk(KERN_INFO "%s: %s switch driver attached.\n",
1904 pdev->attached_dev->name, swdev->name);
1905
1906 priv->init = true;
1907
1908 ret = priv->chip->hw_init(priv);
1909 if (ret)
1910 goto err_unregister_switch;
1911
1912 ret = ar8216_sw_reset_switch(&priv->dev);
1913 if (ret)
1914 goto err_unregister_switch;
1915
1916 /* VID fixup only needed on ar8216 */
1917 if (chip_is_ar8216(priv)) {
1918 dev->phy_ptr = priv;
1919 dev->priv_flags |= IFF_NO_IP_ALIGN;
1920 dev->eth_mangle_rx = ar8216_mangle_rx;
1921 dev->eth_mangle_tx = ar8216_mangle_tx;
1922 }
1923
1924 priv->init = false;
1925
1926 ar8xxx_mib_start(priv);
1927
1928 return 0;
1929
1930 err_unregister_switch:
1931 unregister_switch(&priv->dev);
1932 err_free_priv:
1933 ar8xxx_free(priv);
1934 pdev->priv = NULL;
1935 return ret;
1936 }
1937
1938 static int
1939 ar8216_read_status(struct phy_device *phydev)
1940 {
1941 struct ar8216_priv *priv = phydev->priv;
1942 struct switch_port_link link;
1943 int ret;
1944
1945 if (phydev->addr != 0)
1946 return genphy_read_status(phydev);
1947
1948 ar8216_read_port_link(priv, phydev->addr, &link);
1949 phydev->link = !!link.link;
1950 if (!phydev->link)
1951 return 0;
1952
1953 switch (link.speed) {
1954 case SWITCH_PORT_SPEED_10:
1955 phydev->speed = SPEED_10;
1956 break;
1957 case SWITCH_PORT_SPEED_100:
1958 phydev->speed = SPEED_100;
1959 break;
1960 case SWITCH_PORT_SPEED_1000:
1961 phydev->speed = SPEED_1000;
1962 break;
1963 default:
1964 phydev->speed = 0;
1965 }
1966 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1967
1968 /* flush the address translation unit */
1969 mutex_lock(&priv->reg_mutex);
1970 ret = priv->chip->atu_flush(priv);
1971 mutex_unlock(&priv->reg_mutex);
1972
1973 phydev->state = PHY_RUNNING;
1974 netif_carrier_on(phydev->attached_dev);
1975 phydev->adjust_link(phydev->attached_dev);
1976
1977 return ret;
1978 }
1979
1980 static int
1981 ar8216_config_aneg(struct phy_device *phydev)
1982 {
1983 if (phydev->addr == 0)
1984 return 0;
1985
1986 return genphy_config_aneg(phydev);
1987 }
1988
1989 static const u32 ar8xxx_phy_ids[] = {
1990 0x004dd033,
1991 0x004dd041,
1992 0x004dd042,
1993 };
1994
1995 static bool
1996 ar8xxx_phy_match(u32 phy_id)
1997 {
1998 int i;
1999
2000 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2001 if (phy_id == ar8xxx_phy_ids[i])
2002 return true;
2003
2004 return false;
2005 }
2006
2007 static bool
2008 ar8xxx_is_possible(struct mii_bus *bus)
2009 {
2010 unsigned i;
2011
2012 for (i = 0; i < 4; i++) {
2013 u32 phy_id;
2014
2015 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2016 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2017 if (!ar8xxx_phy_match(phy_id)) {
2018 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2019 dev_name(&bus->dev), i, phy_id);
2020 return false;
2021 }
2022 }
2023
2024 return true;
2025 }
2026
2027 static int
2028 ar8216_probe(struct phy_device *pdev)
2029 {
2030 struct ar8216_priv *priv;
2031 int ret;
2032
2033 /* skip PHYs at unused adresses */
2034 if (pdev->addr != 0 && pdev->addr != 4)
2035 return -ENODEV;
2036
2037 if (!ar8xxx_is_possible(pdev->bus))
2038 return -ENODEV;
2039
2040 priv = ar8xxx_create_mii(pdev->bus);
2041 if (priv == NULL)
2042 return -ENOMEM;
2043
2044 priv->phy = pdev;
2045
2046 ret = ar8xxx_probe_switch(priv);
2047 if (ret)
2048 goto out;
2049
2050 if (pdev->addr == 0) {
2051 if (ar8xxx_has_gige(priv)) {
2052 pdev->supported = SUPPORTED_1000baseT_Full;
2053 pdev->advertising = ADVERTISED_1000baseT_Full;
2054 } else {
2055 pdev->supported = SUPPORTED_100baseT_Full;
2056 pdev->advertising = ADVERTISED_100baseT_Full;
2057 }
2058 } else {
2059 if (ar8xxx_has_gige(priv)) {
2060 pdev->supported |= SUPPORTED_1000baseT_Full;
2061 pdev->advertising |= ADVERTISED_1000baseT_Full;
2062 }
2063 }
2064
2065 ret = 0;
2066
2067 out:
2068 ar8xxx_free(priv);
2069 return ret;
2070 }
2071
2072 static void
2073 ar8216_detach(struct phy_device *pdev)
2074 {
2075 struct net_device *dev = pdev->attached_dev;
2076
2077 if (!dev)
2078 return;
2079
2080 dev->phy_ptr = NULL;
2081 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2082 dev->eth_mangle_rx = NULL;
2083 dev->eth_mangle_tx = NULL;
2084 }
2085
2086 static void
2087 ar8216_remove(struct phy_device *pdev)
2088 {
2089 struct ar8216_priv *priv = pdev->priv;
2090
2091 if (!priv)
2092 return;
2093
2094 pdev->priv = NULL;
2095
2096 if (pdev->addr == 0)
2097 unregister_switch(&priv->dev);
2098
2099 ar8xxx_mib_stop(priv);
2100 ar8xxx_free(priv);
2101 }
2102
2103 static struct phy_driver ar8216_driver = {
2104 .phy_id = 0x004d0000,
2105 .name = "Atheros AR8216/AR8236/AR8316",
2106 .phy_id_mask = 0xffff0000,
2107 .features = PHY_BASIC_FEATURES,
2108 .probe = ar8216_probe,
2109 .remove = ar8216_remove,
2110 .detach = ar8216_detach,
2111 .config_init = &ar8216_config_init,
2112 .config_aneg = &ar8216_config_aneg,
2113 .read_status = &ar8216_read_status,
2114 .driver = { .owner = THIS_MODULE },
2115 };
2116
2117 int __init
2118 ar8216_init(void)
2119 {
2120 return phy_driver_register(&ar8216_driver);
2121 }
2122
2123 void __exit
2124 ar8216_exit(void)
2125 {
2126 phy_driver_unregister(&ar8216_driver);
2127 }
2128
2129 module_init(ar8216_init);
2130 module_exit(ar8216_exit);
2131 MODULE_LICENSE("GPL");
2132
OpenWrt SVN history