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generic: ar8216: add mii_bus field to struct ar8216_priv
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8216_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8216_priv *priv);
67 void (*init_globals)(struct ar8216_priv *priv);
68 void (*init_port)(struct ar8216_priv *priv, int port);
69 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72 int (*atu_flush)(struct ar8216_priv *priv);
73 void (*vtu_flush)(struct ar8216_priv *priv);
74 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8216_priv {
81 struct switch_dev dev;
82 struct mii_bus *mii_bus;
83 struct phy_device *phy;
84 u32 (*read)(struct ar8216_priv *priv, int reg);
85 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
86 const struct net_device_ops *ndo_old;
87 struct net_device_ops ndo;
88 struct mutex reg_mutex;
89 u8 chip_ver;
90 u8 chip_rev;
91 const struct ar8xxx_chip *chip;
92 bool initialized;
93 bool port4_phy;
94 char buf[2048];
95
96 bool init;
97 bool mii_lo_first;
98
99 struct mutex mib_lock;
100 struct delayed_work mib_work;
101 int mib_next_port;
102 u64 *mib_stats;
103
104 /* all fields below are cleared on reset */
105 bool vlan;
106 u16 vlan_id[AR8X16_MAX_VLANS];
107 u8 vlan_table[AR8X16_MAX_VLANS];
108 u8 vlan_tagged;
109 u16 pvid[AR8X16_MAX_PORTS];
110 };
111
112 #define MIB_DESC(_s , _o, _n) \
113 { \
114 .size = (_s), \
115 .offset = (_o), \
116 .name = (_n), \
117 }
118
119 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
120 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
121 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
122 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
123 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
124 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
125 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
126 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
127 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
128 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
129 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
130 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
131 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
132 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
133 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
134 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
135 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
136 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
137 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
138 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
139 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
140 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
141 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
142 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
143 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
144 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
145 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
146 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
147 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
148 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
149 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
150 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
151 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
152 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
153 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
154 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
155 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
156 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
157 };
158
159 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
160 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
161 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
162 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
163 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
164 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
165 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
166 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
167 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
168 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
169 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
170 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
172 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
173 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
174 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
175 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
176 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
177 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
178 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
179 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
180 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
181 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
182 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
183 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
184 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
185 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
186 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
188 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
189 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
190 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
191 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
192 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
193 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
194 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
195 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
196 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
197 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
198 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
199 };
200
201 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
202
203 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
204 {
205 return priv->chip->caps & AR8XXX_CAP_GIGE;
206 }
207
208 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
209 {
210 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
211 }
212
213 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
214 {
215 return priv->chip_ver == AR8XXX_VER_AR8216;
216 }
217
218 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
219 {
220 return priv->chip_ver == AR8XXX_VER_AR8236;
221 }
222
223 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
224 {
225 return priv->chip_ver == AR8XXX_VER_AR8316;
226 }
227
228 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
229 {
230 return priv->chip_ver == AR8XXX_VER_AR8327;
231 }
232
233 static inline void
234 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
235 {
236 regaddr >>= 1;
237 *r1 = regaddr & 0x1e;
238
239 regaddr >>= 5;
240 *r2 = regaddr & 0x7;
241
242 regaddr >>= 3;
243 *page = regaddr & 0x1ff;
244 }
245
246 static u32
247 ar8216_mii_read(struct ar8216_priv *priv, int reg)
248 {
249 struct mii_bus *bus = priv->mii_bus;
250 u16 r1, r2, page;
251 u16 lo, hi;
252
253 split_addr((u32) reg, &r1, &r2, &page);
254
255 mutex_lock(&bus->mdio_lock);
256
257 bus->write(bus, 0x18, 0, page);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo = bus->read(bus, 0x10 | r2, r1);
260 hi = bus->read(bus, 0x10 | r2, r1 + 1);
261
262 mutex_unlock(&bus->mdio_lock);
263
264 return (hi << 16) | lo;
265 }
266
267 static void
268 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
269 {
270 struct mii_bus *bus = priv->mii_bus;
271 u16 r1, r2, r3;
272 u16 lo, hi;
273
274 split_addr((u32) reg, &r1, &r2, &r3);
275 lo = val & 0xffff;
276 hi = (u16) (val >> 16);
277
278 mutex_lock(&bus->mdio_lock);
279
280 bus->write(bus, 0x18, 0, r3);
281 usleep_range(1000, 2000); /* wait for the page switch to propagate */
282 if (priv->mii_lo_first) {
283 bus->write(bus, 0x10 | r2, r1, lo);
284 bus->write(bus, 0x10 | r2, r1 + 1, hi);
285 } else {
286 bus->write(bus, 0x10 | r2, r1 + 1, hi);
287 bus->write(bus, 0x10 | r2, r1, lo);
288 }
289
290 mutex_unlock(&bus->mdio_lock);
291 }
292
293 static void
294 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
295 u16 dbg_addr, u16 dbg_data)
296 {
297 struct mii_bus *bus = priv->mii_bus;
298
299 mutex_lock(&bus->mdio_lock);
300 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
301 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
302 mutex_unlock(&bus->mdio_lock);
303 }
304
305 static void
306 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
307 {
308 struct mii_bus *bus = priv->mii_bus;
309
310 mutex_lock(&bus->mdio_lock);
311 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
312 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
313 mutex_unlock(&bus->mdio_lock);
314 }
315
316 static u32
317 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
318 {
319 u32 v;
320
321 lockdep_assert_held(&priv->reg_mutex);
322
323 v = priv->read(priv, reg);
324 v &= ~mask;
325 v |= val;
326 priv->write(priv, reg, v);
327
328 return v;
329 }
330
331 static inline void
332 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
333 {
334 u32 v;
335
336 lockdep_assert_held(&priv->reg_mutex);
337
338 v = priv->read(priv, reg);
339 v |= val;
340 priv->write(priv, reg, v);
341 }
342
343 static int
344 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
345 unsigned timeout)
346 {
347 int i;
348
349 for (i = 0; i < timeout; i++) {
350 u32 t;
351
352 t = priv->read(priv, reg);
353 if ((t & mask) == val)
354 return 0;
355
356 usleep_range(1000, 2000);
357 }
358
359 return -ETIMEDOUT;
360 }
361
362 static int
363 ar8216_mib_op(struct ar8216_priv *priv, u32 op)
364 {
365 unsigned mib_func;
366 int ret;
367
368 lockdep_assert_held(&priv->mib_lock);
369
370 if (chip_is_ar8327(priv))
371 mib_func = AR8327_REG_MIB_FUNC;
372 else
373 mib_func = AR8216_REG_MIB_FUNC;
374
375 mutex_lock(&priv->reg_mutex);
376 /* Capture the hardware statistics for all ports */
377 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
378 mutex_unlock(&priv->reg_mutex);
379
380 /* Wait for the capturing to complete. */
381 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
382 if (ret)
383 goto out;
384
385 ret = 0;
386
387 out:
388 return ret;
389 }
390
391 static int
392 ar8216_mib_capture(struct ar8216_priv *priv)
393 {
394 return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
395 }
396
397 static int
398 ar8216_mib_flush(struct ar8216_priv *priv)
399 {
400 return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
401 }
402
403 static void
404 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
405 {
406 unsigned int base;
407 u64 *mib_stats;
408 int i;
409
410 WARN_ON(port >= priv->dev.ports);
411
412 lockdep_assert_held(&priv->mib_lock);
413
414 if (chip_is_ar8327(priv))
415 base = AR8327_REG_PORT_STATS_BASE(port);
416 else if (chip_is_ar8236(priv) ||
417 chip_is_ar8316(priv))
418 base = AR8236_REG_PORT_STATS_BASE(port);
419 else
420 base = AR8216_REG_PORT_STATS_BASE(port);
421
422 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
423 for (i = 0; i < priv->chip->num_mibs; i++) {
424 const struct ar8xxx_mib_desc *mib;
425 u64 t;
426
427 mib = &priv->chip->mib_decs[i];
428 t = priv->read(priv, base + mib->offset);
429 if (mib->size == 2) {
430 u64 hi;
431
432 hi = priv->read(priv, base + mib->offset + 4);
433 t |= hi << 32;
434 }
435
436 if (flush)
437 mib_stats[i] = 0;
438 else
439 mib_stats[i] += t;
440 }
441 }
442
443 static void
444 ar8216_read_port_link(struct ar8216_priv *priv, int port,
445 struct switch_port_link *link)
446 {
447 u32 status;
448 u32 speed;
449
450 memset(link, '\0', sizeof(*link));
451
452 status = priv->chip->read_port_status(priv, port);
453
454 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
455 if (link->aneg) {
456 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
457 if (!link->link)
458 return;
459 } else {
460 link->link = true;
461 }
462
463 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
464 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
465 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
466
467 speed = (status & AR8216_PORT_STATUS_SPEED) >>
468 AR8216_PORT_STATUS_SPEED_S;
469
470 switch (speed) {
471 case AR8216_PORT_SPEED_10M:
472 link->speed = SWITCH_PORT_SPEED_10;
473 break;
474 case AR8216_PORT_SPEED_100M:
475 link->speed = SWITCH_PORT_SPEED_100;
476 break;
477 case AR8216_PORT_SPEED_1000M:
478 link->speed = SWITCH_PORT_SPEED_1000;
479 break;
480 default:
481 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
482 break;
483 }
484 }
485
486 static struct sk_buff *
487 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
488 {
489 struct ar8216_priv *priv = dev->phy_ptr;
490 unsigned char *buf;
491
492 if (unlikely(!priv))
493 goto error;
494
495 if (!priv->vlan)
496 goto send;
497
498 if (unlikely(skb_headroom(skb) < 2)) {
499 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
500 goto error;
501 }
502
503 buf = skb_push(skb, 2);
504 buf[0] = 0x10;
505 buf[1] = 0x80;
506
507 send:
508 return skb;
509
510 error:
511 dev_kfree_skb_any(skb);
512 return NULL;
513 }
514
515 static void
516 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
517 {
518 struct ar8216_priv *priv;
519 unsigned char *buf;
520 int port, vlan;
521
522 priv = dev->phy_ptr;
523 if (!priv)
524 return;
525
526 /* don't strip the header if vlan mode is disabled */
527 if (!priv->vlan)
528 return;
529
530 /* strip header, get vlan id */
531 buf = skb->data;
532 skb_pull(skb, 2);
533
534 /* check for vlan header presence */
535 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
536 return;
537
538 port = buf[0] & 0xf;
539
540 /* no need to fix up packets coming from a tagged source */
541 if (priv->vlan_tagged & (1 << port))
542 return;
543
544 /* lookup port vid from local table, the switch passes an invalid vlan id */
545 vlan = priv->vlan_id[priv->pvid[port]];
546
547 buf[14 + 2] &= 0xf0;
548 buf[14 + 2] |= vlan >> 8;
549 buf[15 + 2] = vlan & 0xff;
550 }
551
552 static int
553 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
554 {
555 int timeout = 20;
556 u32 t = 0;
557
558 while (1) {
559 t = priv->read(priv, reg);
560 if ((t & mask) == val)
561 return 0;
562
563 if (timeout-- <= 0)
564 break;
565
566 udelay(10);
567 }
568
569 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
570 (unsigned int) reg, t, mask, val);
571 return -ETIMEDOUT;
572 }
573
574 static void
575 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
576 {
577 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
578 return;
579 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
580 val &= AR8216_VTUDATA_MEMBER;
581 val |= AR8216_VTUDATA_VALID;
582 priv->write(priv, AR8216_REG_VTU_DATA, val);
583 }
584 op |= AR8216_VTU_ACTIVE;
585 priv->write(priv, AR8216_REG_VTU, op);
586 }
587
588 static void
589 ar8216_vtu_flush(struct ar8216_priv *priv)
590 {
591 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
592 }
593
594 static void
595 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
596 {
597 u32 op;
598
599 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
600 ar8216_vtu_op(priv, op, port_mask);
601 }
602
603 static int
604 ar8216_atu_flush(struct ar8216_priv *priv)
605 {
606 int ret;
607
608 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
609 if (!ret)
610 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
611
612 return ret;
613 }
614
615 static u32
616 ar8216_read_port_status(struct ar8216_priv *priv, int port)
617 {
618 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
619 }
620
621 static void
622 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
623 u32 members, u32 pvid)
624 {
625 u32 header;
626
627 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
628 header = AR8216_PORT_CTRL_HEADER;
629 else
630 header = 0;
631
632 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
633 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
634 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
635 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
636 AR8216_PORT_CTRL_LEARN | header |
637 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
638 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
639
640 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
641 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
642 AR8216_PORT_VLAN_DEFAULT_ID,
643 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
644 (ingress << AR8216_PORT_VLAN_MODE_S) |
645 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
646 }
647
648 static int
649 ar8216_hw_init(struct ar8216_priv *priv)
650 {
651 return 0;
652 }
653
654 static void
655 ar8216_init_globals(struct ar8216_priv *priv)
656 {
657 /* standard atheros magic */
658 priv->write(priv, 0x38, 0xc000050e);
659
660 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
661 AR8216_GCTRL_MTU, 1518 + 8 + 2);
662 }
663
664 static void
665 ar8216_init_port(struct ar8216_priv *priv, int port)
666 {
667 /* Enable port learning and tx */
668 priv->write(priv, AR8216_REG_PORT_CTRL(port),
669 AR8216_PORT_CTRL_LEARN |
670 (4 << AR8216_PORT_CTRL_STATE_S));
671
672 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
673
674 if (port == AR8216_PORT_CPU) {
675 priv->write(priv, AR8216_REG_PORT_STATUS(port),
676 AR8216_PORT_STATUS_LINK_UP |
677 (ar8xxx_has_gige(priv) ?
678 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
679 AR8216_PORT_STATUS_TXMAC |
680 AR8216_PORT_STATUS_RXMAC |
681 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
682 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
683 AR8216_PORT_STATUS_DUPLEX);
684 } else {
685 priv->write(priv, AR8216_REG_PORT_STATUS(port),
686 AR8216_PORT_STATUS_LINK_AUTO);
687 }
688 }
689
690 static const struct ar8xxx_chip ar8216_chip = {
691 .caps = AR8XXX_CAP_MIB_COUNTERS,
692
693 .hw_init = ar8216_hw_init,
694 .init_globals = ar8216_init_globals,
695 .init_port = ar8216_init_port,
696 .setup_port = ar8216_setup_port,
697 .read_port_status = ar8216_read_port_status,
698 .atu_flush = ar8216_atu_flush,
699 .vtu_flush = ar8216_vtu_flush,
700 .vtu_load_vlan = ar8216_vtu_load_vlan,
701
702 .num_mibs = ARRAY_SIZE(ar8216_mibs),
703 .mib_decs = ar8216_mibs,
704 };
705
706 static void
707 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
708 u32 members, u32 pvid)
709 {
710 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
711 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
712 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
713 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
714 AR8216_PORT_CTRL_LEARN |
715 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
716 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
717
718 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
719 AR8236_PORT_VLAN_DEFAULT_ID,
720 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
721
722 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
723 AR8236_PORT_VLAN2_VLAN_MODE |
724 AR8236_PORT_VLAN2_MEMBER,
725 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
726 (members << AR8236_PORT_VLAN2_MEMBER_S));
727 }
728
729 static int
730 ar8236_hw_init(struct ar8216_priv *priv)
731 {
732 int i;
733 struct mii_bus *bus;
734
735 if (priv->initialized)
736 return 0;
737
738 /* Initialize the PHYs */
739 bus = priv->mii_bus;
740 for (i = 0; i < 5; i++) {
741 mdiobus_write(bus, i, MII_ADVERTISE,
742 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
743 ADVERTISE_PAUSE_ASYM);
744 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
745 }
746 msleep(1000);
747
748 priv->initialized = true;
749 return 0;
750 }
751
752 static void
753 ar8236_init_globals(struct ar8216_priv *priv)
754 {
755 /* enable jumbo frames */
756 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
757 AR8316_GCTRL_MTU, 9018 + 8 + 2);
758
759 /* Enable MIB counters */
760 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
761 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
762 AR8236_MIB_EN);
763 }
764
765 static const struct ar8xxx_chip ar8236_chip = {
766 .caps = AR8XXX_CAP_MIB_COUNTERS,
767 .hw_init = ar8236_hw_init,
768 .init_globals = ar8236_init_globals,
769 .init_port = ar8216_init_port,
770 .setup_port = ar8236_setup_port,
771 .read_port_status = ar8216_read_port_status,
772 .atu_flush = ar8216_atu_flush,
773 .vtu_flush = ar8216_vtu_flush,
774 .vtu_load_vlan = ar8216_vtu_load_vlan,
775
776 .num_mibs = ARRAY_SIZE(ar8236_mibs),
777 .mib_decs = ar8236_mibs,
778 };
779
780 static int
781 ar8316_hw_init(struct ar8216_priv *priv)
782 {
783 int i;
784 u32 val, newval;
785 struct mii_bus *bus;
786
787 val = priv->read(priv, 0x8);
788
789 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
790 if (priv->port4_phy) {
791 /* value taken from Ubiquiti RouterStation Pro */
792 newval = 0x81461bea;
793 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
794 } else {
795 newval = 0x01261be2;
796 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
797 }
798 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
799 /* value taken from AVM Fritz!Box 7390 sources */
800 newval = 0x010e5b71;
801 } else {
802 /* no known value for phy interface */
803 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
804 priv->phy->interface);
805 return -EINVAL;
806 }
807
808 if (val == newval)
809 goto out;
810
811 priv->write(priv, 0x8, newval);
812
813 /* Initialize the ports */
814 bus = priv->mii_bus;
815 for (i = 0; i < 5; i++) {
816 if ((i == 4) && priv->port4_phy &&
817 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
818 /* work around for phy4 rgmii mode */
819 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
820 /* rx delay */
821 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
822 /* tx delay */
823 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
824 msleep(1000);
825 }
826
827 /* initialize the port itself */
828 mdiobus_write(bus, i, MII_ADVERTISE,
829 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
830 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
831 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
832 msleep(1000);
833 }
834
835 out:
836 priv->initialized = true;
837 return 0;
838 }
839
840 static void
841 ar8316_init_globals(struct ar8216_priv *priv)
842 {
843 /* standard atheros magic */
844 priv->write(priv, 0x38, 0xc000050e);
845
846 /* enable cpu port to receive multicast and broadcast frames */
847 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
848
849 /* enable jumbo frames */
850 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
851 AR8316_GCTRL_MTU, 9018 + 8 + 2);
852
853 /* Enable MIB counters */
854 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
855 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
856 AR8236_MIB_EN);
857 }
858
859 static const struct ar8xxx_chip ar8316_chip = {
860 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
861 .hw_init = ar8316_hw_init,
862 .init_globals = ar8316_init_globals,
863 .init_port = ar8216_init_port,
864 .setup_port = ar8216_setup_port,
865 .read_port_status = ar8216_read_port_status,
866 .atu_flush = ar8216_atu_flush,
867 .vtu_flush = ar8216_vtu_flush,
868 .vtu_load_vlan = ar8216_vtu_load_vlan,
869
870 .num_mibs = ARRAY_SIZE(ar8236_mibs),
871 .mib_decs = ar8236_mibs,
872 };
873
874 static u32
875 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
876 {
877 u32 t;
878
879 if (!cfg)
880 return 0;
881
882 t = 0;
883 switch (cfg->mode) {
884 case AR8327_PAD_NC:
885 break;
886
887 case AR8327_PAD_MAC2MAC_MII:
888 t = AR8327_PAD_MAC_MII_EN;
889 if (cfg->rxclk_sel)
890 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
891 if (cfg->txclk_sel)
892 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
893 break;
894
895 case AR8327_PAD_MAC2MAC_GMII:
896 t = AR8327_PAD_MAC_GMII_EN;
897 if (cfg->rxclk_sel)
898 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
899 if (cfg->txclk_sel)
900 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
901 break;
902
903 case AR8327_PAD_MAC_SGMII:
904 t = AR8327_PAD_SGMII_EN;
905
906 /*
907 * WAR for the QUalcomm Atheros AP136 board.
908 * It seems that RGMII TX/RX delay settings needs to be
909 * applied for SGMII mode as well, The ethernet is not
910 * reliable without this.
911 */
912 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
913 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
914 if (cfg->rxclk_delay_en)
915 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
916 if (cfg->txclk_delay_en)
917 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
918
919 if (cfg->sgmii_delay_en)
920 t |= AR8327_PAD_SGMII_DELAY_EN;
921
922 break;
923
924 case AR8327_PAD_MAC2PHY_MII:
925 t = AR8327_PAD_PHY_MII_EN;
926 if (cfg->rxclk_sel)
927 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
928 if (cfg->txclk_sel)
929 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
930 break;
931
932 case AR8327_PAD_MAC2PHY_GMII:
933 t = AR8327_PAD_PHY_GMII_EN;
934 if (cfg->pipe_rxclk_sel)
935 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
936 if (cfg->rxclk_sel)
937 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
938 if (cfg->txclk_sel)
939 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
940 break;
941
942 case AR8327_PAD_MAC_RGMII:
943 t = AR8327_PAD_RGMII_EN;
944 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
945 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
946 if (cfg->rxclk_delay_en)
947 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
948 if (cfg->txclk_delay_en)
949 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
950 break;
951
952 case AR8327_PAD_PHY_GMII:
953 t = AR8327_PAD_PHYX_GMII_EN;
954 break;
955
956 case AR8327_PAD_PHY_RGMII:
957 t = AR8327_PAD_PHYX_RGMII_EN;
958 break;
959
960 case AR8327_PAD_PHY_MII:
961 t = AR8327_PAD_PHYX_MII_EN;
962 break;
963 }
964
965 return t;
966 }
967
968 static void
969 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
970 {
971 switch (priv->chip_rev) {
972 case 1:
973 /* For 100M waveform */
974 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
975 /* Turn on Gigabit clock */
976 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
977 break;
978
979 case 2:
980 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
981 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
982 /* fallthrough */
983 case 4:
984 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
985 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
986
987 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
988 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
989 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
990 break;
991 }
992 }
993
994 static int
995 ar8327_hw_init(struct ar8216_priv *priv)
996 {
997 struct ar8327_platform_data *pdata;
998 struct ar8327_led_cfg *led_cfg;
999 struct mii_bus *bus;
1000 u32 pos, new_pos;
1001 u32 t;
1002 int i;
1003
1004 pdata = priv->phy->dev.platform_data;
1005 if (!pdata)
1006 return -EINVAL;
1007
1008 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1009 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1010 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1011 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1012 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1013 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1014
1015 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1016 new_pos = pos;
1017
1018 led_cfg = pdata->led_cfg;
1019 if (led_cfg) {
1020 if (led_cfg->open_drain)
1021 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1022 else
1023 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1024
1025 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1026 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1027 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1028 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1029 }
1030
1031 if (new_pos != pos) {
1032 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1033 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1034 }
1035
1036 bus = priv->mii_bus;
1037 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1038 ar8327_phy_fixup(priv, i);
1039
1040 /* start aneg on the PHY */
1041 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1042 ADVERTISE_PAUSE_CAP |
1043 ADVERTISE_PAUSE_ASYM);
1044 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1045 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1046 }
1047
1048 msleep(1000);
1049
1050 return 0;
1051 }
1052
1053 static void
1054 ar8327_init_globals(struct ar8216_priv *priv)
1055 {
1056 u32 t;
1057
1058 /* enable CPU port and disable mirror port */
1059 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1060 AR8327_FWD_CTRL0_MIRROR_PORT;
1061 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1062
1063 /* forward multicast and broadcast frames to CPU */
1064 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1065 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1066 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1067 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1068
1069 /* setup MTU */
1070 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1071 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1072
1073 /* Enable MIB counters */
1074 ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1075 AR8327_MODULE_EN_MIB);
1076 }
1077
1078 static void
1079 ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
1080 struct ar8327_port_cfg *cfg)
1081 {
1082 u32 t;
1083
1084 if (!cfg || !cfg->force_link) {
1085 priv->write(priv, AR8327_REG_PORT_STATUS(port),
1086 AR8216_PORT_STATUS_LINK_AUTO);
1087 return;
1088 }
1089
1090 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1091 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1092 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1093 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1094
1095 switch (cfg->speed) {
1096 case AR8327_PORT_SPEED_10:
1097 t |= AR8216_PORT_SPEED_10M;
1098 break;
1099 case AR8327_PORT_SPEED_100:
1100 t |= AR8216_PORT_SPEED_100M;
1101 break;
1102 case AR8327_PORT_SPEED_1000:
1103 t |= AR8216_PORT_SPEED_1000M;
1104 break;
1105 }
1106
1107 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1108 }
1109
1110 static void
1111 ar8327_init_port(struct ar8216_priv *priv, int port)
1112 {
1113 struct ar8327_platform_data *pdata;
1114 struct ar8327_port_cfg *cfg;
1115 u32 t;
1116
1117 pdata = priv->phy->dev.platform_data;
1118
1119 if (pdata && port == AR8216_PORT_CPU)
1120 cfg = &pdata->port0_cfg;
1121 else if (pdata && port == 6)
1122 cfg = &pdata->port6_cfg;
1123 else
1124 cfg = NULL;
1125
1126 ar8327_config_port(priv, port, cfg);
1127
1128 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1129
1130 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1131 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1132 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1133
1134 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1135 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1136
1137 t = AR8327_PORT_LOOKUP_LEARN;
1138 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1139 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1140 }
1141
1142 static u32
1143 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1144 {
1145 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1146 }
1147
1148 static int
1149 ar8327_atu_flush(struct ar8216_priv *priv)
1150 {
1151 int ret;
1152
1153 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1154 AR8327_ATU_FUNC_BUSY, 0);
1155 if (!ret)
1156 priv->write(priv, AR8327_REG_ATU_FUNC,
1157 AR8327_ATU_FUNC_OP_FLUSH);
1158
1159 return ret;
1160 }
1161
1162 static void
1163 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1164 {
1165 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1166 AR8327_VTU_FUNC1_BUSY, 0))
1167 return;
1168
1169 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1170 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1171
1172 op |= AR8327_VTU_FUNC1_BUSY;
1173 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1174 }
1175
1176 static void
1177 ar8327_vtu_flush(struct ar8216_priv *priv)
1178 {
1179 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1180 }
1181
1182 static void
1183 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1184 {
1185 u32 op;
1186 u32 val;
1187 int i;
1188
1189 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1190 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1191 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1192 u32 mode;
1193
1194 if ((port_mask & BIT(i)) == 0)
1195 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1196 else if (priv->vlan == 0)
1197 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1198 else if (priv->vlan_tagged & BIT(i))
1199 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1200 else
1201 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1202
1203 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1204 }
1205 ar8327_vtu_op(priv, op, val);
1206 }
1207
1208 static void
1209 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1210 u32 members, u32 pvid)
1211 {
1212 u32 t;
1213 u32 mode;
1214
1215 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1216 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1217 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1218
1219 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1220 switch (egress) {
1221 case AR8216_OUT_KEEP:
1222 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1223 break;
1224 case AR8216_OUT_STRIP_VLAN:
1225 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1226 break;
1227 case AR8216_OUT_ADD_VLAN:
1228 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1229 break;
1230 }
1231
1232 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1233 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1234 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1235
1236 t = members;
1237 t |= AR8327_PORT_LOOKUP_LEARN;
1238 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1239 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1240 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1241 }
1242
1243 static const struct ar8xxx_chip ar8327_chip = {
1244 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1245 .hw_init = ar8327_hw_init,
1246 .init_globals = ar8327_init_globals,
1247 .init_port = ar8327_init_port,
1248 .setup_port = ar8327_setup_port,
1249 .read_port_status = ar8327_read_port_status,
1250 .atu_flush = ar8327_atu_flush,
1251 .vtu_flush = ar8327_vtu_flush,
1252 .vtu_load_vlan = ar8327_vtu_load_vlan,
1253
1254 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1255 .mib_decs = ar8236_mibs,
1256 };
1257
1258 static int
1259 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1260 struct switch_val *val)
1261 {
1262 struct ar8216_priv *priv = to_ar8216(dev);
1263 priv->vlan = !!val->value.i;
1264 return 0;
1265 }
1266
1267 static int
1268 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1269 struct switch_val *val)
1270 {
1271 struct ar8216_priv *priv = to_ar8216(dev);
1272 val->value.i = priv->vlan;
1273 return 0;
1274 }
1275
1276
1277 static int
1278 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1279 {
1280 struct ar8216_priv *priv = to_ar8216(dev);
1281
1282 /* make sure no invalid PVIDs get set */
1283
1284 if (vlan >= dev->vlans)
1285 return -EINVAL;
1286
1287 priv->pvid[port] = vlan;
1288 return 0;
1289 }
1290
1291 static int
1292 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1293 {
1294 struct ar8216_priv *priv = to_ar8216(dev);
1295 *vlan = priv->pvid[port];
1296 return 0;
1297 }
1298
1299 static int
1300 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1301 struct switch_val *val)
1302 {
1303 struct ar8216_priv *priv = to_ar8216(dev);
1304 priv->vlan_id[val->port_vlan] = val->value.i;
1305 return 0;
1306 }
1307
1308 static int
1309 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1310 struct switch_val *val)
1311 {
1312 struct ar8216_priv *priv = to_ar8216(dev);
1313 val->value.i = priv->vlan_id[val->port_vlan];
1314 return 0;
1315 }
1316
1317 static int
1318 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1319 struct switch_port_link *link)
1320 {
1321 struct ar8216_priv *priv = to_ar8216(dev);
1322
1323 ar8216_read_port_link(priv, port, link);
1324 return 0;
1325 }
1326
1327 static int
1328 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1329 {
1330 struct ar8216_priv *priv = to_ar8216(dev);
1331 u8 ports = priv->vlan_table[val->port_vlan];
1332 int i;
1333
1334 val->len = 0;
1335 for (i = 0; i < dev->ports; i++) {
1336 struct switch_port *p;
1337
1338 if (!(ports & (1 << i)))
1339 continue;
1340
1341 p = &val->value.ports[val->len++];
1342 p->id = i;
1343 if (priv->vlan_tagged & (1 << i))
1344 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1345 else
1346 p->flags = 0;
1347 }
1348 return 0;
1349 }
1350
1351 static int
1352 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1353 {
1354 struct ar8216_priv *priv = to_ar8216(dev);
1355 u8 *vt = &priv->vlan_table[val->port_vlan];
1356 int i, j;
1357
1358 *vt = 0;
1359 for (i = 0; i < val->len; i++) {
1360 struct switch_port *p = &val->value.ports[i];
1361
1362 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1363 priv->vlan_tagged |= (1 << p->id);
1364 } else {
1365 priv->vlan_tagged &= ~(1 << p->id);
1366 priv->pvid[p->id] = val->port_vlan;
1367
1368 /* make sure that an untagged port does not
1369 * appear in other vlans */
1370 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1371 if (j == val->port_vlan)
1372 continue;
1373 priv->vlan_table[j] &= ~(1 << p->id);
1374 }
1375 }
1376
1377 *vt |= 1 << p->id;
1378 }
1379 return 0;
1380 }
1381
1382 static int
1383 ar8216_sw_hw_apply(struct switch_dev *dev)
1384 {
1385 struct ar8216_priv *priv = to_ar8216(dev);
1386 u8 portmask[AR8X16_MAX_PORTS];
1387 int i, j;
1388
1389 mutex_lock(&priv->reg_mutex);
1390 /* flush all vlan translation unit entries */
1391 priv->chip->vtu_flush(priv);
1392
1393 memset(portmask, 0, sizeof(portmask));
1394 if (!priv->init) {
1395 /* calculate the port destination masks and load vlans
1396 * into the vlan translation unit */
1397 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1398 u8 vp = priv->vlan_table[j];
1399
1400 if (!vp)
1401 continue;
1402
1403 for (i = 0; i < dev->ports; i++) {
1404 u8 mask = (1 << i);
1405 if (vp & mask)
1406 portmask[i] |= vp & ~mask;
1407 }
1408
1409 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1410 priv->vlan_table[j]);
1411 }
1412 } else {
1413 /* vlan disabled:
1414 * isolate all ports, but connect them to the cpu port */
1415 for (i = 0; i < dev->ports; i++) {
1416 if (i == AR8216_PORT_CPU)
1417 continue;
1418
1419 portmask[i] = 1 << AR8216_PORT_CPU;
1420 portmask[AR8216_PORT_CPU] |= (1 << i);
1421 }
1422 }
1423
1424 /* update the port destination mask registers and tag settings */
1425 for (i = 0; i < dev->ports; i++) {
1426 int egress, ingress;
1427 int pvid;
1428
1429 if (priv->vlan) {
1430 pvid = priv->vlan_id[priv->pvid[i]];
1431 if (priv->vlan_tagged & (1 << i))
1432 egress = AR8216_OUT_ADD_VLAN;
1433 else
1434 egress = AR8216_OUT_STRIP_VLAN;
1435 ingress = AR8216_IN_SECURE;
1436 } else {
1437 pvid = i;
1438 egress = AR8216_OUT_KEEP;
1439 ingress = AR8216_IN_PORT_ONLY;
1440 }
1441
1442 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1443 pvid);
1444 }
1445 mutex_unlock(&priv->reg_mutex);
1446 return 0;
1447 }
1448
1449 static int
1450 ar8216_sw_reset_switch(struct switch_dev *dev)
1451 {
1452 struct ar8216_priv *priv = to_ar8216(dev);
1453 int i;
1454
1455 mutex_lock(&priv->reg_mutex);
1456 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1457 offsetof(struct ar8216_priv, vlan));
1458
1459 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1460 priv->vlan_id[i] = i;
1461
1462 /* Configure all ports */
1463 for (i = 0; i < dev->ports; i++)
1464 priv->chip->init_port(priv, i);
1465
1466 priv->chip->init_globals(priv);
1467 mutex_unlock(&priv->reg_mutex);
1468
1469 return ar8216_sw_hw_apply(dev);
1470 }
1471
1472 static int
1473 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1474 const struct switch_attr *attr,
1475 struct switch_val *val)
1476 {
1477 struct ar8216_priv *priv = to_ar8216(dev);
1478 unsigned int len;
1479 int ret;
1480
1481 if (!ar8xxx_has_mib_counters(priv))
1482 return -EOPNOTSUPP;
1483
1484 mutex_lock(&priv->mib_lock);
1485
1486 len = priv->dev.ports * priv->chip->num_mibs *
1487 sizeof(*priv->mib_stats);
1488 memset(priv->mib_stats, '\0', len);
1489 ret = ar8216_mib_flush(priv);
1490 if (ret)
1491 goto unlock;
1492
1493 ret = 0;
1494
1495 unlock:
1496 mutex_unlock(&priv->mib_lock);
1497 return ret;
1498 }
1499
1500 static int
1501 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1502 const struct switch_attr *attr,
1503 struct switch_val *val)
1504 {
1505 struct ar8216_priv *priv = to_ar8216(dev);
1506 int port;
1507 int ret;
1508
1509 if (!ar8xxx_has_mib_counters(priv))
1510 return -EOPNOTSUPP;
1511
1512 port = val->port_vlan;
1513 if (port >= dev->ports)
1514 return -EINVAL;
1515
1516 mutex_lock(&priv->mib_lock);
1517 ret = ar8216_mib_capture(priv);
1518 if (ret)
1519 goto unlock;
1520
1521 ar8216_mib_fetch_port_stat(priv, port, true);
1522
1523 ret = 0;
1524
1525 unlock:
1526 mutex_unlock(&priv->mib_lock);
1527 return ret;
1528 }
1529
1530 static int
1531 ar8216_sw_get_port_mib(struct switch_dev *dev,
1532 const struct switch_attr *attr,
1533 struct switch_val *val)
1534 {
1535 struct ar8216_priv *priv = to_ar8216(dev);
1536 const struct ar8xxx_chip *chip = priv->chip;
1537 u64 *mib_stats;
1538 int port;
1539 int ret;
1540 char *buf = priv->buf;
1541 int i, len = 0;
1542
1543 if (!ar8xxx_has_mib_counters(priv))
1544 return -EOPNOTSUPP;
1545
1546 port = val->port_vlan;
1547 if (port >= dev->ports)
1548 return -EINVAL;
1549
1550 mutex_lock(&priv->mib_lock);
1551 ret = ar8216_mib_capture(priv);
1552 if (ret)
1553 goto unlock;
1554
1555 ar8216_mib_fetch_port_stat(priv, port, false);
1556
1557 len += snprintf(buf + len, sizeof(priv->buf) - len,
1558 "Port %d MIB counters\n",
1559 port);
1560
1561 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1562 for (i = 0; i < chip->num_mibs; i++)
1563 len += snprintf(buf + len, sizeof(priv->buf) - len,
1564 "%-12s: %llu\n",
1565 chip->mib_decs[i].name,
1566 mib_stats[i]);
1567
1568 val->value.s = buf;
1569 val->len = len;
1570
1571 ret = 0;
1572
1573 unlock:
1574 mutex_unlock(&priv->mib_lock);
1575 return ret;
1576 }
1577
1578 static struct switch_attr ar8216_globals[] = {
1579 {
1580 .type = SWITCH_TYPE_INT,
1581 .name = "enable_vlan",
1582 .description = "Enable VLAN mode",
1583 .set = ar8216_sw_set_vlan,
1584 .get = ar8216_sw_get_vlan,
1585 .max = 1
1586 },
1587 {
1588 .type = SWITCH_TYPE_NOVAL,
1589 .name = "reset_mibs",
1590 .description = "Reset all MIB counters",
1591 .set = ar8216_sw_set_reset_mibs,
1592 },
1593
1594 };
1595
1596 static struct switch_attr ar8216_port[] = {
1597 {
1598 .type = SWITCH_TYPE_NOVAL,
1599 .name = "reset_mib",
1600 .description = "Reset single port MIB counters",
1601 .set = ar8216_sw_set_port_reset_mib,
1602 },
1603 {
1604 .type = SWITCH_TYPE_STRING,
1605 .name = "mib",
1606 .description = "Get port's MIB counters",
1607 .set = NULL,
1608 .get = ar8216_sw_get_port_mib,
1609 },
1610 };
1611
1612 static struct switch_attr ar8216_vlan[] = {
1613 {
1614 .type = SWITCH_TYPE_INT,
1615 .name = "vid",
1616 .description = "VLAN ID (0-4094)",
1617 .set = ar8216_sw_set_vid,
1618 .get = ar8216_sw_get_vid,
1619 .max = 4094,
1620 },
1621 };
1622
1623 static const struct switch_dev_ops ar8216_sw_ops = {
1624 .attr_global = {
1625 .attr = ar8216_globals,
1626 .n_attr = ARRAY_SIZE(ar8216_globals),
1627 },
1628 .attr_port = {
1629 .attr = ar8216_port,
1630 .n_attr = ARRAY_SIZE(ar8216_port),
1631 },
1632 .attr_vlan = {
1633 .attr = ar8216_vlan,
1634 .n_attr = ARRAY_SIZE(ar8216_vlan),
1635 },
1636 .get_port_pvid = ar8216_sw_get_pvid,
1637 .set_port_pvid = ar8216_sw_set_pvid,
1638 .get_vlan_ports = ar8216_sw_get_ports,
1639 .set_vlan_ports = ar8216_sw_set_ports,
1640 .apply_config = ar8216_sw_hw_apply,
1641 .reset_switch = ar8216_sw_reset_switch,
1642 .get_port_link = ar8216_sw_get_port_link,
1643 };
1644
1645 static int
1646 ar8216_id_chip(struct ar8216_priv *priv)
1647 {
1648 u32 val;
1649 u16 id;
1650 int i;
1651
1652 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1653 if (val == ~0)
1654 return -ENODEV;
1655
1656 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1657 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1658 u16 t;
1659
1660 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1661 if (val == ~0)
1662 return -ENODEV;
1663
1664 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1665 if (t != id)
1666 return -ENODEV;
1667 }
1668
1669 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1670 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1671
1672 switch (priv->chip_ver) {
1673 case AR8XXX_VER_AR8216:
1674 priv->chip = &ar8216_chip;
1675 break;
1676 case AR8XXX_VER_AR8236:
1677 priv->chip = &ar8236_chip;
1678 break;
1679 case AR8XXX_VER_AR8316:
1680 priv->chip = &ar8316_chip;
1681 break;
1682 case AR8XXX_VER_AR8327:
1683 priv->mii_lo_first = true;
1684 priv->chip = &ar8327_chip;
1685 break;
1686 default:
1687 printk(KERN_DEBUG
1688 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1689 priv->chip_ver, priv->chip_rev,
1690 mdiobus_read(priv->mii_bus, priv->phy->addr, 2),
1691 mdiobus_read(priv->mii_bus, priv->phy->addr, 3));
1692
1693 return -ENODEV;
1694 }
1695
1696 return 0;
1697 }
1698
1699 static void
1700 ar8xxx_mib_work_func(struct work_struct *work)
1701 {
1702 struct ar8216_priv *priv;
1703 int err;
1704
1705 priv = container_of(work, struct ar8216_priv, mib_work.work);
1706
1707 mutex_lock(&priv->mib_lock);
1708
1709 err = ar8216_mib_capture(priv);
1710 if (err)
1711 goto next_port;
1712
1713 ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1714
1715 next_port:
1716 priv->mib_next_port++;
1717 if (priv->mib_next_port >= priv->dev.ports)
1718 priv->mib_next_port = 0;
1719
1720 mutex_unlock(&priv->mib_lock);
1721 schedule_delayed_work(&priv->mib_work,
1722 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1723 }
1724
1725 static int
1726 ar8xxx_mib_init(struct ar8216_priv *priv)
1727 {
1728 unsigned int len;
1729
1730 if (!ar8xxx_has_mib_counters(priv))
1731 return 0;
1732
1733 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1734
1735 len = priv->dev.ports * priv->chip->num_mibs *
1736 sizeof(*priv->mib_stats);
1737 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1738
1739 if (!priv->mib_stats)
1740 return -ENOMEM;
1741
1742 mutex_init(&priv->mib_lock);
1743 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1744
1745 return 0;
1746 }
1747
1748 static void
1749 ar8xxx_mib_start(struct ar8216_priv *priv)
1750 {
1751 if (!ar8xxx_has_mib_counters(priv))
1752 return;
1753
1754 schedule_delayed_work(&priv->mib_work,
1755 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1756 }
1757
1758 static void
1759 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1760 {
1761 if (!ar8xxx_has_mib_counters(priv))
1762 return;
1763
1764 cancel_delayed_work(&priv->mib_work);
1765 kfree(priv->mib_stats);
1766 }
1767
1768 static int
1769 ar8216_config_init(struct phy_device *pdev)
1770 {
1771 struct ar8216_priv *priv = pdev->priv;
1772 struct net_device *dev = pdev->attached_dev;
1773 struct switch_dev *swdev;
1774 int ret;
1775
1776 if (!priv) {
1777 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1778 if (priv == NULL)
1779 return -ENOMEM;
1780 }
1781
1782 priv->mii_bus = pdev->bus;
1783 priv->phy = pdev;
1784
1785 ret = ar8216_id_chip(priv);
1786 if (ret)
1787 goto err_free_priv;
1788
1789 if (pdev->addr != 0) {
1790 if (ar8xxx_has_gige(priv)) {
1791 pdev->supported |= SUPPORTED_1000baseT_Full;
1792 pdev->advertising |= ADVERTISED_1000baseT_Full;
1793 }
1794
1795 if (chip_is_ar8316(priv)) {
1796 /* check if we're attaching to the switch twice */
1797 pdev = pdev->bus->phy_map[0];
1798 if (!pdev) {
1799 kfree(priv);
1800 return 0;
1801 }
1802
1803 /* switch device has not been initialized, reuse priv */
1804 if (!pdev->priv) {
1805 priv->port4_phy = true;
1806 pdev->priv = priv;
1807 return 0;
1808 }
1809
1810 kfree(priv);
1811
1812 /* switch device has been initialized, reinit */
1813 priv = pdev->priv;
1814 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1815 priv->initialized = false;
1816 priv->port4_phy = true;
1817 ar8316_hw_init(priv);
1818 return 0;
1819 }
1820
1821 kfree(priv);
1822 return 0;
1823 }
1824
1825 if (ar8xxx_has_gige(priv))
1826 pdev->supported = SUPPORTED_1000baseT_Full;
1827 else
1828 pdev->supported = SUPPORTED_100baseT_Full;
1829 pdev->advertising = pdev->supported;
1830
1831 mutex_init(&priv->reg_mutex);
1832 priv->read = ar8216_mii_read;
1833 priv->write = ar8216_mii_write;
1834
1835 pdev->priv = priv;
1836
1837 swdev = &priv->dev;
1838 swdev->cpu_port = AR8216_PORT_CPU;
1839 swdev->ops = &ar8216_sw_ops;
1840 swdev->ports = AR8216_NUM_PORTS;
1841
1842 if (chip_is_ar8316(priv)) {
1843 swdev->name = "Atheros AR8316";
1844 swdev->vlans = AR8X16_MAX_VLANS;
1845
1846 if (priv->port4_phy) {
1847 /* port 5 connected to the other mac, therefore unusable */
1848 swdev->ports = (AR8216_NUM_PORTS - 1);
1849 }
1850 } else if (chip_is_ar8236(priv)) {
1851 swdev->name = "Atheros AR8236";
1852 swdev->vlans = AR8216_NUM_VLANS;
1853 swdev->ports = AR8216_NUM_PORTS;
1854 } else if (chip_is_ar8327(priv)) {
1855 swdev->name = "Atheros AR8327";
1856 swdev->vlans = AR8X16_MAX_VLANS;
1857 swdev->ports = AR8327_NUM_PORTS;
1858 } else {
1859 swdev->name = "Atheros AR8216";
1860 swdev->vlans = AR8216_NUM_VLANS;
1861 }
1862
1863 ret = ar8xxx_mib_init(priv);
1864 if (ret)
1865 goto err_free_priv;
1866
1867 ret = register_switch(swdev, pdev->attached_dev);
1868 if (ret)
1869 goto err_cleanup_mib;
1870
1871 printk(KERN_INFO "%s: %s switch driver attached.\n",
1872 pdev->attached_dev->name, swdev->name);
1873
1874 priv->init = true;
1875
1876 ret = priv->chip->hw_init(priv);
1877 if (ret)
1878 goto err_unregister_switch;
1879
1880 ret = ar8216_sw_reset_switch(&priv->dev);
1881 if (ret)
1882 goto err_unregister_switch;
1883
1884 dev->phy_ptr = priv;
1885
1886 /* VID fixup only needed on ar8216 */
1887 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1888 dev->priv_flags |= IFF_NO_IP_ALIGN;
1889 dev->eth_mangle_rx = ar8216_mangle_rx;
1890 dev->eth_mangle_tx = ar8216_mangle_tx;
1891 }
1892
1893 priv->init = false;
1894
1895 ar8xxx_mib_start(priv);
1896
1897 return 0;
1898
1899 err_unregister_switch:
1900 unregister_switch(&priv->dev);
1901 err_cleanup_mib:
1902 ar8xxx_mib_cleanup(priv);
1903 err_free_priv:
1904 kfree(priv);
1905 pdev->priv = NULL;
1906 return ret;
1907 }
1908
1909 static int
1910 ar8216_read_status(struct phy_device *phydev)
1911 {
1912 struct ar8216_priv *priv = phydev->priv;
1913 struct switch_port_link link;
1914 int ret;
1915
1916 if (phydev->addr != 0)
1917 return genphy_read_status(phydev);
1918
1919 ar8216_read_port_link(priv, phydev->addr, &link);
1920 phydev->link = !!link.link;
1921 if (!phydev->link)
1922 return 0;
1923
1924 switch (link.speed) {
1925 case SWITCH_PORT_SPEED_10:
1926 phydev->speed = SPEED_10;
1927 break;
1928 case SWITCH_PORT_SPEED_100:
1929 phydev->speed = SPEED_100;
1930 break;
1931 case SWITCH_PORT_SPEED_1000:
1932 phydev->speed = SPEED_1000;
1933 break;
1934 default:
1935 phydev->speed = 0;
1936 }
1937 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1938
1939 /* flush the address translation unit */
1940 mutex_lock(&priv->reg_mutex);
1941 ret = priv->chip->atu_flush(priv);
1942 mutex_unlock(&priv->reg_mutex);
1943
1944 phydev->state = PHY_RUNNING;
1945 netif_carrier_on(phydev->attached_dev);
1946 phydev->adjust_link(phydev->attached_dev);
1947
1948 return ret;
1949 }
1950
1951 static int
1952 ar8216_config_aneg(struct phy_device *phydev)
1953 {
1954 if (phydev->addr == 0)
1955 return 0;
1956
1957 return genphy_config_aneg(phydev);
1958 }
1959
1960 static int
1961 ar8216_probe(struct phy_device *pdev)
1962 {
1963 struct ar8216_priv *priv;
1964 int ret;
1965
1966 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1967 if (priv == NULL)
1968 return -ENOMEM;
1969
1970 priv->mii_bus = pdev->bus;
1971 priv->phy = pdev;
1972
1973 ret = ar8216_id_chip(priv);
1974 kfree(priv);
1975
1976 return ret;
1977 }
1978
1979 static void
1980 ar8216_detach(struct phy_device *pdev)
1981 {
1982 struct net_device *dev = pdev->attached_dev;
1983
1984 if (!dev)
1985 return;
1986
1987 dev->phy_ptr = NULL;
1988 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1989 dev->eth_mangle_rx = NULL;
1990 dev->eth_mangle_tx = NULL;
1991 }
1992
1993 static void
1994 ar8216_remove(struct phy_device *pdev)
1995 {
1996 struct ar8216_priv *priv = pdev->priv;
1997
1998 if (!priv)
1999 return;
2000
2001 pdev->priv = NULL;
2002
2003 if (pdev->addr == 0)
2004 unregister_switch(&priv->dev);
2005
2006 ar8xxx_mib_cleanup(priv);
2007 kfree(priv);
2008 }
2009
2010 static struct phy_driver ar8216_driver = {
2011 .phy_id = 0x004d0000,
2012 .name = "Atheros AR8216/AR8236/AR8316",
2013 .phy_id_mask = 0xffff0000,
2014 .features = PHY_BASIC_FEATURES,
2015 .probe = ar8216_probe,
2016 .remove = ar8216_remove,
2017 .detach = ar8216_detach,
2018 .config_init = &ar8216_config_init,
2019 .config_aneg = &ar8216_config_aneg,
2020 .read_status = &ar8216_read_status,
2021 .driver = { .owner = THIS_MODULE },
2022 };
2023
2024 int __init
2025 ar8216_init(void)
2026 {
2027 return phy_driver_register(&ar8216_driver);
2028 }
2029
2030 void __exit
2031 ar8216_exit(void)
2032 {
2033 phy_driver_unregister(&ar8216_driver);
2034 }
2035
2036 module_init(ar8216_init);
2037 module_exit(ar8216_exit);
2038 MODULE_LICENSE("GPL");
2039
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