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generic: ar8216: cleanup function/variable names
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8xxx_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8xxx_priv *priv);
67 void (*init_globals)(struct ar8xxx_priv *priv);
68 void (*init_port)(struct ar8xxx_priv *priv, int port);
69 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
72 int (*atu_flush)(struct ar8xxx_priv *priv);
73 void (*vtu_flush)(struct ar8xxx_priv *priv);
74 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8xxx_priv {
81 struct switch_dev dev;
82 struct mii_bus *mii_bus;
83 struct phy_device *phy;
84 u32 (*read)(struct ar8xxx_priv *priv, int reg);
85 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
86 const struct net_device_ops *ndo_old;
87 struct net_device_ops ndo;
88 struct mutex reg_mutex;
89 u8 chip_ver;
90 u8 chip_rev;
91 const struct ar8xxx_chip *chip;
92 bool initialized;
93 bool port4_phy;
94 char buf[2048];
95
96 bool init;
97 bool mii_lo_first;
98
99 struct mutex mib_lock;
100 struct delayed_work mib_work;
101 int mib_next_port;
102 u64 *mib_stats;
103
104 struct list_head list;
105 unsigned int use_count;
106
107 /* all fields below are cleared on reset */
108 bool vlan;
109 u16 vlan_id[AR8X16_MAX_VLANS];
110 u8 vlan_table[AR8X16_MAX_VLANS];
111 u8 vlan_tagged;
112 u16 pvid[AR8X16_MAX_PORTS];
113 };
114
115 #define MIB_DESC(_s , _o, _n) \
116 { \
117 .size = (_s), \
118 .offset = (_o), \
119 .name = (_n), \
120 }
121
122 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
123 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
124 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
125 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
126 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
127 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
128 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
129 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
130 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
131 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
132 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
133 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
134 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
135 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
136 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
137 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
138 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
139 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
140 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
141 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
142 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
143 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
144 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
145 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
146 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
147 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
148 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
149 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
150 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
151 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
152 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
153 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
154 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
155 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
156 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
157 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
158 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
159 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
160 };
161
162 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
163 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
164 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
165 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
166 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
167 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
168 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
169 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
170 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
171 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
172 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
173 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
174 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
175 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
176 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
177 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
178 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
179 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
180 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
181 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
182 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
183 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
184 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
185 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
186 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
187 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
188 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
189 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
190 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
191 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
192 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
193 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
194 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
195 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
196 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
197 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
198 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
199 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
200 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
201 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
202 };
203
204 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
205 static LIST_HEAD(ar8xxx_dev_list);
206
207 static inline struct ar8xxx_priv *
208 swdev_to_ar8xxx(struct switch_dev *swdev)
209 {
210 return container_of(swdev, struct ar8xxx_priv, dev);
211 }
212
213 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
214 {
215 return priv->chip->caps & AR8XXX_CAP_GIGE;
216 }
217
218 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
219 {
220 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
221 }
222
223 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
224 {
225 return priv->chip_ver == AR8XXX_VER_AR8216;
226 }
227
228 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
229 {
230 return priv->chip_ver == AR8XXX_VER_AR8236;
231 }
232
233 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
234 {
235 return priv->chip_ver == AR8XXX_VER_AR8316;
236 }
237
238 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
239 {
240 return priv->chip_ver == AR8XXX_VER_AR8327;
241 }
242
243 static inline void
244 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
245 {
246 regaddr >>= 1;
247 *r1 = regaddr & 0x1e;
248
249 regaddr >>= 5;
250 *r2 = regaddr & 0x7;
251
252 regaddr >>= 3;
253 *page = regaddr & 0x1ff;
254 }
255
256 static u32
257 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
258 {
259 struct mii_bus *bus = priv->mii_bus;
260 u16 r1, r2, page;
261 u16 lo, hi;
262
263 split_addr((u32) reg, &r1, &r2, &page);
264
265 mutex_lock(&bus->mdio_lock);
266
267 bus->write(bus, 0x18, 0, page);
268 usleep_range(1000, 2000); /* wait for the page switch to propagate */
269 lo = bus->read(bus, 0x10 | r2, r1);
270 hi = bus->read(bus, 0x10 | r2, r1 + 1);
271
272 mutex_unlock(&bus->mdio_lock);
273
274 return (hi << 16) | lo;
275 }
276
277 static void
278 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
279 {
280 struct mii_bus *bus = priv->mii_bus;
281 u16 r1, r2, r3;
282 u16 lo, hi;
283
284 split_addr((u32) reg, &r1, &r2, &r3);
285 lo = val & 0xffff;
286 hi = (u16) (val >> 16);
287
288 mutex_lock(&bus->mdio_lock);
289
290 bus->write(bus, 0x18, 0, r3);
291 usleep_range(1000, 2000); /* wait for the page switch to propagate */
292 if (priv->mii_lo_first) {
293 bus->write(bus, 0x10 | r2, r1, lo);
294 bus->write(bus, 0x10 | r2, r1 + 1, hi);
295 } else {
296 bus->write(bus, 0x10 | r2, r1 + 1, hi);
297 bus->write(bus, 0x10 | r2, r1, lo);
298 }
299
300 mutex_unlock(&bus->mdio_lock);
301 }
302
303 static void
304 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
305 u16 dbg_addr, u16 dbg_data)
306 {
307 struct mii_bus *bus = priv->mii_bus;
308
309 mutex_lock(&bus->mdio_lock);
310 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
311 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
312 mutex_unlock(&bus->mdio_lock);
313 }
314
315 static void
316 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
317 {
318 struct mii_bus *bus = priv->mii_bus;
319
320 mutex_lock(&bus->mdio_lock);
321 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
322 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
323 mutex_unlock(&bus->mdio_lock);
324 }
325
326 static u32
327 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
328 {
329 u32 v;
330
331 lockdep_assert_held(&priv->reg_mutex);
332
333 v = priv->read(priv, reg);
334 v &= ~mask;
335 v |= val;
336 priv->write(priv, reg, v);
337
338 return v;
339 }
340
341 static inline void
342 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
343 {
344 u32 v;
345
346 lockdep_assert_held(&priv->reg_mutex);
347
348 v = priv->read(priv, reg);
349 v |= val;
350 priv->write(priv, reg, v);
351 }
352
353 static int
354 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
355 unsigned timeout)
356 {
357 int i;
358
359 for (i = 0; i < timeout; i++) {
360 u32 t;
361
362 t = priv->read(priv, reg);
363 if ((t & mask) == val)
364 return 0;
365
366 usleep_range(1000, 2000);
367 }
368
369 return -ETIMEDOUT;
370 }
371
372 static int
373 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
374 {
375 unsigned mib_func;
376 int ret;
377
378 lockdep_assert_held(&priv->mib_lock);
379
380 if (chip_is_ar8327(priv))
381 mib_func = AR8327_REG_MIB_FUNC;
382 else
383 mib_func = AR8216_REG_MIB_FUNC;
384
385 mutex_lock(&priv->reg_mutex);
386 /* Capture the hardware statistics for all ports */
387 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
388 mutex_unlock(&priv->reg_mutex);
389
390 /* Wait for the capturing to complete. */
391 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
392 if (ret)
393 goto out;
394
395 ret = 0;
396
397 out:
398 return ret;
399 }
400
401 static int
402 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
403 {
404 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
405 }
406
407 static int
408 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
409 {
410 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
411 }
412
413 static void
414 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
415 {
416 unsigned int base;
417 u64 *mib_stats;
418 int i;
419
420 WARN_ON(port >= priv->dev.ports);
421
422 lockdep_assert_held(&priv->mib_lock);
423
424 if (chip_is_ar8327(priv))
425 base = AR8327_REG_PORT_STATS_BASE(port);
426 else if (chip_is_ar8236(priv) ||
427 chip_is_ar8316(priv))
428 base = AR8236_REG_PORT_STATS_BASE(port);
429 else
430 base = AR8216_REG_PORT_STATS_BASE(port);
431
432 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
433 for (i = 0; i < priv->chip->num_mibs; i++) {
434 const struct ar8xxx_mib_desc *mib;
435 u64 t;
436
437 mib = &priv->chip->mib_decs[i];
438 t = priv->read(priv, base + mib->offset);
439 if (mib->size == 2) {
440 u64 hi;
441
442 hi = priv->read(priv, base + mib->offset + 4);
443 t |= hi << 32;
444 }
445
446 if (flush)
447 mib_stats[i] = 0;
448 else
449 mib_stats[i] += t;
450 }
451 }
452
453 static void
454 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
455 struct switch_port_link *link)
456 {
457 u32 status;
458 u32 speed;
459
460 memset(link, '\0', sizeof(*link));
461
462 status = priv->chip->read_port_status(priv, port);
463
464 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
465 if (link->aneg) {
466 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
467 if (!link->link)
468 return;
469 } else {
470 link->link = true;
471 }
472
473 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
474 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
475 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
476
477 speed = (status & AR8216_PORT_STATUS_SPEED) >>
478 AR8216_PORT_STATUS_SPEED_S;
479
480 switch (speed) {
481 case AR8216_PORT_SPEED_10M:
482 link->speed = SWITCH_PORT_SPEED_10;
483 break;
484 case AR8216_PORT_SPEED_100M:
485 link->speed = SWITCH_PORT_SPEED_100;
486 break;
487 case AR8216_PORT_SPEED_1000M:
488 link->speed = SWITCH_PORT_SPEED_1000;
489 break;
490 default:
491 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
492 break;
493 }
494 }
495
496 static struct sk_buff *
497 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
498 {
499 struct ar8xxx_priv *priv = dev->phy_ptr;
500 unsigned char *buf;
501
502 if (unlikely(!priv))
503 goto error;
504
505 if (!priv->vlan)
506 goto send;
507
508 if (unlikely(skb_headroom(skb) < 2)) {
509 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
510 goto error;
511 }
512
513 buf = skb_push(skb, 2);
514 buf[0] = 0x10;
515 buf[1] = 0x80;
516
517 send:
518 return skb;
519
520 error:
521 dev_kfree_skb_any(skb);
522 return NULL;
523 }
524
525 static void
526 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
527 {
528 struct ar8xxx_priv *priv;
529 unsigned char *buf;
530 int port, vlan;
531
532 priv = dev->phy_ptr;
533 if (!priv)
534 return;
535
536 /* don't strip the header if vlan mode is disabled */
537 if (!priv->vlan)
538 return;
539
540 /* strip header, get vlan id */
541 buf = skb->data;
542 skb_pull(skb, 2);
543
544 /* check for vlan header presence */
545 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
546 return;
547
548 port = buf[0] & 0xf;
549
550 /* no need to fix up packets coming from a tagged source */
551 if (priv->vlan_tagged & (1 << port))
552 return;
553
554 /* lookup port vid from local table, the switch passes an invalid vlan id */
555 vlan = priv->vlan_id[priv->pvid[port]];
556
557 buf[14 + 2] &= 0xf0;
558 buf[14 + 2] |= vlan >> 8;
559 buf[15 + 2] = vlan & 0xff;
560 }
561
562 static int
563 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
564 {
565 int timeout = 20;
566 u32 t = 0;
567
568 while (1) {
569 t = priv->read(priv, reg);
570 if ((t & mask) == val)
571 return 0;
572
573 if (timeout-- <= 0)
574 break;
575
576 udelay(10);
577 }
578
579 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
580 (unsigned int) reg, t, mask, val);
581 return -ETIMEDOUT;
582 }
583
584 static void
585 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
586 {
587 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
588 return;
589 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
590 val &= AR8216_VTUDATA_MEMBER;
591 val |= AR8216_VTUDATA_VALID;
592 priv->write(priv, AR8216_REG_VTU_DATA, val);
593 }
594 op |= AR8216_VTU_ACTIVE;
595 priv->write(priv, AR8216_REG_VTU, op);
596 }
597
598 static void
599 ar8216_vtu_flush(struct ar8xxx_priv *priv)
600 {
601 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
602 }
603
604 static void
605 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
606 {
607 u32 op;
608
609 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
610 ar8216_vtu_op(priv, op, port_mask);
611 }
612
613 static int
614 ar8216_atu_flush(struct ar8xxx_priv *priv)
615 {
616 int ret;
617
618 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
619 if (!ret)
620 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
621
622 return ret;
623 }
624
625 static u32
626 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
627 {
628 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
629 }
630
631 static void
632 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
633 u32 members, u32 pvid)
634 {
635 u32 header;
636
637 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
638 header = AR8216_PORT_CTRL_HEADER;
639 else
640 header = 0;
641
642 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
643 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
644 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
645 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
646 AR8216_PORT_CTRL_LEARN | header |
647 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
648 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
649
650 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
651 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
652 AR8216_PORT_VLAN_DEFAULT_ID,
653 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
654 (ingress << AR8216_PORT_VLAN_MODE_S) |
655 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
656 }
657
658 static int
659 ar8216_hw_init(struct ar8xxx_priv *priv)
660 {
661 return 0;
662 }
663
664 static void
665 ar8216_init_globals(struct ar8xxx_priv *priv)
666 {
667 /* standard atheros magic */
668 priv->write(priv, 0x38, 0xc000050e);
669
670 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
671 AR8216_GCTRL_MTU, 1518 + 8 + 2);
672 }
673
674 static void
675 ar8216_init_port(struct ar8xxx_priv *priv, int port)
676 {
677 /* Enable port learning and tx */
678 priv->write(priv, AR8216_REG_PORT_CTRL(port),
679 AR8216_PORT_CTRL_LEARN |
680 (4 << AR8216_PORT_CTRL_STATE_S));
681
682 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
683
684 if (port == AR8216_PORT_CPU) {
685 priv->write(priv, AR8216_REG_PORT_STATUS(port),
686 AR8216_PORT_STATUS_LINK_UP |
687 (ar8xxx_has_gige(priv) ?
688 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
689 AR8216_PORT_STATUS_TXMAC |
690 AR8216_PORT_STATUS_RXMAC |
691 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
692 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
693 AR8216_PORT_STATUS_DUPLEX);
694 } else {
695 priv->write(priv, AR8216_REG_PORT_STATUS(port),
696 AR8216_PORT_STATUS_LINK_AUTO);
697 }
698 }
699
700 static const struct ar8xxx_chip ar8216_chip = {
701 .caps = AR8XXX_CAP_MIB_COUNTERS,
702
703 .hw_init = ar8216_hw_init,
704 .init_globals = ar8216_init_globals,
705 .init_port = ar8216_init_port,
706 .setup_port = ar8216_setup_port,
707 .read_port_status = ar8216_read_port_status,
708 .atu_flush = ar8216_atu_flush,
709 .vtu_flush = ar8216_vtu_flush,
710 .vtu_load_vlan = ar8216_vtu_load_vlan,
711
712 .num_mibs = ARRAY_SIZE(ar8216_mibs),
713 .mib_decs = ar8216_mibs,
714 };
715
716 static void
717 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
718 u32 members, u32 pvid)
719 {
720 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
721 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
722 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
723 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
724 AR8216_PORT_CTRL_LEARN |
725 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
726 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
727
728 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
729 AR8236_PORT_VLAN_DEFAULT_ID,
730 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
731
732 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
733 AR8236_PORT_VLAN2_VLAN_MODE |
734 AR8236_PORT_VLAN2_MEMBER,
735 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
736 (members << AR8236_PORT_VLAN2_MEMBER_S));
737 }
738
739 static int
740 ar8236_hw_init(struct ar8xxx_priv *priv)
741 {
742 int i;
743 struct mii_bus *bus;
744
745 if (priv->initialized)
746 return 0;
747
748 /* Initialize the PHYs */
749 bus = priv->mii_bus;
750 for (i = 0; i < 5; i++) {
751 mdiobus_write(bus, i, MII_ADVERTISE,
752 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
753 ADVERTISE_PAUSE_ASYM);
754 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
755 }
756 msleep(1000);
757
758 priv->initialized = true;
759 return 0;
760 }
761
762 static void
763 ar8236_init_globals(struct ar8xxx_priv *priv)
764 {
765 /* enable jumbo frames */
766 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
767 AR8316_GCTRL_MTU, 9018 + 8 + 2);
768
769 /* Enable MIB counters */
770 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
771 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
772 AR8236_MIB_EN);
773 }
774
775 static const struct ar8xxx_chip ar8236_chip = {
776 .caps = AR8XXX_CAP_MIB_COUNTERS,
777 .hw_init = ar8236_hw_init,
778 .init_globals = ar8236_init_globals,
779 .init_port = ar8216_init_port,
780 .setup_port = ar8236_setup_port,
781 .read_port_status = ar8216_read_port_status,
782 .atu_flush = ar8216_atu_flush,
783 .vtu_flush = ar8216_vtu_flush,
784 .vtu_load_vlan = ar8216_vtu_load_vlan,
785
786 .num_mibs = ARRAY_SIZE(ar8236_mibs),
787 .mib_decs = ar8236_mibs,
788 };
789
790 static int
791 ar8316_hw_init(struct ar8xxx_priv *priv)
792 {
793 int i;
794 u32 val, newval;
795 struct mii_bus *bus;
796
797 val = priv->read(priv, AR8316_REG_POSTRIP);
798
799 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
800 if (priv->port4_phy) {
801 /* value taken from Ubiquiti RouterStation Pro */
802 newval = 0x81461bea;
803 pr_info("ar8316: Using port 4 as PHY\n");
804 } else {
805 newval = 0x01261be2;
806 pr_info("ar8316: Using port 4 as switch port\n");
807 }
808 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
809 /* value taken from AVM Fritz!Box 7390 sources */
810 newval = 0x010e5b71;
811 } else {
812 /* no known value for phy interface */
813 pr_err("ar8316: unsupported mii mode: %d.\n",
814 priv->phy->interface);
815 return -EINVAL;
816 }
817
818 if (val == newval)
819 goto out;
820
821 priv->write(priv, AR8316_REG_POSTRIP, newval);
822
823 if (priv->port4_phy &&
824 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
825 /* work around for phy4 rgmii mode */
826 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
827 /* rx delay */
828 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
829 /* tx delay */
830 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
831 msleep(1000);
832 }
833
834 /* Initialize the ports */
835 bus = priv->mii_bus;
836 for (i = 0; i < 5; i++) {
837 /* initialize the port itself */
838 mdiobus_write(bus, i, MII_ADVERTISE,
839 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
840 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
841 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
842 }
843
844 msleep(1000);
845
846 out:
847 priv->initialized = true;
848 return 0;
849 }
850
851 static void
852 ar8316_init_globals(struct ar8xxx_priv *priv)
853 {
854 /* standard atheros magic */
855 priv->write(priv, 0x38, 0xc000050e);
856
857 /* enable cpu port to receive multicast and broadcast frames */
858 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
859
860 /* enable jumbo frames */
861 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
862 AR8316_GCTRL_MTU, 9018 + 8 + 2);
863
864 /* Enable MIB counters */
865 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
866 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
867 AR8236_MIB_EN);
868 }
869
870 static const struct ar8xxx_chip ar8316_chip = {
871 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
872 .hw_init = ar8316_hw_init,
873 .init_globals = ar8316_init_globals,
874 .init_port = ar8216_init_port,
875 .setup_port = ar8216_setup_port,
876 .read_port_status = ar8216_read_port_status,
877 .atu_flush = ar8216_atu_flush,
878 .vtu_flush = ar8216_vtu_flush,
879 .vtu_load_vlan = ar8216_vtu_load_vlan,
880
881 .num_mibs = ARRAY_SIZE(ar8236_mibs),
882 .mib_decs = ar8236_mibs,
883 };
884
885 static u32
886 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
887 {
888 u32 t;
889
890 if (!cfg)
891 return 0;
892
893 t = 0;
894 switch (cfg->mode) {
895 case AR8327_PAD_NC:
896 break;
897
898 case AR8327_PAD_MAC2MAC_MII:
899 t = AR8327_PAD_MAC_MII_EN;
900 if (cfg->rxclk_sel)
901 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
902 if (cfg->txclk_sel)
903 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
904 break;
905
906 case AR8327_PAD_MAC2MAC_GMII:
907 t = AR8327_PAD_MAC_GMII_EN;
908 if (cfg->rxclk_sel)
909 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
910 if (cfg->txclk_sel)
911 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
912 break;
913
914 case AR8327_PAD_MAC_SGMII:
915 t = AR8327_PAD_SGMII_EN;
916
917 /*
918 * WAR for the QUalcomm Atheros AP136 board.
919 * It seems that RGMII TX/RX delay settings needs to be
920 * applied for SGMII mode as well, The ethernet is not
921 * reliable without this.
922 */
923 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
924 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
925 if (cfg->rxclk_delay_en)
926 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
927 if (cfg->txclk_delay_en)
928 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
929
930 if (cfg->sgmii_delay_en)
931 t |= AR8327_PAD_SGMII_DELAY_EN;
932
933 break;
934
935 case AR8327_PAD_MAC2PHY_MII:
936 t = AR8327_PAD_PHY_MII_EN;
937 if (cfg->rxclk_sel)
938 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
939 if (cfg->txclk_sel)
940 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
941 break;
942
943 case AR8327_PAD_MAC2PHY_GMII:
944 t = AR8327_PAD_PHY_GMII_EN;
945 if (cfg->pipe_rxclk_sel)
946 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
947 if (cfg->rxclk_sel)
948 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
949 if (cfg->txclk_sel)
950 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
951 break;
952
953 case AR8327_PAD_MAC_RGMII:
954 t = AR8327_PAD_RGMII_EN;
955 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
956 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
957 if (cfg->rxclk_delay_en)
958 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
959 if (cfg->txclk_delay_en)
960 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
961 break;
962
963 case AR8327_PAD_PHY_GMII:
964 t = AR8327_PAD_PHYX_GMII_EN;
965 break;
966
967 case AR8327_PAD_PHY_RGMII:
968 t = AR8327_PAD_PHYX_RGMII_EN;
969 break;
970
971 case AR8327_PAD_PHY_MII:
972 t = AR8327_PAD_PHYX_MII_EN;
973 break;
974 }
975
976 return t;
977 }
978
979 static void
980 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
981 {
982 switch (priv->chip_rev) {
983 case 1:
984 /* For 100M waveform */
985 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
986 /* Turn on Gigabit clock */
987 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
988 break;
989
990 case 2:
991 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
992 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
993 /* fallthrough */
994 case 4:
995 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
996 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
997
998 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
999 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1000 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1001 break;
1002 }
1003 }
1004
1005 static int
1006 ar8327_hw_init(struct ar8xxx_priv *priv)
1007 {
1008 struct ar8327_platform_data *pdata;
1009 struct ar8327_led_cfg *led_cfg;
1010 struct mii_bus *bus;
1011 u32 pos, new_pos;
1012 u32 t;
1013 int i;
1014
1015 pdata = priv->phy->dev.platform_data;
1016 if (!pdata)
1017 return -EINVAL;
1018
1019 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1020 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1021 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1022 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1023 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1024 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1025
1026 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1027 new_pos = pos;
1028
1029 led_cfg = pdata->led_cfg;
1030 if (led_cfg) {
1031 if (led_cfg->open_drain)
1032 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1033 else
1034 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1035
1036 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1037 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1038 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1039 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1040 }
1041
1042 if (new_pos != pos) {
1043 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1044 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1045 }
1046
1047 bus = priv->mii_bus;
1048 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1049 ar8327_phy_fixup(priv, i);
1050
1051 /* start aneg on the PHY */
1052 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1053 ADVERTISE_PAUSE_CAP |
1054 ADVERTISE_PAUSE_ASYM);
1055 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1056 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1057 }
1058
1059 msleep(1000);
1060
1061 return 0;
1062 }
1063
1064 static void
1065 ar8327_init_globals(struct ar8xxx_priv *priv)
1066 {
1067 u32 t;
1068
1069 /* enable CPU port and disable mirror port */
1070 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1071 AR8327_FWD_CTRL0_MIRROR_PORT;
1072 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1073
1074 /* forward multicast and broadcast frames to CPU */
1075 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1076 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1077 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1078 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1079
1080 /* setup MTU */
1081 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1082 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1083
1084 /* Enable MIB counters */
1085 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1086 AR8327_MODULE_EN_MIB);
1087 }
1088
1089 static void
1090 ar8327_config_port(struct ar8xxx_priv *priv, unsigned int port,
1091 struct ar8327_port_cfg *cfg)
1092 {
1093 u32 t;
1094
1095 if (!cfg || !cfg->force_link) {
1096 priv->write(priv, AR8327_REG_PORT_STATUS(port),
1097 AR8216_PORT_STATUS_LINK_AUTO);
1098 return;
1099 }
1100
1101 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1102 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1103 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1104 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1105
1106 switch (cfg->speed) {
1107 case AR8327_PORT_SPEED_10:
1108 t |= AR8216_PORT_SPEED_10M;
1109 break;
1110 case AR8327_PORT_SPEED_100:
1111 t |= AR8216_PORT_SPEED_100M;
1112 break;
1113 case AR8327_PORT_SPEED_1000:
1114 t |= AR8216_PORT_SPEED_1000M;
1115 break;
1116 }
1117
1118 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1119 }
1120
1121 static void
1122 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1123 {
1124 struct ar8327_platform_data *pdata;
1125 struct ar8327_port_cfg *cfg;
1126 u32 t;
1127
1128 pdata = priv->phy->dev.platform_data;
1129
1130 if (pdata && port == AR8216_PORT_CPU)
1131 cfg = &pdata->port0_cfg;
1132 else if (pdata && port == 6)
1133 cfg = &pdata->port6_cfg;
1134 else
1135 cfg = NULL;
1136
1137 ar8327_config_port(priv, port, cfg);
1138
1139 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1140
1141 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1142 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1143 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1144
1145 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1146 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1147
1148 t = AR8327_PORT_LOOKUP_LEARN;
1149 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1150 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1151 }
1152
1153 static u32
1154 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1155 {
1156 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1157 }
1158
1159 static int
1160 ar8327_atu_flush(struct ar8xxx_priv *priv)
1161 {
1162 int ret;
1163
1164 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1165 AR8327_ATU_FUNC_BUSY, 0);
1166 if (!ret)
1167 priv->write(priv, AR8327_REG_ATU_FUNC,
1168 AR8327_ATU_FUNC_OP_FLUSH);
1169
1170 return ret;
1171 }
1172
1173 static void
1174 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1175 {
1176 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1177 AR8327_VTU_FUNC1_BUSY, 0))
1178 return;
1179
1180 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1181 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1182
1183 op |= AR8327_VTU_FUNC1_BUSY;
1184 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1185 }
1186
1187 static void
1188 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1189 {
1190 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1191 }
1192
1193 static void
1194 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1195 {
1196 u32 op;
1197 u32 val;
1198 int i;
1199
1200 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1201 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1202 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1203 u32 mode;
1204
1205 if ((port_mask & BIT(i)) == 0)
1206 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1207 else if (priv->vlan == 0)
1208 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1209 else if (priv->vlan_tagged & BIT(i))
1210 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1211 else
1212 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1213
1214 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1215 }
1216 ar8327_vtu_op(priv, op, val);
1217 }
1218
1219 static void
1220 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1221 u32 members, u32 pvid)
1222 {
1223 u32 t;
1224 u32 mode;
1225
1226 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1227 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1228 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1229
1230 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1231 switch (egress) {
1232 case AR8216_OUT_KEEP:
1233 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1234 break;
1235 case AR8216_OUT_STRIP_VLAN:
1236 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1237 break;
1238 case AR8216_OUT_ADD_VLAN:
1239 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1240 break;
1241 }
1242
1243 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1244 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1245 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1246
1247 t = members;
1248 t |= AR8327_PORT_LOOKUP_LEARN;
1249 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1250 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1251 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1252 }
1253
1254 static const struct ar8xxx_chip ar8327_chip = {
1255 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1256 .hw_init = ar8327_hw_init,
1257 .init_globals = ar8327_init_globals,
1258 .init_port = ar8327_init_port,
1259 .setup_port = ar8327_setup_port,
1260 .read_port_status = ar8327_read_port_status,
1261 .atu_flush = ar8327_atu_flush,
1262 .vtu_flush = ar8327_vtu_flush,
1263 .vtu_load_vlan = ar8327_vtu_load_vlan,
1264
1265 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1266 .mib_decs = ar8236_mibs,
1267 };
1268
1269 static int
1270 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1271 struct switch_val *val)
1272 {
1273 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1274 priv->vlan = !!val->value.i;
1275 return 0;
1276 }
1277
1278 static int
1279 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1280 struct switch_val *val)
1281 {
1282 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1283 val->value.i = priv->vlan;
1284 return 0;
1285 }
1286
1287
1288 static int
1289 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1290 {
1291 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1292
1293 /* make sure no invalid PVIDs get set */
1294
1295 if (vlan >= dev->vlans)
1296 return -EINVAL;
1297
1298 priv->pvid[port] = vlan;
1299 return 0;
1300 }
1301
1302 static int
1303 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1304 {
1305 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1306 *vlan = priv->pvid[port];
1307 return 0;
1308 }
1309
1310 static int
1311 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1312 struct switch_val *val)
1313 {
1314 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1315 priv->vlan_id[val->port_vlan] = val->value.i;
1316 return 0;
1317 }
1318
1319 static int
1320 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1321 struct switch_val *val)
1322 {
1323 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1324 val->value.i = priv->vlan_id[val->port_vlan];
1325 return 0;
1326 }
1327
1328 static int
1329 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1330 struct switch_port_link *link)
1331 {
1332 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1333
1334 ar8216_read_port_link(priv, port, link);
1335 return 0;
1336 }
1337
1338 static int
1339 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1340 {
1341 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1342 u8 ports = priv->vlan_table[val->port_vlan];
1343 int i;
1344
1345 val->len = 0;
1346 for (i = 0; i < dev->ports; i++) {
1347 struct switch_port *p;
1348
1349 if (!(ports & (1 << i)))
1350 continue;
1351
1352 p = &val->value.ports[val->len++];
1353 p->id = i;
1354 if (priv->vlan_tagged & (1 << i))
1355 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1356 else
1357 p->flags = 0;
1358 }
1359 return 0;
1360 }
1361
1362 static int
1363 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1364 {
1365 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1366 u8 *vt = &priv->vlan_table[val->port_vlan];
1367 int i, j;
1368
1369 *vt = 0;
1370 for (i = 0; i < val->len; i++) {
1371 struct switch_port *p = &val->value.ports[i];
1372
1373 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1374 priv->vlan_tagged |= (1 << p->id);
1375 } else {
1376 priv->vlan_tagged &= ~(1 << p->id);
1377 priv->pvid[p->id] = val->port_vlan;
1378
1379 /* make sure that an untagged port does not
1380 * appear in other vlans */
1381 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1382 if (j == val->port_vlan)
1383 continue;
1384 priv->vlan_table[j] &= ~(1 << p->id);
1385 }
1386 }
1387
1388 *vt |= 1 << p->id;
1389 }
1390 return 0;
1391 }
1392
1393 static int
1394 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1395 {
1396 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1397 u8 portmask[AR8X16_MAX_PORTS];
1398 int i, j;
1399
1400 mutex_lock(&priv->reg_mutex);
1401 /* flush all vlan translation unit entries */
1402 priv->chip->vtu_flush(priv);
1403
1404 memset(portmask, 0, sizeof(portmask));
1405 if (!priv->init) {
1406 /* calculate the port destination masks and load vlans
1407 * into the vlan translation unit */
1408 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1409 u8 vp = priv->vlan_table[j];
1410
1411 if (!vp)
1412 continue;
1413
1414 for (i = 0; i < dev->ports; i++) {
1415 u8 mask = (1 << i);
1416 if (vp & mask)
1417 portmask[i] |= vp & ~mask;
1418 }
1419
1420 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1421 priv->vlan_table[j]);
1422 }
1423 } else {
1424 /* vlan disabled:
1425 * isolate all ports, but connect them to the cpu port */
1426 for (i = 0; i < dev->ports; i++) {
1427 if (i == AR8216_PORT_CPU)
1428 continue;
1429
1430 portmask[i] = 1 << AR8216_PORT_CPU;
1431 portmask[AR8216_PORT_CPU] |= (1 << i);
1432 }
1433 }
1434
1435 /* update the port destination mask registers and tag settings */
1436 for (i = 0; i < dev->ports; i++) {
1437 int egress, ingress;
1438 int pvid;
1439
1440 if (priv->vlan) {
1441 pvid = priv->vlan_id[priv->pvid[i]];
1442 if (priv->vlan_tagged & (1 << i))
1443 egress = AR8216_OUT_ADD_VLAN;
1444 else
1445 egress = AR8216_OUT_STRIP_VLAN;
1446 ingress = AR8216_IN_SECURE;
1447 } else {
1448 pvid = i;
1449 egress = AR8216_OUT_KEEP;
1450 ingress = AR8216_IN_PORT_ONLY;
1451 }
1452
1453 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1454 pvid);
1455 }
1456 mutex_unlock(&priv->reg_mutex);
1457 return 0;
1458 }
1459
1460 static int
1461 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1462 {
1463 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1464 int i;
1465
1466 mutex_lock(&priv->reg_mutex);
1467 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1468 offsetof(struct ar8xxx_priv, vlan));
1469
1470 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1471 priv->vlan_id[i] = i;
1472
1473 /* Configure all ports */
1474 for (i = 0; i < dev->ports; i++)
1475 priv->chip->init_port(priv, i);
1476
1477 priv->chip->init_globals(priv);
1478 mutex_unlock(&priv->reg_mutex);
1479
1480 return ar8xxx_sw_hw_apply(dev);
1481 }
1482
1483 static int
1484 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1485 const struct switch_attr *attr,
1486 struct switch_val *val)
1487 {
1488 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1489 unsigned int len;
1490 int ret;
1491
1492 if (!ar8xxx_has_mib_counters(priv))
1493 return -EOPNOTSUPP;
1494
1495 mutex_lock(&priv->mib_lock);
1496
1497 len = priv->dev.ports * priv->chip->num_mibs *
1498 sizeof(*priv->mib_stats);
1499 memset(priv->mib_stats, '\0', len);
1500 ret = ar8xxx_mib_flush(priv);
1501 if (ret)
1502 goto unlock;
1503
1504 ret = 0;
1505
1506 unlock:
1507 mutex_unlock(&priv->mib_lock);
1508 return ret;
1509 }
1510
1511 static int
1512 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1513 const struct switch_attr *attr,
1514 struct switch_val *val)
1515 {
1516 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1517 int port;
1518 int ret;
1519
1520 if (!ar8xxx_has_mib_counters(priv))
1521 return -EOPNOTSUPP;
1522
1523 port = val->port_vlan;
1524 if (port >= dev->ports)
1525 return -EINVAL;
1526
1527 mutex_lock(&priv->mib_lock);
1528 ret = ar8xxx_mib_capture(priv);
1529 if (ret)
1530 goto unlock;
1531
1532 ar8xxx_mib_fetch_port_stat(priv, port, true);
1533
1534 ret = 0;
1535
1536 unlock:
1537 mutex_unlock(&priv->mib_lock);
1538 return ret;
1539 }
1540
1541 static int
1542 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1543 const struct switch_attr *attr,
1544 struct switch_val *val)
1545 {
1546 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1547 const struct ar8xxx_chip *chip = priv->chip;
1548 u64 *mib_stats;
1549 int port;
1550 int ret;
1551 char *buf = priv->buf;
1552 int i, len = 0;
1553
1554 if (!ar8xxx_has_mib_counters(priv))
1555 return -EOPNOTSUPP;
1556
1557 port = val->port_vlan;
1558 if (port >= dev->ports)
1559 return -EINVAL;
1560
1561 mutex_lock(&priv->mib_lock);
1562 ret = ar8xxx_mib_capture(priv);
1563 if (ret)
1564 goto unlock;
1565
1566 ar8xxx_mib_fetch_port_stat(priv, port, false);
1567
1568 len += snprintf(buf + len, sizeof(priv->buf) - len,
1569 "Port %d MIB counters\n",
1570 port);
1571
1572 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1573 for (i = 0; i < chip->num_mibs; i++)
1574 len += snprintf(buf + len, sizeof(priv->buf) - len,
1575 "%-12s: %llu\n",
1576 chip->mib_decs[i].name,
1577 mib_stats[i]);
1578
1579 val->value.s = buf;
1580 val->len = len;
1581
1582 ret = 0;
1583
1584 unlock:
1585 mutex_unlock(&priv->mib_lock);
1586 return ret;
1587 }
1588
1589 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1590 {
1591 .type = SWITCH_TYPE_INT,
1592 .name = "enable_vlan",
1593 .description = "Enable VLAN mode",
1594 .set = ar8xxx_sw_set_vlan,
1595 .get = ar8xxx_sw_get_vlan,
1596 .max = 1
1597 },
1598 {
1599 .type = SWITCH_TYPE_NOVAL,
1600 .name = "reset_mibs",
1601 .description = "Reset all MIB counters",
1602 .set = ar8xxx_sw_set_reset_mibs,
1603 },
1604
1605 };
1606
1607 static struct switch_attr ar8xxx_sw_attr_port[] = {
1608 {
1609 .type = SWITCH_TYPE_NOVAL,
1610 .name = "reset_mib",
1611 .description = "Reset single port MIB counters",
1612 .set = ar8xxx_sw_set_port_reset_mib,
1613 },
1614 {
1615 .type = SWITCH_TYPE_STRING,
1616 .name = "mib",
1617 .description = "Get port's MIB counters",
1618 .set = NULL,
1619 .get = ar8xxx_sw_get_port_mib,
1620 },
1621 };
1622
1623 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1624 {
1625 .type = SWITCH_TYPE_INT,
1626 .name = "vid",
1627 .description = "VLAN ID (0-4094)",
1628 .set = ar8xxx_sw_set_vid,
1629 .get = ar8xxx_sw_get_vid,
1630 .max = 4094,
1631 },
1632 };
1633
1634 static const struct switch_dev_ops ar8xxx_sw_ops = {
1635 .attr_global = {
1636 .attr = ar8xxx_sw_attr_globals,
1637 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1638 },
1639 .attr_port = {
1640 .attr = ar8xxx_sw_attr_port,
1641 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1642 },
1643 .attr_vlan = {
1644 .attr = ar8xxx_sw_attr_vlan,
1645 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1646 },
1647 .get_port_pvid = ar8xxx_sw_get_pvid,
1648 .set_port_pvid = ar8xxx_sw_set_pvid,
1649 .get_vlan_ports = ar8xxx_sw_get_ports,
1650 .set_vlan_ports = ar8xxx_sw_set_ports,
1651 .apply_config = ar8xxx_sw_hw_apply,
1652 .reset_switch = ar8xxx_sw_reset_switch,
1653 .get_port_link = ar8xxx_sw_get_port_link,
1654 };
1655
1656 static int
1657 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1658 {
1659 u32 val;
1660 u16 id;
1661 int i;
1662
1663 val = priv->read(priv, AR8216_REG_CTRL);
1664 if (val == ~0)
1665 return -ENODEV;
1666
1667 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1668 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1669 u16 t;
1670
1671 val = priv->read(priv, AR8216_REG_CTRL);
1672 if (val == ~0)
1673 return -ENODEV;
1674
1675 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1676 if (t != id)
1677 return -ENODEV;
1678 }
1679
1680 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1681 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1682
1683 switch (priv->chip_ver) {
1684 case AR8XXX_VER_AR8216:
1685 priv->chip = &ar8216_chip;
1686 break;
1687 case AR8XXX_VER_AR8236:
1688 priv->chip = &ar8236_chip;
1689 break;
1690 case AR8XXX_VER_AR8316:
1691 priv->chip = &ar8316_chip;
1692 break;
1693 case AR8XXX_VER_AR8327:
1694 priv->mii_lo_first = true;
1695 priv->chip = &ar8327_chip;
1696 break;
1697 default:
1698 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1699 priv->chip_ver, priv->chip_rev);
1700
1701 return -ENODEV;
1702 }
1703
1704 return 0;
1705 }
1706
1707 static void
1708 ar8xxx_mib_work_func(struct work_struct *work)
1709 {
1710 struct ar8xxx_priv *priv;
1711 int err;
1712
1713 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1714
1715 mutex_lock(&priv->mib_lock);
1716
1717 err = ar8xxx_mib_capture(priv);
1718 if (err)
1719 goto next_port;
1720
1721 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1722
1723 next_port:
1724 priv->mib_next_port++;
1725 if (priv->mib_next_port >= priv->dev.ports)
1726 priv->mib_next_port = 0;
1727
1728 mutex_unlock(&priv->mib_lock);
1729 schedule_delayed_work(&priv->mib_work,
1730 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1731 }
1732
1733 static int
1734 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1735 {
1736 unsigned int len;
1737
1738 if (!ar8xxx_has_mib_counters(priv))
1739 return 0;
1740
1741 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1742
1743 len = priv->dev.ports * priv->chip->num_mibs *
1744 sizeof(*priv->mib_stats);
1745 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1746
1747 if (!priv->mib_stats)
1748 return -ENOMEM;
1749
1750 return 0;
1751 }
1752
1753 static void
1754 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1755 {
1756 if (!ar8xxx_has_mib_counters(priv))
1757 return;
1758
1759 schedule_delayed_work(&priv->mib_work,
1760 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1761 }
1762
1763 static void
1764 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1765 {
1766 if (!ar8xxx_has_mib_counters(priv))
1767 return;
1768
1769 cancel_delayed_work(&priv->mib_work);
1770 }
1771
1772 static struct ar8xxx_priv *
1773 ar8xxx_create(void)
1774 {
1775 struct ar8xxx_priv *priv;
1776
1777 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1778 if (priv == NULL)
1779 return NULL;
1780
1781 mutex_init(&priv->reg_mutex);
1782 mutex_init(&priv->mib_lock);
1783 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1784
1785 return priv;
1786 }
1787
1788 static void
1789 ar8xxx_free(struct ar8xxx_priv *priv)
1790 {
1791 kfree(priv->mib_stats);
1792 kfree(priv);
1793 }
1794
1795 static struct ar8xxx_priv *
1796 ar8xxx_create_mii(struct mii_bus *bus)
1797 {
1798 struct ar8xxx_priv *priv;
1799
1800 priv = ar8xxx_create();
1801 if (priv) {
1802 priv->mii_bus = bus;
1803 priv->read = ar8xxx_mii_read;
1804 priv->write = ar8xxx_mii_write;
1805 }
1806
1807 return priv;
1808 }
1809
1810 static int
1811 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1812 {
1813 struct switch_dev *swdev;
1814 int ret;
1815
1816 ret = ar8xxx_id_chip(priv);
1817 if (ret)
1818 return ret;
1819
1820 swdev = &priv->dev;
1821 swdev->cpu_port = AR8216_PORT_CPU;
1822 swdev->ops = &ar8xxx_sw_ops;
1823
1824 if (chip_is_ar8316(priv)) {
1825 swdev->name = "Atheros AR8316";
1826 swdev->vlans = AR8X16_MAX_VLANS;
1827 swdev->ports = AR8216_NUM_PORTS;
1828 } else if (chip_is_ar8236(priv)) {
1829 swdev->name = "Atheros AR8236";
1830 swdev->vlans = AR8216_NUM_VLANS;
1831 swdev->ports = AR8216_NUM_PORTS;
1832 } else if (chip_is_ar8327(priv)) {
1833 swdev->name = "Atheros AR8327";
1834 swdev->vlans = AR8X16_MAX_VLANS;
1835 swdev->ports = AR8327_NUM_PORTS;
1836 } else {
1837 swdev->name = "Atheros AR8216";
1838 swdev->vlans = AR8216_NUM_VLANS;
1839 swdev->ports = AR8216_NUM_PORTS;
1840 }
1841
1842 ret = ar8xxx_mib_init(priv);
1843 if (ret)
1844 return ret;
1845
1846 return 0;
1847 }
1848
1849 static int
1850 ar8xxx_phy_config_init(struct phy_device *phydev)
1851 {
1852 struct ar8xxx_priv *priv = phydev->priv;
1853 struct net_device *dev = phydev->attached_dev;
1854 int ret;
1855
1856 if (WARN_ON(!priv))
1857 return -ENODEV;
1858
1859 priv->phy = phydev;
1860
1861 if (phydev->addr != 0) {
1862 if (chip_is_ar8316(priv)) {
1863 /* switch device has been initialized, reinit */
1864 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1865 priv->initialized = false;
1866 priv->port4_phy = true;
1867 ar8316_hw_init(priv);
1868 return 0;
1869 }
1870
1871 return 0;
1872 }
1873
1874 priv->init = true;
1875
1876 ret = priv->chip->hw_init(priv);
1877 if (ret)
1878 return ret;
1879
1880 ret = ar8xxx_sw_reset_switch(&priv->dev);
1881 if (ret)
1882 return ret;
1883
1884 /* VID fixup only needed on ar8216 */
1885 if (chip_is_ar8216(priv)) {
1886 dev->phy_ptr = priv;
1887 dev->priv_flags |= IFF_NO_IP_ALIGN;
1888 dev->eth_mangle_rx = ar8216_mangle_rx;
1889 dev->eth_mangle_tx = ar8216_mangle_tx;
1890 }
1891
1892 priv->init = false;
1893
1894 ar8xxx_mib_start(priv);
1895
1896 return 0;
1897 }
1898
1899 static int
1900 ar8xxx_phy_read_status(struct phy_device *phydev)
1901 {
1902 struct ar8xxx_priv *priv = phydev->priv;
1903 struct switch_port_link link;
1904 int ret;
1905
1906 if (phydev->addr != 0)
1907 return genphy_read_status(phydev);
1908
1909 ar8216_read_port_link(priv, phydev->addr, &link);
1910 phydev->link = !!link.link;
1911 if (!phydev->link)
1912 return 0;
1913
1914 switch (link.speed) {
1915 case SWITCH_PORT_SPEED_10:
1916 phydev->speed = SPEED_10;
1917 break;
1918 case SWITCH_PORT_SPEED_100:
1919 phydev->speed = SPEED_100;
1920 break;
1921 case SWITCH_PORT_SPEED_1000:
1922 phydev->speed = SPEED_1000;
1923 break;
1924 default:
1925 phydev->speed = 0;
1926 }
1927 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1928
1929 /* flush the address translation unit */
1930 mutex_lock(&priv->reg_mutex);
1931 ret = priv->chip->atu_flush(priv);
1932 mutex_unlock(&priv->reg_mutex);
1933
1934 phydev->state = PHY_RUNNING;
1935 netif_carrier_on(phydev->attached_dev);
1936 phydev->adjust_link(phydev->attached_dev);
1937
1938 return ret;
1939 }
1940
1941 static int
1942 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1943 {
1944 if (phydev->addr == 0)
1945 return 0;
1946
1947 return genphy_config_aneg(phydev);
1948 }
1949
1950 static const u32 ar8xxx_phy_ids[] = {
1951 0x004dd033,
1952 0x004dd041,
1953 0x004dd042,
1954 };
1955
1956 static bool
1957 ar8xxx_phy_match(u32 phy_id)
1958 {
1959 int i;
1960
1961 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1962 if (phy_id == ar8xxx_phy_ids[i])
1963 return true;
1964
1965 return false;
1966 }
1967
1968 static bool
1969 ar8xxx_is_possible(struct mii_bus *bus)
1970 {
1971 unsigned i;
1972
1973 for (i = 0; i < 4; i++) {
1974 u32 phy_id;
1975
1976 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1977 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1978 if (!ar8xxx_phy_match(phy_id)) {
1979 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1980 dev_name(&bus->dev), i, phy_id);
1981 return false;
1982 }
1983 }
1984
1985 return true;
1986 }
1987
1988 static int
1989 ar8xxx_phy_probe(struct phy_device *phydev)
1990 {
1991 struct ar8xxx_priv *priv;
1992 struct switch_dev *swdev;
1993 int ret;
1994
1995 /* skip PHYs at unused adresses */
1996 if (phydev->addr != 0 && phydev->addr != 4)
1997 return -ENODEV;
1998
1999 if (!ar8xxx_is_possible(phydev->bus))
2000 return -ENODEV;
2001
2002 mutex_lock(&ar8xxx_dev_list_lock);
2003 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2004 if (priv->mii_bus == phydev->bus)
2005 goto found;
2006
2007 priv = ar8xxx_create_mii(phydev->bus);
2008 if (priv == NULL) {
2009 ret = -ENOMEM;
2010 goto unlock;
2011 }
2012
2013 ret = ar8xxx_probe_switch(priv);
2014 if (ret)
2015 goto free_priv;
2016
2017 swdev = &priv->dev;
2018 swdev->alias = dev_name(&priv->mii_bus->dev);
2019 ret = register_switch(swdev, NULL);
2020 if (ret)
2021 goto free_priv;
2022
2023 pr_info("%s: %s switch registered on %s\n",
2024 swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
2025
2026 found:
2027 if (phydev->addr == 0) {
2028 if (ar8xxx_has_gige(priv)) {
2029 phydev->supported = SUPPORTED_1000baseT_Full;
2030 phydev->advertising = ADVERTISED_1000baseT_Full;
2031 } else {
2032 phydev->supported = SUPPORTED_100baseT_Full;
2033 phydev->advertising = ADVERTISED_100baseT_Full;
2034 }
2035 } else {
2036 if (ar8xxx_has_gige(priv)) {
2037 phydev->supported |= SUPPORTED_1000baseT_Full;
2038 phydev->advertising |= ADVERTISED_1000baseT_Full;
2039 }
2040 }
2041
2042 phydev->priv = priv;
2043 priv->use_count++;
2044
2045 list_add(&priv->list, &ar8xxx_dev_list);
2046
2047 mutex_unlock(&ar8xxx_dev_list_lock);
2048
2049 return 0;
2050
2051 free_priv:
2052 ar8xxx_free(priv);
2053 unlock:
2054 mutex_unlock(&ar8xxx_dev_list_lock);
2055 return ret;
2056 }
2057
2058 static void
2059 ar8xxx_phy_detach(struct phy_device *phydev)
2060 {
2061 struct net_device *dev = phydev->attached_dev;
2062
2063 if (!dev)
2064 return;
2065
2066 dev->phy_ptr = NULL;
2067 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2068 dev->eth_mangle_rx = NULL;
2069 dev->eth_mangle_tx = NULL;
2070 }
2071
2072 static void
2073 ar8xxx_phy_remove(struct phy_device *phydev)
2074 {
2075 struct ar8xxx_priv *priv = phydev->priv;
2076
2077 if (WARN_ON(!priv))
2078 return;
2079
2080 phydev->priv = NULL;
2081 if (--priv->use_count > 0)
2082 return;
2083
2084 mutex_lock(&ar8xxx_dev_list_lock);
2085 list_del(&priv->list);
2086 mutex_unlock(&ar8xxx_dev_list_lock);
2087
2088 unregister_switch(&priv->dev);
2089 ar8xxx_mib_stop(priv);
2090 ar8xxx_free(priv);
2091 }
2092
2093 static struct phy_driver ar8xxx_phy_driver = {
2094 .phy_id = 0x004d0000,
2095 .name = "Atheros AR8216/AR8236/AR8316",
2096 .phy_id_mask = 0xffff0000,
2097 .features = PHY_BASIC_FEATURES,
2098 .probe = ar8xxx_phy_probe,
2099 .remove = ar8xxx_phy_remove,
2100 .detach = ar8xxx_phy_detach,
2101 .config_init = ar8xxx_phy_config_init,
2102 .config_aneg = ar8xxx_phy_config_aneg,
2103 .read_status = ar8xxx_phy_read_status,
2104 .driver = { .owner = THIS_MODULE },
2105 };
2106
2107 int __init
2108 ar8xxx_init(void)
2109 {
2110 return phy_driver_register(&ar8xxx_phy_driver);
2111 }
2112
2113 void __exit
2114 ar8xxx_exit(void)
2115 {
2116 phy_driver_unregister(&ar8xxx_phy_driver);
2117 }
2118
2119 module_init(ar8xxx_init);
2120 module_exit(ar8xxx_exit);
2121 MODULE_LICENSE("GPL");
2122
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