target/linux/generic/files/drivers/net/phy/ar8216.h

   1 /*
   2  * ar8216.h: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __AR8216_H
  18 #define __AR8216_H
  19
  20 #define BITS(_s, _n)    (((1UL << (_n)) - 1) << _s)
  21
  22 #define AR8216_PORT_CPU 0
  23 #define AR8216_NUM_PORTS        6
  24 #define AR8216_NUM_VLANS        16
  25 #define AR8316_NUM_VLANS        4096
  26
  27 /* Atheros specific MII registers */
  28 #define MII_ATH_DBG_ADDR                0x1d
  29 #define MII_ATH_DBG_DATA                0x1e
  30
  31 #define AR8216_REG_CTRL                 0x0000
  32 #define   AR8216_CTRL_REVISION          BITS(0, 8)
  33 #define   AR8216_CTRL_REVISION_S        0
  34 #define   AR8216_CTRL_VERSION           BITS(8, 8)
  35 #define   AR8216_CTRL_VERSION_S         8
  36 #define   AR8216_CTRL_RESET             BIT(31)
  37
  38 #define AR8216_REG_FLOOD_MASK           0x002C
  39 #define   AR8216_FM_UNI_DEST_PORTS      BITS(0, 6)
  40 #define   AR8216_FM_MULTI_DEST_PORTS    BITS(16, 6)
  41
  42 #define AR8216_REG_GLOBAL_CTRL          0x0030
  43 #define   AR8216_GCTRL_MTU              BITS(0, 11)
  44 #define   AR8236_GCTRL_MTU              BITS(0, 14)
  45 #define   AR8316_GCTRL_MTU              BITS(0, 14)
  46
  47 #define AR8216_REG_VTU                  0x0040
  48 #define   AR8216_VTU_OP                 BITS(0, 3)
  49 #define   AR8216_VTU_OP_NOOP            0x0
  50 #define   AR8216_VTU_OP_FLUSH           0x1
  51 #define   AR8216_VTU_OP_LOAD            0x2
  52 #define   AR8216_VTU_OP_PURGE           0x3
  53 #define   AR8216_VTU_OP_REMOVE_PORT     0x4
  54 #define   AR8216_VTU_ACTIVE             BIT(3)
  55 #define   AR8216_VTU_FULL               BIT(4)
  56 #define   AR8216_VTU_PORT               BITS(8, 4)
  57 #define   AR8216_VTU_PORT_S             8
  58 #define   AR8216_VTU_VID                BITS(16, 12)
  59 #define   AR8216_VTU_VID_S              16
  60 #define   AR8216_VTU_PRIO               BITS(28, 3)
  61 #define   AR8216_VTU_PRIO_S             28
  62 #define   AR8216_VTU_PRIO_EN            BIT(31)
  63
  64 #define AR8216_REG_VTU_DATA             0x0044
  65 #define   AR8216_VTUDATA_MEMBER         BITS(0, 10)
  66 #define   AR8236_VTUDATA_MEMBER         BITS(0, 7)
  67 #define   AR8216_VTUDATA_VALID          BIT(11)
  68
  69 #define AR8216_REG_ATU                  0x0050
  70 #define   AR8216_ATU_OP                 BITS(0, 3)
  71 #define   AR8216_ATU_OP_NOOP            0x0
  72 #define   AR8216_ATU_OP_FLUSH           0x1
  73 #define   AR8216_ATU_OP_LOAD            0x2
  74 #define   AR8216_ATU_OP_PURGE           0x3
  75 #define   AR8216_ATU_OP_FLUSH_LOCKED    0x4
  76 #define   AR8216_ATU_OP_FLUSH_UNICAST   0x5
  77 #define   AR8216_ATU_OP_GET_NEXT        0x6
  78 #define   AR8216_ATU_ACTIVE             BIT(3)
  79 #define   AR8216_ATU_PORT_NUM           BITS(8, 4)
  80 #define   AR8216_ATU_FULL_VIO           BIT(12)
  81 #define   AR8216_ATU_ADDR4              BITS(16, 8)
  82 #define   AR8216_ATU_ADDR5              BITS(24, 8)
  83
  84 #define AR8216_REG_ATU_DATA             0x0054
  85 #define   AR8216_ATU_ADDR3              BITS(0, 8)
  86 #define   AR8216_ATU_ADDR2              BITS(8, 8)
  87 #define   AR8216_ATU_ADDR1              BITS(16, 8)
  88 #define   AR8216_ATU_ADDR0              BITS(24, 8)
  89
  90 #define AR8216_REG_ATU_CTRL             0x005C
  91 #define   AR8216_ATU_CTRL_AGE_EN        BIT(17)
  92 #define   AR8216_ATU_CTRL_AGE_TIME      BITS(0, 16)
  93 #define   AR8216_ATU_CTRL_AGE_TIME_S    0
  94
  95 #define AR8216_PORT_OFFSET(_i)          (0x0100 * (_i + 1))
  96 #define AR8216_REG_PORT_STATUS(_i)      (AR8216_PORT_OFFSET(_i) + 0x0000)
  97 #define   AR8216_PORT_STATUS_SPEED      BITS(0,2)
  98 #define   AR8216_PORT_STATUS_SPEED_S    0
  99 #define   AR8216_PORT_STATUS_TXMAC      BIT(2)
 100 #define   AR8216_PORT_STATUS_RXMAC      BIT(3)
 101 #define   AR8216_PORT_STATUS_TXFLOW     BIT(4)
 102 #define   AR8216_PORT_STATUS_RXFLOW     BIT(5)
 103 #define   AR8216_PORT_STATUS_DUPLEX     BIT(6)
 104 #define   AR8216_PORT_STATUS_LINK_UP    BIT(8)
 105 #define   AR8216_PORT_STATUS_LINK_AUTO  BIT(9)
 106 #define   AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
 107
 108 #define AR8216_REG_PORT_CTRL(_i)        (AR8216_PORT_OFFSET(_i) + 0x0004)
 109
 110 /* port forwarding state */
 111 #define   AR8216_PORT_CTRL_STATE        BITS(0, 3)
 112 #define   AR8216_PORT_CTRL_STATE_S      0
 113
 114 #define   AR8216_PORT_CTRL_LEARN_LOCK   BIT(7)
 115
 116 /* egress 802.1q mode */
 117 #define   AR8216_PORT_CTRL_VLAN_MODE    BITS(8, 2)
 118 #define   AR8216_PORT_CTRL_VLAN_MODE_S  8
 119
 120 #define   AR8216_PORT_CTRL_IGMP_SNOOP   BIT(10)
 121 #define   AR8216_PORT_CTRL_HEADER       BIT(11)
 122 #define   AR8216_PORT_CTRL_MAC_LOOP     BIT(12)
 123 #define   AR8216_PORT_CTRL_SINGLE_VLAN  BIT(13)
 124 #define   AR8216_PORT_CTRL_LEARN        BIT(14)
 125 #define   AR8216_PORT_CTRL_MIRROR_TX    BIT(16)
 126 #define   AR8216_PORT_CTRL_MIRROR_RX    BIT(17)
 127
 128 #define AR8216_REG_PORT_VLAN(_i)        (AR8216_PORT_OFFSET(_i) + 0x0008)
 129
 130 #define   AR8216_PORT_VLAN_DEFAULT_ID   BITS(0, 12)
 131 #define   AR8216_PORT_VLAN_DEFAULT_ID_S 0
 132
 133 #define   AR8216_PORT_VLAN_DEST_PORTS   BITS(16, 9)
 134 #define   AR8216_PORT_VLAN_DEST_PORTS_S 16
 135
 136 /* bit0 added to the priority field of egress frames */
 137 #define   AR8216_PORT_VLAN_TX_PRIO      BIT(27)
 138
 139 /* port default priority */
 140 #define   AR8216_PORT_VLAN_PRIORITY     BITS(28, 2)
 141 #define   AR8216_PORT_VLAN_PRIORITY_S   28
 142
 143 /* ingress 802.1q mode */
 144 #define   AR8216_PORT_VLAN_MODE         BITS(30, 2)
 145 #define   AR8216_PORT_VLAN_MODE_S       30
 146
 147 #define AR8216_REG_PORT_RATE(_i)        (AR8216_PORT_OFFSET(_i) + 0x000c)
 148 #define AR8216_REG_PORT_PRIO(_i)        (AR8216_PORT_OFFSET(_i) + 0x0010)
 149
 150
 151 #define AR8236_REG_PORT_VLAN(_i)        (AR8216_PORT_OFFSET((_i)) + 0x0008)
 152 #define   AR8236_PORT_VLAN_DEFAULT_ID   BITS(16, 12)
 153 #define   AR8236_PORT_VLAN_DEFAULT_ID_S 16
 154 #define   AR8236_PORT_VLAN_PRIORITY     BITS(29, 3)
 155 #define   AR8236_PORT_VLAN_PRIORITY_S   28
 156
 157 #define AR8236_REG_PORT_VLAN2(_i)       (AR8216_PORT_OFFSET((_i)) + 0x000c)
 158 #define   AR8236_PORT_VLAN2_MEMBER      BITS(16, 7)
 159 #define   AR8236_PORT_VLAN2_MEMBER_S    16
 160 #define   AR8236_PORT_VLAN2_TX_PRIO     BIT(23)
 161 #define   AR8236_PORT_VLAN2_VLAN_MODE   BITS(30, 2)
 162 #define   AR8236_PORT_VLAN2_VLAN_MODE_S 30
 163
 164 #define AR8327_NUM_PORTS        7
 165 #define AR8327_NUM_PHYS         5
 166 #define AR8327_PORTS_ALL        0x7f
 167
 168 #define AR8327_REG_MASK                         0x000
 169
 170 #define AR8327_REG_PAD0_MODE                    0x004
 171 #define AR8327_REG_PAD5_MODE                    0x008
 172 #define AR8327_REG_PAD6_MODE                    0x00c
 173 #define   AR8327_PAD_MAC_MII_RXCLK_SEL          BIT(0)
 174 #define   AR8327_PAD_MAC_MII_TXCLK_SEL          BIT(1)
 175 #define   AR8327_PAD_MAC_MII_EN                 BIT(2)
 176 #define   AR8327_PAD_MAC_GMII_RXCLK_SEL         BIT(4)
 177 #define   AR8327_PAD_MAC_GMII_TXCLK_SEL         BIT(5)
 178 #define   AR8327_PAD_MAC_GMII_EN                BIT(6)
 179 #define   AR8327_PAD_SGMII_EN                   BIT(7)
 180 #define   AR8327_PAD_PHY_MII_RXCLK_SEL          BIT(8)
 181 #define   AR8327_PAD_PHY_MII_TXCLK_SEL          BIT(9)
 182 #define   AR8327_PAD_PHY_MII_EN                 BIT(10)
 183 #define   AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL    BIT(11)
 184 #define   AR8327_PAD_PHY_GMII_RXCLK_SEL         BIT(12)
 185 #define   AR8327_PAD_PHY_GMII_TXCLK_SEL         BIT(13)
 186 #define   AR8327_PAD_PHY_GMII_EN                BIT(14)
 187 #define   AR8327_PAD_PHYX_GMII_EN               BIT(16)
 188 #define   AR8327_PAD_PHYX_RGMII_EN              BIT(17)
 189 #define   AR8327_PAD_PHYX_MII_EN                BIT(18)
 190 #define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL      BITS(20, 2)
 191 #define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S    20
 192 #define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL      BITS(22, 2)
 193 #define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S    22
 194 #define   AR8327_PAD_RGMII_RXCLK_DELAY_EN       BIT(24)
 195 #define   AR8327_PAD_RGMII_TXCLK_DELAY_EN       BIT(25)
 196 #define   AR8327_PAD_RGMII_EN                   BIT(26)
 197
 198 #define AR8327_REG_POWER_ON_STRIP               0x010
 199
 200 #define AR8327_REG_INT_STATUS0                  0x020
 201 #define   AR8327_INT0_VT_DONE                   BIT(20)
 202
 203 #define AR8327_REG_INT_STATUS1                  0x024
 204 #define AR8327_REG_INT_MASK0                    0x028
 205 #define AR8327_REG_INT_MASK1                    0x02c
 206 #define AR8327_REG_SERVICE_TAG                  0x048
 207 #define AR8327_REG_LED_CTRL0                    0x050
 208 #define AR8327_REG_LED_CTRL1                    0x054
 209 #define AR8327_REG_LED_CTRL2                    0x058
 210 #define AR8327_REG_LED_CTRL3                    0x05c
 211 #define AR8327_REG_MAC_ADDR0                    0x060
 212 #define AR8327_REG_MAC_ADDR1                    0x064
 213
 214 #define AR8327_REG_MAX_FRAME_SIZE               0x078
 215 #define   AR8327_MAX_FRAME_SIZE_MTU             BITS(0, 14)
 216
 217 #define AR8327_REG_PORT_STATUS(_i)              (0x07c + (_i) * 4)
 218
 219 #define AR8327_REG_HEADER_CTRL                  0x098
 220 #define AR8327_REG_PORT_HEADER(_i)              (0x09c + (_i) * 4)
 221
 222 #define AR8327_REG_PORT_VLAN0(_i)               (0x420 + (_i) * 0x8)
 223 #define   AR8327_PORT_VLAN0_DEF_SVID            BITS(0, 12)
 224 #define   AR8327_PORT_VLAN0_DEF_SVID_S          0
 225 #define   AR8327_PORT_VLAN0_DEF_CVID            BITS(16, 12)
 226 #define   AR8327_PORT_VLAN0_DEF_CVID_S          16
 227
 228 #define AR8327_REG_PORT_VLAN1(_i)               (0x424 + (_i) * 0x8)
 229 #define   AR8327_PORT_VLAN1_PORT_VLAN_PROP      BIT(6)
 230 #define   AR8327_PORT_VLAN1_OUT_MODE            BITS(12, 2)
 231 #define   AR8327_PORT_VLAN1_OUT_MODE_S          12
 232 #define   AR8327_PORT_VLAN1_OUT_MODE_UNMOD      0
 233 #define   AR8327_PORT_VLAN1_OUT_MODE_UNTAG      1
 234 #define   AR8327_PORT_VLAN1_OUT_MODE_TAG        2
 235 #define   AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH    3
 236
 237 #define AR8327_REG_ATU_DATA0                    0x600
 238 #define AR8327_REG_ATU_DATA1                    0x604
 239 #define AR8327_REG_ATU_DATA2                    0x608
 240
 241 #define AR8327_REG_ATU_FUNC                     0x60c
 242 #define   AR8327_ATU_FUNC_OP                    BITS(0, 4)
 243 #define   AR8327_ATU_FUNC_OP_NOOP               0x0
 244 #define   AR8327_ATU_FUNC_OP_FLUSH              0x1
 245 #define   AR8327_ATU_FUNC_OP_LOAD               0x2
 246 #define   AR8327_ATU_FUNC_OP_PURGE              0x3
 247 #define   AR8327_ATU_FUNC_OP_FLUSH_LOCKED       0x4
 248 #define   AR8327_ATU_FUNC_OP_FLUSH_UNICAST      0x5
 249 #define   AR8327_ATU_FUNC_OP_GET_NEXT           0x6
 250 #define   AR8327_ATU_FUNC_OP_SEARCH_MAC         0x7
 251 #define   AR8327_ATU_FUNC_OP_CHANGE_TRUNK       0x8
 252 #define   AR8327_ATU_FUNC_BUSY                  BIT(31)
 253
 254 #define AR8327_REG_VTU_FUNC0                    0x0610
 255 #define   AR8327_VTU_FUNC0_EG_MODE              BITS(4, 14)
 256 #define   AR8327_VTU_FUNC0_EG_MODE_S(_i)        (4 + (_i) * 2)
 257 #define   AR8327_VTU_FUNC0_EG_MODE_KEEP         0
 258 #define   AR8327_VTU_FUNC0_EG_MODE_UNTAG        1
 259 #define   AR8327_VTU_FUNC0_EG_MODE_TAG          2
 260 #define   AR8327_VTU_FUNC0_EG_MODE_NOT          3
 261 #define   AR8327_VTU_FUNC0_IVL                  BIT(19)
 262 #define   AR8327_VTU_FUNC0_VALID                BIT(20)
 263
 264 #define AR8327_REG_VTU_FUNC1                    0x0614
 265 #define   AR8327_VTU_FUNC1_OP                   BITS(0, 3)
 266 #define   AR8327_VTU_FUNC1_OP_NOOP              0
 267 #define   AR8327_VTU_FUNC1_OP_FLUSH             1
 268 #define   AR8327_VTU_FUNC1_OP_LOAD              2
 269 #define   AR8327_VTU_FUNC1_OP_PURGE             3
 270 #define   AR8327_VTU_FUNC1_OP_REMOVE_PORT       4
 271 #define   AR8327_VTU_FUNC1_OP_GET_NEXT          5
 272 #define   AR8327_VTU_FUNC1_OP_GET_ONE           6
 273 #define   AR8327_VTU_FUNC1_FULL                 BIT(4)
 274 #define   AR8327_VTU_FUNC1_PORT                 BIT(8, 4)
 275 #define   AR8327_VTU_FUNC1_PORT_S               8
 276 #define   AR8327_VTU_FUNC1_VID                  BIT(16, 12)
 277 #define   AR8327_VTU_FUNC1_VID_S                16
 278 #define   AR8327_VTU_FUNC1_BUSY                 BIT(31)
 279
 280 #define AR8327_REG_FWD_CTRL0                    0x620
 281 #define   AR8327_FWD_CTRL0_CPU_PORT_EN          BIT(10)
 282 #define   AR8327_FWD_CTRL0_MIRROR_PORT          BITS(4, 4)
 283 #define   AR8327_FWD_CTRL0_MIRROR_PORT_S        4
 284
 285 #define AR8327_REG_FWD_CTRL1                    0x624
 286 #define   AR8327_FWD_CTRL1_UC_FLOOD             BITS(0, 7)
 287 #define   AR8327_FWD_CTRL1_UC_FLOOD_S           0
 288 #define   AR8327_FWD_CTRL1_MC_FLOOD             BITS(8, 7)
 289 #define   AR8327_FWD_CTRL1_MC_FLOOD_S           8
 290 #define   AR8327_FWD_CTRL1_BC_FLOOD             BITS(16, 7)
 291 #define   AR8327_FWD_CTRL1_BC_FLOOD_S           16
 292 #define   AR8327_FWD_CTRL1_IGMP                 BITS(24, 7)
 293 #define   AR8327_FWD_CTRL1_IGMP_S               24
 294
 295 #define AR8327_REG_PORT_LOOKUP(_i)              (0x660 + (_i) * 0xc)
 296 #define   AR8327_PORT_LOOKUP_MEMBER             BITS(0, 7)
 297 #define   AR8327_PORT_LOOKUP_IN_MODE            BITS(8, 2)
 298 #define   AR8327_PORT_LOOKUP_IN_MODE_S          8
 299 #define   AR8327_PORT_LOOKUP_STATE              BITS(16, 3)
 300 #define   AR8327_PORT_LOOKUP_STATE_S            16
 301 #define   AR8327_PORT_LOOKUP_LEARN              BIT(20)
 302
 303 #define AR8327_REG_PORT_PRIO(_i)                (0x664 + (_i) * 0xc)
 304
 305 /* port speed */
 306 enum {
 307         AR8216_PORT_SPEED_10M = 0,
 308         AR8216_PORT_SPEED_100M = 1,
 309         AR8216_PORT_SPEED_1000M = 2,
 310         AR8216_PORT_SPEED_ERR = 3,
 311 };
 312
 313 /* ingress 802.1q mode */
 314 enum {
 315         AR8216_IN_PORT_ONLY = 0,
 316         AR8216_IN_PORT_FALLBACK = 1,
 317         AR8216_IN_VLAN_ONLY = 2,
 318         AR8216_IN_SECURE = 3
 319 };
 320
 321 /* egress 802.1q mode */
 322 enum {
 323         AR8216_OUT_KEEP = 0,
 324         AR8216_OUT_STRIP_VLAN = 1,
 325         AR8216_OUT_ADD_VLAN = 2
 326 };
 327
 328 /* port forwarding state */
 329 enum {
 330         AR8216_PORT_STATE_DISABLED = 0,
 331         AR8216_PORT_STATE_BLOCK = 1,
 332         AR8216_PORT_STATE_LISTEN = 2,
 333         AR8216_PORT_STATE_LEARN = 3,
 334         AR8216_PORT_STATE_FORWARD = 4
 335 };
 336
 337 #endif