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[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 /* Atheros specific MII registers */
37 #define MII_ATH_MMD_ADDR 0x0d
38 #define MII_ATH_MMD_DATA 0x0e
39 #define MII_ATH_DBG_ADDR 0x1d
40 #define MII_ATH_DBG_DATA 0x1e
41
42 #define AR8216_REG_CTRL 0x0000
43 #define AR8216_CTRL_REVISION BITS(0, 8)
44 #define AR8216_CTRL_REVISION_S 0
45 #define AR8216_CTRL_VERSION BITS(8, 8)
46 #define AR8216_CTRL_VERSION_S 8
47 #define AR8216_CTRL_RESET BIT(31)
48
49 #define AR8216_REG_FLOOD_MASK 0x002C
50 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
51 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
52 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
53 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
54
55 #define AR8216_REG_GLOBAL_CTRL 0x0030
56 #define AR8216_GCTRL_MTU BITS(0, 11)
57 #define AR8236_GCTRL_MTU BITS(0, 14)
58 #define AR8316_GCTRL_MTU BITS(0, 14)
59
60 #define AR8216_REG_VTU 0x0040
61 #define AR8216_VTU_OP BITS(0, 3)
62 #define AR8216_VTU_OP_NOOP 0x0
63 #define AR8216_VTU_OP_FLUSH 0x1
64 #define AR8216_VTU_OP_LOAD 0x2
65 #define AR8216_VTU_OP_PURGE 0x3
66 #define AR8216_VTU_OP_REMOVE_PORT 0x4
67 #define AR8216_VTU_ACTIVE BIT(3)
68 #define AR8216_VTU_FULL BIT(4)
69 #define AR8216_VTU_PORT BITS(8, 4)
70 #define AR8216_VTU_PORT_S 8
71 #define AR8216_VTU_VID BITS(16, 12)
72 #define AR8216_VTU_VID_S 16
73 #define AR8216_VTU_PRIO BITS(28, 3)
74 #define AR8216_VTU_PRIO_S 28
75 #define AR8216_VTU_PRIO_EN BIT(31)
76
77 #define AR8216_REG_VTU_DATA 0x0044
78 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
79 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
80 #define AR8216_VTUDATA_VALID BIT(11)
81
82 #define AR8216_REG_ATU 0x0050
83 #define AR8216_ATU_OP BITS(0, 3)
84 #define AR8216_ATU_OP_NOOP 0x0
85 #define AR8216_ATU_OP_FLUSH 0x1
86 #define AR8216_ATU_OP_LOAD 0x2
87 #define AR8216_ATU_OP_PURGE 0x3
88 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4
89 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5
90 #define AR8216_ATU_OP_GET_NEXT 0x6
91 #define AR8216_ATU_ACTIVE BIT(3)
92 #define AR8216_ATU_PORT_NUM BITS(8, 4)
93 #define AR8216_ATU_FULL_VIO BIT(12)
94 #define AR8216_ATU_ADDR4 BITS(16, 8)
95 #define AR8216_ATU_ADDR5 BITS(24, 8)
96
97 #define AR8216_REG_ATU_DATA 0x0054
98 #define AR8216_ATU_ADDR3 BITS(0, 8)
99 #define AR8216_ATU_ADDR2 BITS(8, 8)
100 #define AR8216_ATU_ADDR1 BITS(16, 8)
101 #define AR8216_ATU_ADDR0 BITS(24, 8)
102
103 #define AR8216_REG_ATU_CTRL 0x005C
104 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
105 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
106 #define AR8216_ATU_CTRL_AGE_TIME_S 0
107 #define AR8236_ATU_CTRL_RES BIT(20)
108
109 #define AR8216_REG_MIB_FUNC 0x0080
110 #define AR8216_MIB_TIMER BITS(0, 16)
111 #define AR8216_MIB_AT_HALF_EN BIT(16)
112 #define AR8216_MIB_BUSY BIT(17)
113 #define AR8216_MIB_FUNC BITS(24, 3)
114 #define AR8216_MIB_FUNC_S 24
115 #define AR8216_MIB_FUNC_NO_OP 0x0
116 #define AR8216_MIB_FUNC_FLUSH 0x1
117 #define AR8216_MIB_FUNC_CAPTURE 0x3
118 #define AR8236_MIB_EN BIT(30)
119
120 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
121 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
122 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
123
124 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
125 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
126 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
127 #define AR8216_PORT_STATUS_SPEED_S 0
128 #define AR8216_PORT_STATUS_TXMAC BIT(2)
129 #define AR8216_PORT_STATUS_RXMAC BIT(3)
130 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
131 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
132 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
133 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
134 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
135 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
136
137 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
138
139 /* port forwarding state */
140 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
141 #define AR8216_PORT_CTRL_STATE_S 0
142
143 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
144
145 /* egress 802.1q mode */
146 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
147 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
148
149 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
150 #define AR8216_PORT_CTRL_HEADER BIT(11)
151 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
152 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
153 #define AR8216_PORT_CTRL_LEARN BIT(14)
154 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
155 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
156
157 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
158
159 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
160 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
161
162 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
163 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
164
165 /* bit0 added to the priority field of egress frames */
166 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
167
168 /* port default priority */
169 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
170 #define AR8216_PORT_VLAN_PRIORITY_S 28
171
172 /* ingress 802.1q mode */
173 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
174 #define AR8216_PORT_VLAN_MODE_S 30
175
176 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
177 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
178
179 #define AR8216_STATS_RXBROAD 0x00
180 #define AR8216_STATS_RXPAUSE 0x04
181 #define AR8216_STATS_RXMULTI 0x08
182 #define AR8216_STATS_RXFCSERR 0x0c
183 #define AR8216_STATS_RXALIGNERR 0x10
184 #define AR8216_STATS_RXRUNT 0x14
185 #define AR8216_STATS_RXFRAGMENT 0x18
186 #define AR8216_STATS_RX64BYTE 0x1c
187 #define AR8216_STATS_RX128BYTE 0x20
188 #define AR8216_STATS_RX256BYTE 0x24
189 #define AR8216_STATS_RX512BYTE 0x28
190 #define AR8216_STATS_RX1024BYTE 0x2c
191 #define AR8216_STATS_RXMAXBYTE 0x30
192 #define AR8216_STATS_RXTOOLONG 0x34
193 #define AR8216_STATS_RXGOODBYTE 0x38
194 #define AR8216_STATS_RXBADBYTE 0x40
195 #define AR8216_STATS_RXOVERFLOW 0x48
196 #define AR8216_STATS_FILTERED 0x4c
197 #define AR8216_STATS_TXBROAD 0x50
198 #define AR8216_STATS_TXPAUSE 0x54
199 #define AR8216_STATS_TXMULTI 0x58
200 #define AR8216_STATS_TXUNDERRUN 0x5c
201 #define AR8216_STATS_TX64BYTE 0x60
202 #define AR8216_STATS_TX128BYTE 0x64
203 #define AR8216_STATS_TX256BYTE 0x68
204 #define AR8216_STATS_TX512BYTE 0x6c
205 #define AR8216_STATS_TX1024BYTE 0x70
206 #define AR8216_STATS_TXMAXBYTE 0x74
207 #define AR8216_STATS_TXOVERSIZE 0x78
208 #define AR8216_STATS_TXBYTE 0x7c
209 #define AR8216_STATS_TXCOLLISION 0x84
210 #define AR8216_STATS_TXABORTCOL 0x88
211 #define AR8216_STATS_TXMULTICOL 0x8c
212 #define AR8216_STATS_TXSINGLECOL 0x90
213 #define AR8216_STATS_TXEXCDEFER 0x94
214 #define AR8216_STATS_TXDEFER 0x98
215 #define AR8216_STATS_TXLATECOL 0x9c
216
217 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
218 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
219 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
220 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
221 #define AR8236_PORT_VLAN_PRIORITY_S 28
222
223 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
224 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
225 #define AR8236_PORT_VLAN2_MEMBER_S 16
226 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
227 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
228 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
229
230 #define AR8236_STATS_RXBROAD 0x00
231 #define AR8236_STATS_RXPAUSE 0x04
232 #define AR8236_STATS_RXMULTI 0x08
233 #define AR8236_STATS_RXFCSERR 0x0c
234 #define AR8236_STATS_RXALIGNERR 0x10
235 #define AR8236_STATS_RXRUNT 0x14
236 #define AR8236_STATS_RXFRAGMENT 0x18
237 #define AR8236_STATS_RX64BYTE 0x1c
238 #define AR8236_STATS_RX128BYTE 0x20
239 #define AR8236_STATS_RX256BYTE 0x24
240 #define AR8236_STATS_RX512BYTE 0x28
241 #define AR8236_STATS_RX1024BYTE 0x2c
242 #define AR8236_STATS_RX1518BYTE 0x30
243 #define AR8236_STATS_RXMAXBYTE 0x34
244 #define AR8236_STATS_RXTOOLONG 0x38
245 #define AR8236_STATS_RXGOODBYTE 0x3c
246 #define AR8236_STATS_RXBADBYTE 0x44
247 #define AR8236_STATS_RXOVERFLOW 0x4c
248 #define AR8236_STATS_FILTERED 0x50
249 #define AR8236_STATS_TXBROAD 0x54
250 #define AR8236_STATS_TXPAUSE 0x58
251 #define AR8236_STATS_TXMULTI 0x5c
252 #define AR8236_STATS_TXUNDERRUN 0x60
253 #define AR8236_STATS_TX64BYTE 0x64
254 #define AR8236_STATS_TX128BYTE 0x68
255 #define AR8236_STATS_TX256BYTE 0x6c
256 #define AR8236_STATS_TX512BYTE 0x70
257 #define AR8236_STATS_TX1024BYTE 0x74
258 #define AR8236_STATS_TX1518BYTE 0x78
259 #define AR8236_STATS_TXMAXBYTE 0x7c
260 #define AR8236_STATS_TXOVERSIZE 0x80
261 #define AR8236_STATS_TXBYTE 0x84
262 #define AR8236_STATS_TXCOLLISION 0x8c
263 #define AR8236_STATS_TXABORTCOL 0x90
264 #define AR8236_STATS_TXMULTICOL 0x94
265 #define AR8236_STATS_TXSINGLECOL 0x98
266 #define AR8236_STATS_TXEXCDEFER 0x9c
267 #define AR8236_STATS_TXDEFER 0xa0
268 #define AR8236_STATS_TXLATECOL 0xa4
269
270 #define AR8316_REG_POSTRIP 0x0008
271 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
272 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
273 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
274 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
275 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
276 #define AR8316_POSTRIP_RTL_MODE BIT(5)
277 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
278 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
279 #define AR8316_POSTRIP_SERDES_EN BIT(8)
280 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
281 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
282 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
283 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
284 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
285 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
286 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
287 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
288 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
289 #define AR8316_POSTRIP_MAN_EN BIT(18)
290 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
291 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
292 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
293 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
294 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
295 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
296 #define AR8316_POSTRIP_SPI_EN BIT(25)
297 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
298 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
299
300 /* port speed */
301 enum {
302 AR8216_PORT_SPEED_10M = 0,
303 AR8216_PORT_SPEED_100M = 1,
304 AR8216_PORT_SPEED_1000M = 2,
305 AR8216_PORT_SPEED_ERR = 3,
306 };
307
308 /* ingress 802.1q mode */
309 enum {
310 AR8216_IN_PORT_ONLY = 0,
311 AR8216_IN_PORT_FALLBACK = 1,
312 AR8216_IN_VLAN_ONLY = 2,
313 AR8216_IN_SECURE = 3
314 };
315
316 /* egress 802.1q mode */
317 enum {
318 AR8216_OUT_KEEP = 0,
319 AR8216_OUT_STRIP_VLAN = 1,
320 AR8216_OUT_ADD_VLAN = 2
321 };
322
323 /* port forwarding state */
324 enum {
325 AR8216_PORT_STATE_DISABLED = 0,
326 AR8216_PORT_STATE_BLOCK = 1,
327 AR8216_PORT_STATE_LISTEN = 2,
328 AR8216_PORT_STATE_LEARN = 3,
329 AR8216_PORT_STATE_FORWARD = 4
330 };
331
332 enum {
333 AR8XXX_VER_AR8216 = 0x01,
334 AR8XXX_VER_AR8236 = 0x03,
335 AR8XXX_VER_AR8316 = 0x10,
336 AR8XXX_VER_AR8327 = 0x12,
337 AR8XXX_VER_AR8337 = 0x13,
338 };
339
340 struct ar8xxx_priv;
341
342 struct ar8xxx_mib_desc {
343 unsigned int size;
344 unsigned int offset;
345 const char *name;
346 };
347
348 struct ar8xxx_chip {
349 unsigned long caps;
350 bool config_at_probe;
351 bool mii_lo_first;
352
353 /* parameters to calculate REG_PORT_STATS_BASE */
354 unsigned reg_port_stats_start;
355 unsigned reg_port_stats_length;
356
357 int (*hw_init)(struct ar8xxx_priv *priv);
358 void (*cleanup)(struct ar8xxx_priv *priv);
359
360 const char *name;
361 int vlans;
362 int ports;
363 const struct switch_dev_ops *swops;
364
365 void (*init_globals)(struct ar8xxx_priv *priv);
366 void (*init_port)(struct ar8xxx_priv *priv, int port);
367 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
368 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
369 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
370 int (*atu_flush)(struct ar8xxx_priv *priv);
371 void (*vtu_flush)(struct ar8xxx_priv *priv);
372 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
373 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
374 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
375 int (*sw_hw_apply)(struct switch_dev *dev);
376
377 const struct ar8xxx_mib_desc *mib_decs;
378 unsigned num_mibs;
379 unsigned mib_func;
380 };
381
382 struct ar8xxx_priv {
383 struct switch_dev dev;
384 struct mii_bus *mii_bus;
385 struct phy_device *phy;
386
387 int (*get_port_link)(unsigned port);
388
389 const struct net_device_ops *ndo_old;
390 struct net_device_ops ndo;
391 struct mutex reg_mutex;
392 u8 chip_ver;
393 u8 chip_rev;
394 const struct ar8xxx_chip *chip;
395 void *chip_data;
396 bool initialized;
397 bool port4_phy;
398 char buf[2048];
399 bool link_up[AR8X16_MAX_PORTS];
400
401 bool init;
402
403 struct mutex mib_lock;
404 struct delayed_work mib_work;
405 int mib_next_port;
406 u64 *mib_stats;
407
408 struct list_head list;
409 unsigned int use_count;
410
411 /* all fields below are cleared on reset */
412 bool vlan;
413 u16 vlan_id[AR8X16_MAX_VLANS];
414 u8 vlan_table[AR8X16_MAX_VLANS];
415 u8 vlan_tagged;
416 u16 pvid[AR8X16_MAX_PORTS];
417
418 /* mirroring */
419 bool mirror_rx;
420 bool mirror_tx;
421 int source_port;
422 int monitor_port;
423 };
424
425 u32
426 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
427 void
428 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
429 u32
430 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
431
432 void
433 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
434 u16 dbg_addr, u16 dbg_data);
435 void
436 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data);
437 u16
438 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr);
439 void
440 ar8xxx_phy_init(struct ar8xxx_priv *priv);
441 int
442 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
443 struct switch_val *val);
444 int
445 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
446 struct switch_val *val);
447 int
448 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
449 const struct switch_attr *attr,
450 struct switch_val *val);
451 int
452 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
453 const struct switch_attr *attr,
454 struct switch_val *val);
455 int
456 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
457 const struct switch_attr *attr,
458 struct switch_val *val);
459 int
460 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
461 const struct switch_attr *attr,
462 struct switch_val *val);
463 int
464 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
465 const struct switch_attr *attr,
466 struct switch_val *val);
467 int
468 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
469 const struct switch_attr *attr,
470 struct switch_val *val);
471 int
472 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
473 const struct switch_attr *attr,
474 struct switch_val *val);
475 int
476 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
477 const struct switch_attr *attr,
478 struct switch_val *val);
479 int
480 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
481 const struct switch_attr *attr,
482 struct switch_val *val);
483 int
484 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
485 int
486 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
487 int
488 ar8xxx_sw_hw_apply(struct switch_dev *dev);
489 int
490 ar8xxx_sw_reset_switch(struct switch_dev *dev);
491 int
492 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
493 struct switch_port_link *link);
494 int
495 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
496 const struct switch_attr *attr,
497 struct switch_val *val);
498 int
499 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
500 const struct switch_attr *attr,
501 struct switch_val *val);
502 int
503 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
504
505 static inline struct ar8xxx_priv *
506 swdev_to_ar8xxx(struct switch_dev *swdev)
507 {
508 return container_of(swdev, struct ar8xxx_priv, dev);
509 }
510
511 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
512 {
513 return priv->chip->caps & AR8XXX_CAP_GIGE;
514 }
515
516 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
517 {
518 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
519 }
520
521 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
522 {
523 return priv->chip_ver == AR8XXX_VER_AR8216;
524 }
525
526 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
527 {
528 return priv->chip_ver == AR8XXX_VER_AR8236;
529 }
530
531 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
532 {
533 return priv->chip_ver == AR8XXX_VER_AR8316;
534 }
535
536 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
537 {
538 return priv->chip_ver == AR8XXX_VER_AR8327;
539 }
540
541 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
542 {
543 return priv->chip_ver == AR8XXX_VER_AR8337;
544 }
545
546 static inline void
547 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
548 {
549 ar8xxx_rmw(priv, reg, 0, val);
550 }
551
552 static inline void
553 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
554 {
555 ar8xxx_rmw(priv, reg, val, 0);
556 }
557
558 static inline void
559 wait_for_page_switch(void)
560 {
561 udelay(5);
562 }
563
564 #endif
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