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[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
37 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
38
39 /* Atheros specific MII registers */
40 #define MII_ATH_MMD_ADDR 0x0d
41 #define MII_ATH_MMD_DATA 0x0e
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
44
45 #define AR8216_REG_CTRL 0x0000
46 #define AR8216_CTRL_REVISION BITS(0, 8)
47 #define AR8216_CTRL_REVISION_S 0
48 #define AR8216_CTRL_VERSION BITS(8, 8)
49 #define AR8216_CTRL_VERSION_S 8
50 #define AR8216_CTRL_RESET BIT(31)
51
52 #define AR8216_REG_FLOOD_MASK 0x002C
53 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
54 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
55 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
56 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
57
58 #define AR8216_REG_GLOBAL_CTRL 0x0030
59 #define AR8216_GCTRL_MTU BITS(0, 11)
60 #define AR8236_GCTRL_MTU BITS(0, 14)
61 #define AR8316_GCTRL_MTU BITS(0, 14)
62
63 #define AR8216_REG_VTU 0x0040
64 #define AR8216_VTU_OP BITS(0, 3)
65 #define AR8216_VTU_OP_NOOP 0x0
66 #define AR8216_VTU_OP_FLUSH 0x1
67 #define AR8216_VTU_OP_LOAD 0x2
68 #define AR8216_VTU_OP_PURGE 0x3
69 #define AR8216_VTU_OP_REMOVE_PORT 0x4
70 #define AR8216_VTU_ACTIVE BIT(3)
71 #define AR8216_VTU_FULL BIT(4)
72 #define AR8216_VTU_PORT BITS(8, 4)
73 #define AR8216_VTU_PORT_S 8
74 #define AR8216_VTU_VID BITS(16, 12)
75 #define AR8216_VTU_VID_S 16
76 #define AR8216_VTU_PRIO BITS(28, 3)
77 #define AR8216_VTU_PRIO_S 28
78 #define AR8216_VTU_PRIO_EN BIT(31)
79
80 #define AR8216_REG_VTU_DATA 0x0044
81 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
82 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
83 #define AR8216_VTUDATA_VALID BIT(11)
84
85 #define AR8216_REG_ATU_FUNC0 0x0050
86 #define AR8216_ATU_OP BITS(0, 3)
87 #define AR8216_ATU_OP_NOOP 0x0
88 #define AR8216_ATU_OP_FLUSH 0x1
89 #define AR8216_ATU_OP_LOAD 0x2
90 #define AR8216_ATU_OP_PURGE 0x3
91 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
92 #define AR8216_ATU_OP_FLUSH_PORT 0x5
93 #define AR8216_ATU_OP_GET_NEXT 0x6
94 #define AR8216_ATU_ACTIVE BIT(3)
95 #define AR8216_ATU_PORT_NUM BITS(8, 4)
96 #define AR8216_ATU_PORT_NUM_S 8
97 #define AR8216_ATU_FULL_VIO BIT(12)
98 #define AR8216_ATU_ADDR5 BITS(16, 8)
99 #define AR8216_ATU_ADDR5_S 16
100 #define AR8216_ATU_ADDR4 BITS(24, 8)
101 #define AR8216_ATU_ADDR4_S 24
102
103 #define AR8216_REG_ATU_FUNC1 0x0054
104 #define AR8216_ATU_ADDR3 BITS(0, 8)
105 #define AR8216_ATU_ADDR3_S 0
106 #define AR8216_ATU_ADDR2 BITS(8, 8)
107 #define AR8216_ATU_ADDR2_S 8
108 #define AR8216_ATU_ADDR1 BITS(16, 8)
109 #define AR8216_ATU_ADDR1_S 16
110 #define AR8216_ATU_ADDR0 BITS(24, 8)
111 #define AR8216_ATU_ADDR0_S 24
112
113 #define AR8216_REG_ATU_FUNC2 0x0058
114 #define AR8216_ATU_PORTS BITS(0, 6)
115 #define AR8216_ATU_PORT0 BIT(0)
116 #define AR8216_ATU_PORT1 BIT(1)
117 #define AR8216_ATU_PORT2 BIT(2)
118 #define AR8216_ATU_PORT3 BIT(3)
119 #define AR8216_ATU_PORT4 BIT(4)
120 #define AR8216_ATU_PORT5 BIT(5)
121 #define AR8216_ATU_STATUS BITS(16, 4)
122 #define AR8216_ATU_STATUS_S 16
123
124 #define AR8216_REG_ATU_CTRL 0x005C
125 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
126 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
127 #define AR8216_ATU_CTRL_AGE_TIME_S 0
128 #define AR8236_ATU_CTRL_RES BIT(20)
129
130 #define AR8216_REG_MIB_FUNC 0x0080
131 #define AR8216_MIB_TIMER BITS(0, 16)
132 #define AR8216_MIB_AT_HALF_EN BIT(16)
133 #define AR8216_MIB_BUSY BIT(17)
134 #define AR8216_MIB_FUNC BITS(24, 3)
135 #define AR8216_MIB_FUNC_S 24
136 #define AR8216_MIB_FUNC_NO_OP 0x0
137 #define AR8216_MIB_FUNC_FLUSH 0x1
138 #define AR8216_MIB_FUNC_CAPTURE 0x3
139 #define AR8236_MIB_EN BIT(30)
140
141 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
142 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
143 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
144
145 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
146 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
147 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
148 #define AR8216_PORT_STATUS_SPEED_S 0
149 #define AR8216_PORT_STATUS_TXMAC BIT(2)
150 #define AR8216_PORT_STATUS_RXMAC BIT(3)
151 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
152 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
153 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
154 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
155 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
156 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
157
158 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
159
160 /* port forwarding state */
161 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
162 #define AR8216_PORT_CTRL_STATE_S 0
163
164 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
165
166 /* egress 802.1q mode */
167 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
168 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
169
170 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
171 #define AR8216_PORT_CTRL_HEADER BIT(11)
172 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
173 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
174 #define AR8216_PORT_CTRL_LEARN BIT(14)
175 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
176 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
177
178 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
179
180 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
181 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
182
183 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
184 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
185
186 /* bit0 added to the priority field of egress frames */
187 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
188
189 /* port default priority */
190 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
191 #define AR8216_PORT_VLAN_PRIORITY_S 28
192
193 /* ingress 802.1q mode */
194 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
195 #define AR8216_PORT_VLAN_MODE_S 30
196
197 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
198 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
199
200 #define AR8216_STATS_RXBROAD 0x00
201 #define AR8216_STATS_RXPAUSE 0x04
202 #define AR8216_STATS_RXMULTI 0x08
203 #define AR8216_STATS_RXFCSERR 0x0c
204 #define AR8216_STATS_RXALIGNERR 0x10
205 #define AR8216_STATS_RXRUNT 0x14
206 #define AR8216_STATS_RXFRAGMENT 0x18
207 #define AR8216_STATS_RX64BYTE 0x1c
208 #define AR8216_STATS_RX128BYTE 0x20
209 #define AR8216_STATS_RX256BYTE 0x24
210 #define AR8216_STATS_RX512BYTE 0x28
211 #define AR8216_STATS_RX1024BYTE 0x2c
212 #define AR8216_STATS_RXMAXBYTE 0x30
213 #define AR8216_STATS_RXTOOLONG 0x34
214 #define AR8216_STATS_RXGOODBYTE 0x38
215 #define AR8216_STATS_RXBADBYTE 0x40
216 #define AR8216_STATS_RXOVERFLOW 0x48
217 #define AR8216_STATS_FILTERED 0x4c
218 #define AR8216_STATS_TXBROAD 0x50
219 #define AR8216_STATS_TXPAUSE 0x54
220 #define AR8216_STATS_TXMULTI 0x58
221 #define AR8216_STATS_TXUNDERRUN 0x5c
222 #define AR8216_STATS_TX64BYTE 0x60
223 #define AR8216_STATS_TX128BYTE 0x64
224 #define AR8216_STATS_TX256BYTE 0x68
225 #define AR8216_STATS_TX512BYTE 0x6c
226 #define AR8216_STATS_TX1024BYTE 0x70
227 #define AR8216_STATS_TXMAXBYTE 0x74
228 #define AR8216_STATS_TXOVERSIZE 0x78
229 #define AR8216_STATS_TXBYTE 0x7c
230 #define AR8216_STATS_TXCOLLISION 0x84
231 #define AR8216_STATS_TXABORTCOL 0x88
232 #define AR8216_STATS_TXMULTICOL 0x8c
233 #define AR8216_STATS_TXSINGLECOL 0x90
234 #define AR8216_STATS_TXEXCDEFER 0x94
235 #define AR8216_STATS_TXDEFER 0x98
236 #define AR8216_STATS_TXLATECOL 0x9c
237
238 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
239 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
240 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
241 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
242 #define AR8236_PORT_VLAN_PRIORITY_S 28
243
244 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
245 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
246 #define AR8236_PORT_VLAN2_MEMBER_S 16
247 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
248 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
249 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
250
251 #define AR8236_STATS_RXBROAD 0x00
252 #define AR8236_STATS_RXPAUSE 0x04
253 #define AR8236_STATS_RXMULTI 0x08
254 #define AR8236_STATS_RXFCSERR 0x0c
255 #define AR8236_STATS_RXALIGNERR 0x10
256 #define AR8236_STATS_RXRUNT 0x14
257 #define AR8236_STATS_RXFRAGMENT 0x18
258 #define AR8236_STATS_RX64BYTE 0x1c
259 #define AR8236_STATS_RX128BYTE 0x20
260 #define AR8236_STATS_RX256BYTE 0x24
261 #define AR8236_STATS_RX512BYTE 0x28
262 #define AR8236_STATS_RX1024BYTE 0x2c
263 #define AR8236_STATS_RX1518BYTE 0x30
264 #define AR8236_STATS_RXMAXBYTE 0x34
265 #define AR8236_STATS_RXTOOLONG 0x38
266 #define AR8236_STATS_RXGOODBYTE 0x3c
267 #define AR8236_STATS_RXBADBYTE 0x44
268 #define AR8236_STATS_RXOVERFLOW 0x4c
269 #define AR8236_STATS_FILTERED 0x50
270 #define AR8236_STATS_TXBROAD 0x54
271 #define AR8236_STATS_TXPAUSE 0x58
272 #define AR8236_STATS_TXMULTI 0x5c
273 #define AR8236_STATS_TXUNDERRUN 0x60
274 #define AR8236_STATS_TX64BYTE 0x64
275 #define AR8236_STATS_TX128BYTE 0x68
276 #define AR8236_STATS_TX256BYTE 0x6c
277 #define AR8236_STATS_TX512BYTE 0x70
278 #define AR8236_STATS_TX1024BYTE 0x74
279 #define AR8236_STATS_TX1518BYTE 0x78
280 #define AR8236_STATS_TXMAXBYTE 0x7c
281 #define AR8236_STATS_TXOVERSIZE 0x80
282 #define AR8236_STATS_TXBYTE 0x84
283 #define AR8236_STATS_TXCOLLISION 0x8c
284 #define AR8236_STATS_TXABORTCOL 0x90
285 #define AR8236_STATS_TXMULTICOL 0x94
286 #define AR8236_STATS_TXSINGLECOL 0x98
287 #define AR8236_STATS_TXEXCDEFER 0x9c
288 #define AR8236_STATS_TXDEFER 0xa0
289 #define AR8236_STATS_TXLATECOL 0xa4
290
291 #define AR8316_REG_POSTRIP 0x0008
292 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
293 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
294 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
295 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
296 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
297 #define AR8316_POSTRIP_RTL_MODE BIT(5)
298 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
299 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
300 #define AR8316_POSTRIP_SERDES_EN BIT(8)
301 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
302 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
303 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
304 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
305 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
306 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
307 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
308 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
309 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
310 #define AR8316_POSTRIP_MAN_EN BIT(18)
311 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
312 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
313 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
314 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
315 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
316 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
317 #define AR8316_POSTRIP_SPI_EN BIT(25)
318 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
319 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
320
321 /* port speed */
322 enum {
323 AR8216_PORT_SPEED_10M = 0,
324 AR8216_PORT_SPEED_100M = 1,
325 AR8216_PORT_SPEED_1000M = 2,
326 AR8216_PORT_SPEED_ERR = 3,
327 };
328
329 /* ingress 802.1q mode */
330 enum {
331 AR8216_IN_PORT_ONLY = 0,
332 AR8216_IN_PORT_FALLBACK = 1,
333 AR8216_IN_VLAN_ONLY = 2,
334 AR8216_IN_SECURE = 3
335 };
336
337 /* egress 802.1q mode */
338 enum {
339 AR8216_OUT_KEEP = 0,
340 AR8216_OUT_STRIP_VLAN = 1,
341 AR8216_OUT_ADD_VLAN = 2
342 };
343
344 /* port forwarding state */
345 enum {
346 AR8216_PORT_STATE_DISABLED = 0,
347 AR8216_PORT_STATE_BLOCK = 1,
348 AR8216_PORT_STATE_LISTEN = 2,
349 AR8216_PORT_STATE_LEARN = 3,
350 AR8216_PORT_STATE_FORWARD = 4
351 };
352
353 enum {
354 AR8XXX_VER_AR8216 = 0x01,
355 AR8XXX_VER_AR8236 = 0x03,
356 AR8XXX_VER_AR8316 = 0x10,
357 AR8XXX_VER_AR8327 = 0x12,
358 AR8XXX_VER_AR8337 = 0x13,
359 };
360
361 #define AR8XXX_NUM_ARL_RECORDS 100
362
363 enum arl_op {
364 AR8XXX_ARL_INITIALIZE,
365 AR8XXX_ARL_GET_NEXT
366 };
367
368 struct arl_entry {
369 u8 port;
370 u8 mac[6];
371 };
372
373 struct ar8xxx_priv;
374
375 struct ar8xxx_mib_desc {
376 unsigned int size;
377 unsigned int offset;
378 const char *name;
379 };
380
381 struct ar8xxx_chip {
382 unsigned long caps;
383 bool config_at_probe;
384 bool mii_lo_first;
385
386 /* parameters to calculate REG_PORT_STATS_BASE */
387 unsigned reg_port_stats_start;
388 unsigned reg_port_stats_length;
389
390 unsigned reg_arl_ctrl;
391
392 int (*hw_init)(struct ar8xxx_priv *priv);
393 void (*cleanup)(struct ar8xxx_priv *priv);
394
395 const char *name;
396 int vlans;
397 int ports;
398 const struct switch_dev_ops *swops;
399
400 void (*init_globals)(struct ar8xxx_priv *priv);
401 void (*init_port)(struct ar8xxx_priv *priv, int port);
402 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
403 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
404 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
405 int (*atu_flush)(struct ar8xxx_priv *priv);
406 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
407 void (*vtu_flush)(struct ar8xxx_priv *priv);
408 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
409 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
410 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
411 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
412 u32 *status, enum arl_op op);
413 int (*sw_hw_apply)(struct switch_dev *dev);
414
415 const struct ar8xxx_mib_desc *mib_decs;
416 unsigned num_mibs;
417 unsigned mib_func;
418 };
419
420 struct ar8xxx_priv {
421 struct switch_dev dev;
422 struct mii_bus *mii_bus;
423 struct phy_device *phy;
424
425 int (*get_port_link)(unsigned port);
426
427 const struct net_device_ops *ndo_old;
428 struct net_device_ops ndo;
429 struct mutex reg_mutex;
430 u8 chip_ver;
431 u8 chip_rev;
432 const struct ar8xxx_chip *chip;
433 void *chip_data;
434 bool initialized;
435 bool port4_phy;
436 char buf[2048];
437 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
438 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
439 bool link_up[AR8X16_MAX_PORTS];
440
441 bool init;
442
443 struct mutex mib_lock;
444 struct delayed_work mib_work;
445 int mib_next_port;
446 u64 *mib_stats;
447
448 struct list_head list;
449 unsigned int use_count;
450
451 /* all fields below are cleared on reset */
452 bool vlan;
453 u16 vlan_id[AR8X16_MAX_VLANS];
454 u8 vlan_table[AR8X16_MAX_VLANS];
455 u8 vlan_tagged;
456 u16 pvid[AR8X16_MAX_PORTS];
457 int arl_age_time;
458
459 /* mirroring */
460 bool mirror_rx;
461 bool mirror_tx;
462 int source_port;
463 int monitor_port;
464 };
465
466 u32
467 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
468 void
469 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
470 u32
471 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
472 void
473 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
474 u32
475 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
476
477 void
478 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
479 u16 dbg_addr, u16 dbg_data);
480 void
481 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
482 u16
483 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
484 void
485 ar8xxx_phy_init(struct ar8xxx_priv *priv);
486 int
487 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
488 struct switch_val *val);
489 int
490 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
491 struct switch_val *val);
492 int
493 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
494 const struct switch_attr *attr,
495 struct switch_val *val);
496 int
497 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
498 const struct switch_attr *attr,
499 struct switch_val *val);
500 int
501 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
502 const struct switch_attr *attr,
503 struct switch_val *val);
504 int
505 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
506 const struct switch_attr *attr,
507 struct switch_val *val);
508 int
509 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
510 const struct switch_attr *attr,
511 struct switch_val *val);
512 int
513 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
514 const struct switch_attr *attr,
515 struct switch_val *val);
516 int
517 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
518 const struct switch_attr *attr,
519 struct switch_val *val);
520 int
521 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
522 const struct switch_attr *attr,
523 struct switch_val *val);
524 int
525 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
526 const struct switch_attr *attr,
527 struct switch_val *val);
528 int
529 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
530 int
531 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
532 int
533 ar8xxx_sw_hw_apply(struct switch_dev *dev);
534 int
535 ar8xxx_sw_reset_switch(struct switch_dev *dev);
536 int
537 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
538 struct switch_port_link *link);
539 int
540 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
541 const struct switch_attr *attr,
542 struct switch_val *val);
543 int
544 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
545 const struct switch_attr *attr,
546 struct switch_val *val);
547 int
548 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
549 const struct switch_attr *attr,
550 struct switch_val *val);
551 int
552 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
553 const struct switch_attr *attr,
554 struct switch_val *val);
555 int
556 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
557 const struct switch_attr *attr,
558 struct switch_val *val);
559 int
560 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
561 const struct switch_attr *attr,
562 struct switch_val *val);
563 int
564 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
565 const struct switch_attr *attr,
566 struct switch_val *val);
567 int
568 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
569
570 static inline struct ar8xxx_priv *
571 swdev_to_ar8xxx(struct switch_dev *swdev)
572 {
573 return container_of(swdev, struct ar8xxx_priv, dev);
574 }
575
576 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
577 {
578 return priv->chip->caps & AR8XXX_CAP_GIGE;
579 }
580
581 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
582 {
583 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
584 }
585
586 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
587 {
588 return priv->chip_ver == AR8XXX_VER_AR8216;
589 }
590
591 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
592 {
593 return priv->chip_ver == AR8XXX_VER_AR8236;
594 }
595
596 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
597 {
598 return priv->chip_ver == AR8XXX_VER_AR8316;
599 }
600
601 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
602 {
603 return priv->chip_ver == AR8XXX_VER_AR8327;
604 }
605
606 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
607 {
608 return priv->chip_ver == AR8XXX_VER_AR8337;
609 }
610
611 static inline void
612 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
613 {
614 ar8xxx_rmw(priv, reg, 0, val);
615 }
616
617 static inline void
618 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
619 {
620 ar8xxx_rmw(priv, reg, val, 0);
621 }
622
623 static inline void
624 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
625 {
626 regaddr >>= 1;
627 *r1 = regaddr & 0x1e;
628
629 regaddr >>= 5;
630 *r2 = regaddr & 0x7;
631
632 regaddr >>= 3;
633 *page = regaddr & 0x1ff;
634 }
635
636 static inline void
637 wait_for_page_switch(void)
638 {
639 udelay(5);
640 }
641
642 #endif
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