target/linux/generic/files/drivers/net/phy/ar8327.h

   1 /*
   2  * ar8327.h: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __AR8327_H
  18 #define __AR8327_H
  19
  20 #define AR8327_NUM_PORTS        7
  21 #define AR8327_NUM_LEDS         15
  22 #define AR8327_PORTS_ALL        0x7f
  23 #define AR8327_NUM_LED_CTRL_REGS        4
  24
  25 #define AR8327_REG_MASK                         0x000
  26
  27 #define AR8327_REG_PAD0_MODE                    0x004
  28 #define AR8327_REG_PAD5_MODE                    0x008
  29 #define AR8327_REG_PAD6_MODE                    0x00c
  30 #define   AR8327_PAD_MAC_MII_RXCLK_SEL          BIT(0)
  31 #define   AR8327_PAD_MAC_MII_TXCLK_SEL          BIT(1)
  32 #define   AR8327_PAD_MAC_MII_EN                 BIT(2)
  33 #define   AR8327_PAD_MAC_GMII_RXCLK_SEL         BIT(4)
  34 #define   AR8327_PAD_MAC_GMII_TXCLK_SEL         BIT(5)
  35 #define   AR8327_PAD_MAC_GMII_EN                BIT(6)
  36 #define   AR8327_PAD_SGMII_EN                   BIT(7)
  37 #define   AR8327_PAD_PHY_MII_RXCLK_SEL          BIT(8)
  38 #define   AR8327_PAD_PHY_MII_TXCLK_SEL          BIT(9)
  39 #define   AR8327_PAD_PHY_MII_EN                 BIT(10)
  40 #define   AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL    BIT(11)
  41 #define   AR8327_PAD_PHY_GMII_RXCLK_SEL         BIT(12)
  42 #define   AR8327_PAD_PHY_GMII_TXCLK_SEL         BIT(13)
  43 #define   AR8327_PAD_PHY_GMII_EN                BIT(14)
  44 #define   AR8327_PAD_PHYX_GMII_EN               BIT(16)
  45 #define   AR8327_PAD_PHYX_RGMII_EN              BIT(17)
  46 #define   AR8327_PAD_PHYX_MII_EN                BIT(18)
  47 #define   AR8327_PAD_SGMII_DELAY_EN             BIT(19)
  48 #define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL      BITS(20, 2)
  49 #define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S    20
  50 #define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL      BITS(22, 2)
  51 #define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S    22
  52 #define   AR8327_PAD_RGMII_RXCLK_DELAY_EN       BIT(24)
  53 #define   AR8327_PAD_RGMII_TXCLK_DELAY_EN       BIT(25)
  54 #define   AR8327_PAD_RGMII_EN                   BIT(26)
  55
  56 #define AR8327_REG_POWER_ON_STRIP               0x010
  57 #define   AR8327_POWER_ON_STRIP_POWER_ON_SEL    BIT(31)
  58 #define   AR8327_POWER_ON_STRIP_LED_OPEN_EN     BIT(24)
  59 #define   AR8327_POWER_ON_STRIP_SERDES_AEN      BIT(7)
  60
  61 #define AR8327_REG_INT_STATUS0                  0x020
  62 #define   AR8327_INT0_VT_DONE                   BIT(20)
  63
  64 #define AR8327_REG_INT_STATUS1                  0x024
  65 #define AR8327_REG_INT_MASK0                    0x028
  66 #define AR8327_REG_INT_MASK1                    0x02c
  67
  68 #define AR8327_REG_MODULE_EN                    0x030
  69 #define   AR8327_MODULE_EN_MIB                  BIT(0)
  70
  71 #define AR8327_REG_MIB_FUNC                     0x034
  72 #define   AR8327_MIB_CPU_KEEP                   BIT(20)
  73
  74 #define AR8327_REG_SERVICE_TAG                  0x048
  75 #define AR8327_REG_LED_CTRL(_i)                 (0x050 + (_i) * 4)
  76 #define AR8327_REG_LED_CTRL0                    0x050
  77 #define AR8327_REG_LED_CTRL1                    0x054
  78 #define AR8327_REG_LED_CTRL2                    0x058
  79 #define AR8327_REG_LED_CTRL3                    0x05c
  80 #define AR8327_REG_MAC_ADDR0                    0x060
  81 #define AR8327_REG_MAC_ADDR1                    0x064
  82
  83 #define AR8327_REG_MAX_FRAME_SIZE               0x078
  84 #define   AR8327_MAX_FRAME_SIZE_MTU             BITS(0, 14)
  85
  86 #define AR8327_REG_PORT_STATUS(_i)              (0x07c + (_i) * 4)
  87 #define   AR8327_PORT_STATUS_TXFLOW_AUTO        BIT(10)
  88 #define   AR8327_PORT_STATUS_RXFLOW_AUTO        BIT(11)
  89
  90 #define AR8327_REG_HEADER_CTRL                  0x098
  91 #define AR8327_REG_PORT_HEADER(_i)              (0x09c + (_i) * 4)
  92
  93 #define AR8327_REG_SGMII_CTRL                   0x0e0
  94 #define   AR8327_SGMII_CTRL_EN_PLL              BIT(1)
  95 #define   AR8327_SGMII_CTRL_EN_RX               BIT(2)
  96 #define   AR8327_SGMII_CTRL_EN_TX               BIT(3)
  97
  98 #define AR8327_REG_EEE_CTRL                     0x100
  99 #define   AR8327_EEE_CTRL_DISABLE_PHY(_i)       BIT(4 + (_i) * 2)
 100
 101 #define AR8327_REG_PORT_VLAN0(_i)               (0x420 + (_i) * 0x8)
 102 #define   AR8327_PORT_VLAN0_DEF_SVID            BITS(0, 12)
 103 #define   AR8327_PORT_VLAN0_DEF_SVID_S          0
 104 #define   AR8327_PORT_VLAN0_DEF_CVID            BITS(16, 12)
 105 #define   AR8327_PORT_VLAN0_DEF_CVID_S          16
 106
 107 #define AR8327_REG_PORT_VLAN1(_i)               (0x424 + (_i) * 0x8)
 108 #define   AR8327_PORT_VLAN1_PORT_VLAN_PROP      BIT(6)
 109 #define   AR8327_PORT_VLAN1_OUT_MODE            BITS(12, 2)
 110 #define   AR8327_PORT_VLAN1_OUT_MODE_S          12
 111 #define   AR8327_PORT_VLAN1_OUT_MODE_UNMOD      0
 112 #define   AR8327_PORT_VLAN1_OUT_MODE_UNTAG      1
 113 #define   AR8327_PORT_VLAN1_OUT_MODE_TAG        2
 114 #define   AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH    3
 115
 116 #define AR8327_REG_ATU_DATA0                    0x600
 117 #define   AR8327_ATU_ADDR0                      BITS(0, 8)
 118 #define   AR8327_ATU_ADDR0_S                    0
 119 #define   AR8327_ATU_ADDR1                      BITS(8, 8)
 120 #define   AR8327_ATU_ADDR1_S                    8
 121 #define   AR8327_ATU_ADDR2                      BITS(16, 8)
 122 #define   AR8327_ATU_ADDR2_S                    16
 123 #define   AR8327_ATU_ADDR3                      BITS(24, 8)
 124 #define   AR8327_ATU_ADDR3_S                    24
 125 #define AR8327_REG_ATU_DATA1                    0x604
 126 #define   AR8327_ATU_ADDR4                      BITS(0, 8)
 127 #define   AR8327_ATU_ADDR4_S                    0
 128 #define   AR8327_ATU_ADDR5                      BITS(8, 8)
 129 #define   AR8327_ATU_ADDR5_S                    8
 130 #define   AR8327_ATU_PORTS                      BITS(16, 7)
 131 #define   AR8327_ATU_PORT0                      BIT(16)
 132 #define   AR8327_ATU_PORT1                      BIT(17)
 133 #define   AR8327_ATU_PORT2                      BIT(18)
 134 #define   AR8327_ATU_PORT3                      BIT(19)
 135 #define   AR8327_ATU_PORT4                      BIT(20)
 136 #define   AR8327_ATU_PORT5                      BIT(21)
 137 #define   AR8327_ATU_PORT6                      BIT(22)
 138 #define AR8327_REG_ATU_DATA2                    0x608
 139 #define   AR8327_ATU_STATUS                     BITS(0, 4)
 140
 141 #define AR8327_REG_ATU_FUNC                     0x60c
 142 #define   AR8327_ATU_FUNC_OP                    BITS(0, 4)
 143 #define   AR8327_ATU_FUNC_OP_NOOP               0x0
 144 #define   AR8327_ATU_FUNC_OP_FLUSH              0x1
 145 #define   AR8327_ATU_FUNC_OP_LOAD               0x2
 146 #define   AR8327_ATU_FUNC_OP_PURGE              0x3
 147 #define   AR8327_ATU_FUNC_OP_FLUSH_LOCKED       0x4
 148 #define   AR8327_ATU_FUNC_OP_FLUSH_UNICAST      0x5
 149 #define   AR8327_ATU_FUNC_OP_GET_NEXT           0x6
 150 #define   AR8327_ATU_FUNC_OP_SEARCH_MAC         0x7
 151 #define   AR8327_ATU_FUNC_OP_CHANGE_TRUNK       0x8
 152 #define   AR8327_ATU_FUNC_BUSY                  BIT(31)
 153
 154 #define AR8327_REG_VTU_FUNC0                    0x0610
 155 #define   AR8327_VTU_FUNC0_EG_MODE              BITS(4, 14)
 156 #define   AR8327_VTU_FUNC0_EG_MODE_S(_i)        (4 + (_i) * 2)
 157 #define   AR8327_VTU_FUNC0_EG_MODE_KEEP         0
 158 #define   AR8327_VTU_FUNC0_EG_MODE_UNTAG        1
 159 #define   AR8327_VTU_FUNC0_EG_MODE_TAG          2
 160 #define   AR8327_VTU_FUNC0_EG_MODE_NOT          3
 161 #define   AR8327_VTU_FUNC0_IVL                  BIT(19)
 162 #define   AR8327_VTU_FUNC0_VALID                BIT(20)
 163
 164 #define AR8327_REG_VTU_FUNC1                    0x0614
 165 #define   AR8327_VTU_FUNC1_OP                   BITS(0, 3)
 166 #define   AR8327_VTU_FUNC1_OP_NOOP              0
 167 #define   AR8327_VTU_FUNC1_OP_FLUSH             1
 168 #define   AR8327_VTU_FUNC1_OP_LOAD              2
 169 #define   AR8327_VTU_FUNC1_OP_PURGE             3
 170 #define   AR8327_VTU_FUNC1_OP_REMOVE_PORT       4
 171 #define   AR8327_VTU_FUNC1_OP_GET_NEXT          5
 172 #define   AR8327_VTU_FUNC1_OP_GET_ONE           6
 173 #define   AR8327_VTU_FUNC1_FULL                 BIT(4)
 174 #define   AR8327_VTU_FUNC1_PORT                 BIT(8, 4)
 175 #define   AR8327_VTU_FUNC1_PORT_S               8
 176 #define   AR8327_VTU_FUNC1_VID                  BIT(16, 12)
 177 #define   AR8327_VTU_FUNC1_VID_S                16
 178 #define   AR8327_VTU_FUNC1_BUSY                 BIT(31)
 179
 180 #define AR8327_REG_FWD_CTRL0                    0x620
 181 #define   AR8327_FWD_CTRL0_CPU_PORT_EN          BIT(10)
 182 #define   AR8327_FWD_CTRL0_MIRROR_PORT          BITS(4, 4)
 183 #define   AR8327_FWD_CTRL0_MIRROR_PORT_S        4
 184
 185 #define AR8327_REG_FWD_CTRL1                    0x624
 186 #define   AR8327_FWD_CTRL1_UC_FLOOD             BITS(0, 7)
 187 #define   AR8327_FWD_CTRL1_UC_FLOOD_S           0
 188 #define   AR8327_FWD_CTRL1_MC_FLOOD             BITS(8, 7)
 189 #define   AR8327_FWD_CTRL1_MC_FLOOD_S           8
 190 #define   AR8327_FWD_CTRL1_BC_FLOOD             BITS(16, 7)
 191 #define   AR8327_FWD_CTRL1_BC_FLOOD_S           16
 192 #define   AR8327_FWD_CTRL1_IGMP                 BITS(24, 7)
 193 #define   AR8327_FWD_CTRL1_IGMP_S               24
 194
 195 #define AR8327_REG_PORT_LOOKUP(_i)              (0x660 + (_i) * 0xc)
 196 #define   AR8327_PORT_LOOKUP_MEMBER             BITS(0, 7)
 197 #define   AR8327_PORT_LOOKUP_IN_MODE            BITS(8, 2)
 198 #define   AR8327_PORT_LOOKUP_IN_MODE_S          8
 199 #define   AR8327_PORT_LOOKUP_STATE              BITS(16, 3)
 200 #define   AR8327_PORT_LOOKUP_STATE_S            16
 201 #define   AR8327_PORT_LOOKUP_LEARN              BIT(20)
 202 #define   AR8327_PORT_LOOKUP_ING_MIRROR_EN      BIT(25)
 203
 204 #define AR8327_REG_PORT_PRIO(_i)                (0x664 + (_i) * 0xc)
 205
 206 #define AR8327_REG_PORT_HOL_CTRL1(_i)           (0x974 + (_i) * 0x8)
 207 #define   AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN    BIT(16)
 208
 209 #define AR8337_PAD_MAC06_EXCHANGE_EN            BIT(31)
 210
 211 enum ar8327_led_pattern {
 212         AR8327_LED_PATTERN_OFF = 0,
 213         AR8327_LED_PATTERN_BLINK,
 214         AR8327_LED_PATTERN_ON,
 215         AR8327_LED_PATTERN_RULE,
 216 };
 217
 218 struct ar8327_led_entry {
 219         unsigned reg;
 220         unsigned shift;
 221 };
 222
 223 struct ar8327_led {
 224         struct led_classdev cdev;
 225         struct ar8xxx_priv *sw_priv;
 226
 227         char *name;
 228         bool active_low;
 229         u8 led_num;
 230         enum ar8327_led_mode mode;
 231
 232         struct mutex mutex;
 233         spinlock_t lock;
 234         struct work_struct led_work;
 235         bool enable_hw_mode;
 236         enum ar8327_led_pattern pattern;
 237 };
 238
 239 struct ar8327_data {
 240         u32 port0_status;
 241         u32 port6_status;
 242
 243         struct ar8327_led **leds;
 244         unsigned int num_leds;
 245
 246         /* all fields below are cleared on reset */
 247         bool eee[AR8XXX_NUM_PHYS];
 248 };
 249
 250 #endif