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b53: Make b53_switch_init static
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "b53_regs.h"
30 #include "b53_priv.h"
31
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 { },
77 };
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 { }
124 };
125
126 /* MIB counters */
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
163 { }
164 };
165
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
167 {
168 unsigned int i;
169
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
171
172 for (i = 0; i < 10; i++) {
173 u8 vta;
174
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
177 return 0;
178
179 usleep_range(100, 200);
180 }
181
182 return -EIO;
183 }
184
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
186 u16 untag)
187 {
188 if (is5325(dev)) {
189 u32 entry = 0;
190
191 if (members) {
192 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
193 members;
194 if (dev->core_rev >= 3)
195 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
196 else
197 entry |= VA_VALID_25;
198 }
199
200 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
201 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
202 VTA_RW_STATE_WR | VTA_RW_OP_EN);
203 } else if (is5365(dev)) {
204 u16 entry = 0;
205
206 if (members)
207 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
208 members | VA_VALID_65;
209
210 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
211 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
212 VTA_RW_STATE_WR | VTA_RW_OP_EN);
213 } else {
214 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
215 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
216 (untag << VTE_UNTAG_S) | members);
217
218 b53_do_vlan_op(dev, VTA_CMD_WRITE);
219 }
220 }
221
222 void b53_set_forwarding(struct b53_device *dev, int enable)
223 {
224 u8 mgmt;
225
226 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
227
228 if (enable)
229 mgmt |= SM_SW_FWD_EN;
230 else
231 mgmt &= ~SM_SW_FWD_EN;
232
233 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
234 }
235
236 static void b53_enable_vlan(struct b53_device *dev, int enable)
237 {
238 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
239
240 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
243
244 if (is5325(dev) || is5365(dev)) {
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
247 } else if (is63xx(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
250 } else {
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
253 }
254
255 mgmt &= ~SM_SW_FWD_MODE;
256
257 if (enable) {
258 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
259 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
260 vc4 &= ~VC4_ING_VID_CHECK_MASK;
261 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
262 vc5 |= VC5_DROP_VTABLE_MISS;
263
264 if (is5325(dev))
265 vc0 &= ~VC0_RESERVED_1;
266
267 if (is5325(dev) || is5365(dev))
268 vc1 |= VC1_RX_MCST_TAG_EN;
269
270 if (!is5325(dev) && !is5365(dev)) {
271 if (dev->allow_vid_4095)
272 vc5 |= VC5_VID_FFF_EN;
273 else
274 vc5 &= ~VC5_VID_FFF_EN;
275 }
276 } else {
277 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
278 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
279 vc4 &= ~VC4_ING_VID_CHECK_MASK;
280 vc5 &= ~VC5_DROP_VTABLE_MISS;
281
282 if (is5325(dev) || is5365(dev))
283 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
284 else
285 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
286
287 if (is5325(dev) || is5365(dev))
288 vc1 &= ~VC1_RX_MCST_TAG_EN;
289
290 if (!is5325(dev) && !is5365(dev))
291 vc5 &= ~VC5_VID_FFF_EN;
292 }
293
294 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
295 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
296
297 if (is5325(dev) || is5365(dev)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev) && enable)
300 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
301 VC3_HIGH_8BIT_EN);
302 else
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
304
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
307 } else if (is63xx(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
311 } else {
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
315 }
316
317 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
318 }
319
320 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
321 {
322 u32 port_mask = 0;
323 u16 max_size = JMS_MIN_SIZE;
324
325 if (is5325(dev) || is5365(dev))
326 return -EINVAL;
327
328 if (enable) {
329 port_mask = dev->enabled_ports;
330 max_size = JMS_MAX_SIZE;
331 if (allow_10_100)
332 port_mask |= JPM_10_100_JUMBO_EN;
333 }
334
335 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
336 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
337 }
338
339 static int b53_flush_arl(struct b53_device *dev)
340 {
341 unsigned int i;
342
343 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
344 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
345
346 for (i = 0; i < 10; i++) {
347 u8 fast_age_ctrl;
348
349 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
350 &fast_age_ctrl);
351
352 if (!(fast_age_ctrl & FAST_AGE_DONE))
353 return 0;
354
355 mdelay(1);
356 }
357
358 pr_warn("time out while flushing ARL\n");
359
360 return -EINVAL;
361 }
362
363 static void b53_enable_ports(struct b53_device *dev)
364 {
365 unsigned i;
366
367 b53_for_each_port(dev, i) {
368 u8 port_ctrl;
369 u16 pvlan_mask;
370
371 /*
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
374 */
375 if (dev->enable_vlan || is_cpu_port(dev, i))
376 pvlan_mask = 0x1ff;
377 else if (is531x5(dev) || is5301x(dev))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask = BIT(dev->sw_dev.cpu_port);
380 else
381 pvlan_mask = BIT(B53_CPU_PORT);
382
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
385 i = B53_CPU_PORT;
386
387 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
390 else if (i == B53_CPU_PORT)
391 port_ctrl = PORT_CTRL_RX_BCST_EN |
392 PORT_CTRL_RX_MCST_EN |
393 PORT_CTRL_RX_UCST_EN;
394 else
395 port_ctrl = 0;
396
397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
398 pvlan_mask);
399
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
402 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
403 port_ctrl);
404 }
405 }
406
407 static void b53_enable_mib(struct b53_device *dev)
408 {
409 u8 gc;
410
411 b53_read8(dev, B53_CTRL_PAGE, B53_GLOBAL_CONFIG, &gc);
412
413 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
414
415 b53_write8(dev, B53_CTRL_PAGE, B53_GLOBAL_CONFIG, gc);
416 }
417
418 static int b53_apply(struct b53_device *dev)
419 {
420 int i;
421
422 /* clear all vlan entries */
423 if (is5325(dev) || is5365(dev)) {
424 for (i = 1; i < dev->sw_dev.vlans; i++)
425 b53_set_vlan_entry(dev, i, 0, 0);
426 } else {
427 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
428 }
429
430 b53_enable_vlan(dev, dev->enable_vlan);
431
432 /* fill VLAN table */
433 if (dev->enable_vlan) {
434 for (i = 0; i < dev->sw_dev.vlans; i++) {
435 struct b53_vlan *vlan = &dev->vlans[i];
436
437 if (!vlan->members)
438 continue;
439
440 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
441 }
442
443 b53_for_each_port(dev, i)
444 b53_write16(dev, B53_VLAN_PAGE,
445 B53_VLAN_PORT_DEF_TAG(i),
446 dev->ports[i].pvid);
447 } else {
448 b53_for_each_port(dev, i)
449 b53_write16(dev, B53_VLAN_PAGE,
450 B53_VLAN_PORT_DEF_TAG(i), 1);
451
452 }
453
454 b53_enable_ports(dev);
455
456 if (!is5325(dev) && !is5365(dev))
457 b53_set_jumbo(dev, dev->enable_jumbo, 1);
458
459 return 0;
460 }
461
462 static void b53_switch_reset_gpio(struct b53_device *dev)
463 {
464 int gpio = dev->reset_gpio;
465
466 if (gpio < 0)
467 return;
468
469 /*
470 * Reset sequence: RESET low(50ms)->high(20ms)
471 */
472 gpio_set_value(gpio, 0);
473 mdelay(50);
474
475 gpio_set_value(gpio, 1);
476 mdelay(20);
477
478 dev->current_page = 0xff;
479 }
480
481 static int b53_switch_reset(struct b53_device *dev)
482 {
483 u8 mgmt;
484
485 b53_switch_reset_gpio(dev);
486
487 if (is539x(dev)) {
488 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
489 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
490 }
491
492 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
493
494 if (!(mgmt & SM_SW_FWD_EN)) {
495 mgmt &= ~SM_SW_FWD_MODE;
496 mgmt |= SM_SW_FWD_EN;
497
498 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
499 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
500
501 if (!(mgmt & SM_SW_FWD_EN)) {
502 pr_err("Failed to enable switch!\n");
503 return -EINVAL;
504 }
505 }
506
507 /* enable all ports */
508 b53_enable_ports(dev);
509
510 /* configure MII port if necessary */
511 if (is5325(dev)) {
512 u8 mii_port_override;
513
514 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
515 &mii_port_override);
516 /* reverse mii needs to be enabled */
517 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
518 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
519 mii_port_override | PORT_OVERRIDE_RV_MII_25);
520 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
521 &mii_port_override);
522
523 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
524 pr_err("Failed to enable reverse MII mode\n");
525 return -EINVAL;
526 }
527 }
528 } else if ((is531x5(dev) || is5301x(dev)) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
529 u8 mii_port_override;
530
531 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
532 &mii_port_override);
533 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
534 mii_port_override | PORT_OVERRIDE_EN |
535 PORT_OVERRIDE_LINK);
536 }
537
538 b53_enable_mib(dev);
539
540 return b53_flush_arl(dev);
541 }
542
543 /*
544 * Swconfig glue functions
545 */
546
547 static int b53_global_get_vlan_enable(struct switch_dev *dev,
548 const struct switch_attr *attr,
549 struct switch_val *val)
550 {
551 struct b53_device *priv = sw_to_b53(dev);
552
553 val->value.i = priv->enable_vlan;
554
555 return 0;
556 }
557
558 static int b53_global_set_vlan_enable(struct switch_dev *dev,
559 const struct switch_attr *attr,
560 struct switch_val *val)
561 {
562 struct b53_device *priv = sw_to_b53(dev);
563
564 priv->enable_vlan = val->value.i;
565
566 return 0;
567 }
568
569 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
570 const struct switch_attr *attr,
571 struct switch_val *val)
572 {
573 struct b53_device *priv = sw_to_b53(dev);
574
575 val->value.i = priv->enable_jumbo;
576
577 return 0;
578 }
579
580 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
581 const struct switch_attr *attr,
582 struct switch_val *val)
583 {
584 struct b53_device *priv = sw_to_b53(dev);
585
586 priv->enable_jumbo = val->value.i;
587
588 return 0;
589 }
590
591 static int b53_global_get_4095_enable(struct switch_dev *dev,
592 const struct switch_attr *attr,
593 struct switch_val *val)
594 {
595 struct b53_device *priv = sw_to_b53(dev);
596
597 val->value.i = priv->allow_vid_4095;
598
599 return 0;
600 }
601
602 static int b53_global_set_4095_enable(struct switch_dev *dev,
603 const struct switch_attr *attr,
604 struct switch_val *val)
605 {
606 struct b53_device *priv = sw_to_b53(dev);
607
608 priv->allow_vid_4095 = val->value.i;
609
610 return 0;
611 }
612
613 static int b53_global_get_ports(struct switch_dev *dev,
614 const struct switch_attr *attr,
615 struct switch_val *val)
616 {
617 struct b53_device *priv = sw_to_b53(dev);
618
619 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
620 priv->enabled_ports);
621 val->value.s = priv->buf;
622
623 return 0;
624 }
625
626 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
627 {
628 struct b53_device *priv = sw_to_b53(dev);
629
630 *val = priv->ports[port].pvid;
631
632 return 0;
633 }
634
635 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
636 {
637 struct b53_device *priv = sw_to_b53(dev);
638
639 if (val > 15 && is5325(priv))
640 return -EINVAL;
641 if (val == 4095 && !priv->allow_vid_4095)
642 return -EINVAL;
643
644 priv->ports[port].pvid = val;
645
646 return 0;
647 }
648
649 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
650 {
651 struct b53_device *priv = sw_to_b53(dev);
652 struct switch_port *port = &val->value.ports[0];
653 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
654 int i;
655
656 val->len = 0;
657
658 if (!vlan->members)
659 return 0;
660
661 for (i = 0; i < dev->ports; i++) {
662 if (!(vlan->members & BIT(i)))
663 continue;
664
665
666 if (!(vlan->untag & BIT(i)))
667 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
668 else
669 port->flags = 0;
670
671 port->id = i;
672 val->len++;
673 port++;
674 }
675
676 return 0;
677 }
678
679 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
680 {
681 struct b53_device *priv = sw_to_b53(dev);
682 struct switch_port *port;
683 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
684 int i;
685
686 /* only BCM5325 and BCM5365 supports VID 0 */
687 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
688 return -EINVAL;
689
690 /* VLAN 4095 needs special handling */
691 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
692 return -EINVAL;
693
694 port = &val->value.ports[0];
695 vlan->members = 0;
696 vlan->untag = 0;
697 for (i = 0; i < val->len; i++, port++) {
698 vlan->members |= BIT(port->id);
699
700 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
701 vlan->untag |= BIT(port->id);
702 priv->ports[port->id].pvid = val->port_vlan;
703 };
704 }
705
706 /* ignore disabled ports */
707 vlan->members &= priv->enabled_ports;
708 vlan->untag &= priv->enabled_ports;
709
710 return 0;
711 }
712
713 static int b53_port_get_link(struct switch_dev *dev, int port,
714 struct switch_port_link *link)
715 {
716 struct b53_device *priv = sw_to_b53(dev);
717
718 if (is_cpu_port(priv, port)) {
719 link->link = 1;
720 link->duplex = 1;
721 link->speed = is5325(priv) || is5365(priv) ?
722 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
723 link->aneg = 0;
724 } else if (priv->enabled_ports & BIT(port)) {
725 u32 speed;
726 u16 lnk, duplex;
727
728 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
729 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
730
731 lnk = (lnk >> port) & 1;
732 duplex = (duplex >> port) & 1;
733
734 if (is5325(priv) || is5365(priv)) {
735 u16 tmp;
736
737 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
738 speed = SPEED_PORT_FE(tmp, port);
739 } else {
740 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
741 speed = SPEED_PORT_GE(speed, port);
742 }
743
744 link->link = lnk;
745 if (lnk) {
746 link->duplex = duplex;
747 switch (speed) {
748 case SPEED_STAT_10M:
749 link->speed = SWITCH_PORT_SPEED_10;
750 break;
751 case SPEED_STAT_100M:
752 link->speed = SWITCH_PORT_SPEED_100;
753 break;
754 case SPEED_STAT_1000M:
755 link->speed = SWITCH_PORT_SPEED_1000;
756 break;
757 }
758 }
759
760 link->aneg = 1;
761 } else {
762 link->link = 0;
763 }
764
765 return 0;
766
767 }
768
769 static int b53_global_reset_switch(struct switch_dev *dev)
770 {
771 struct b53_device *priv = sw_to_b53(dev);
772
773 /* reset vlans */
774 priv->enable_vlan = 0;
775 priv->enable_jumbo = 0;
776 priv->allow_vid_4095 = 0;
777
778 memset(priv->vlans, 0, sizeof(priv->vlans) * dev->vlans);
779 memset(priv->ports, 0, sizeof(priv->ports) * dev->ports);
780
781 return b53_switch_reset(priv);
782 }
783
784 static int b53_global_apply_config(struct switch_dev *dev)
785 {
786 struct b53_device *priv = sw_to_b53(dev);
787
788 /* disable switching */
789 b53_set_forwarding(priv, 0);
790
791 b53_apply(priv);
792
793 /* enable switching */
794 b53_set_forwarding(priv, 1);
795
796 return 0;
797 }
798
799
800 static int b53_global_reset_mib(struct switch_dev *dev,
801 const struct switch_attr *attr,
802 struct switch_val *val)
803 {
804 struct b53_device *priv = sw_to_b53(dev);
805 u8 gc;
806
807 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
808
809 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
810 mdelay(1);
811 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
812 mdelay(1);
813
814 return 0;
815 }
816
817 static int b53_port_get_mib(struct switch_dev *sw_dev,
818 const struct switch_attr *attr,
819 struct switch_val *val)
820 {
821 struct b53_device *dev = sw_to_b53(sw_dev);
822 const struct b53_mib_desc *mibs;
823 int port = val->port_vlan;
824 int len = 0;
825
826 if (!(BIT(port) & dev->enabled_ports))
827 return -1;
828
829 if (is5365(dev)) {
830 if (port == 5)
831 port = 8;
832
833 mibs = b53_mibs_65;
834 } else if (is63xx(dev)) {
835 mibs = b53_mibs_63xx;
836 } else {
837 mibs = b53_mibs;
838 }
839
840 dev->buf[0] = 0;
841
842 for (; mibs->size > 0; mibs++) {
843 u64 val;
844
845 if (mibs->size == 8) {
846 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
847 } else {
848 u32 val32;
849
850 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
851 &val32);
852 val = val32;
853 }
854
855 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
856 "%-20s: %llu\n", mibs->name, val);
857 }
858
859 val->len = len;
860 val->value.s = dev->buf;
861
862 return 0;
863 }
864
865 static struct switch_attr b53_global_ops_25[] = {
866 {
867 .type = SWITCH_TYPE_INT,
868 .name = "enable_vlan",
869 .description = "Enable VLAN mode",
870 .set = b53_global_set_vlan_enable,
871 .get = b53_global_get_vlan_enable,
872 .max = 1,
873 },
874 {
875 .type = SWITCH_TYPE_STRING,
876 .name = "ports",
877 .description = "Available ports (as bitmask)",
878 .get = b53_global_get_ports,
879 },
880 };
881
882 static struct switch_attr b53_global_ops_65[] = {
883 {
884 .type = SWITCH_TYPE_INT,
885 .name = "enable_vlan",
886 .description = "Enable VLAN mode",
887 .set = b53_global_set_vlan_enable,
888 .get = b53_global_get_vlan_enable,
889 .max = 1,
890 },
891 {
892 .type = SWITCH_TYPE_STRING,
893 .name = "ports",
894 .description = "Available ports (as bitmask)",
895 .get = b53_global_get_ports,
896 },
897 {
898 .type = SWITCH_TYPE_INT,
899 .name = "reset_mib",
900 .description = "Reset MIB counters",
901 .set = b53_global_reset_mib,
902 },
903 };
904
905 static struct switch_attr b53_global_ops[] = {
906 {
907 .type = SWITCH_TYPE_INT,
908 .name = "enable_vlan",
909 .description = "Enable VLAN mode",
910 .set = b53_global_set_vlan_enable,
911 .get = b53_global_get_vlan_enable,
912 .max = 1,
913 },
914 {
915 .type = SWITCH_TYPE_STRING,
916 .name = "ports",
917 .description = "Available Ports (as bitmask)",
918 .get = b53_global_get_ports,
919 },
920 {
921 .type = SWITCH_TYPE_INT,
922 .name = "reset_mib",
923 .description = "Reset MIB counters",
924 .set = b53_global_reset_mib,
925 },
926 {
927 .type = SWITCH_TYPE_INT,
928 .name = "enable_jumbo",
929 .description = "Enable Jumbo Frames",
930 .set = b53_global_set_jumbo_enable,
931 .get = b53_global_get_jumbo_enable,
932 .max = 1,
933 },
934 {
935 .type = SWITCH_TYPE_INT,
936 .name = "allow_vid_4095",
937 .description = "Allow VID 4095",
938 .set = b53_global_set_4095_enable,
939 .get = b53_global_get_4095_enable,
940 .max = 1,
941 },
942 };
943
944 static struct switch_attr b53_port_ops[] = {
945 {
946 .type = SWITCH_TYPE_STRING,
947 .name = "mib",
948 .description = "Get port's MIB counters",
949 .get = b53_port_get_mib,
950 },
951 };
952
953 static struct switch_attr b53_no_ops[] = {
954 };
955
956 static const struct switch_dev_ops b53_switch_ops_25 = {
957 .attr_global = {
958 .attr = b53_global_ops_25,
959 .n_attr = ARRAY_SIZE(b53_global_ops_25),
960 },
961 .attr_port = {
962 .attr = b53_no_ops,
963 .n_attr = ARRAY_SIZE(b53_no_ops),
964 },
965 .attr_vlan = {
966 .attr = b53_no_ops,
967 .n_attr = ARRAY_SIZE(b53_no_ops),
968 },
969
970 .get_vlan_ports = b53_vlan_get_ports,
971 .set_vlan_ports = b53_vlan_set_ports,
972 .get_port_pvid = b53_port_get_pvid,
973 .set_port_pvid = b53_port_set_pvid,
974 .apply_config = b53_global_apply_config,
975 .reset_switch = b53_global_reset_switch,
976 .get_port_link = b53_port_get_link,
977 };
978
979 static const struct switch_dev_ops b53_switch_ops_65 = {
980 .attr_global = {
981 .attr = b53_global_ops_65,
982 .n_attr = ARRAY_SIZE(b53_global_ops_65),
983 },
984 .attr_port = {
985 .attr = b53_port_ops,
986 .n_attr = ARRAY_SIZE(b53_port_ops),
987 },
988 .attr_vlan = {
989 .attr = b53_no_ops,
990 .n_attr = ARRAY_SIZE(b53_no_ops),
991 },
992
993 .get_vlan_ports = b53_vlan_get_ports,
994 .set_vlan_ports = b53_vlan_set_ports,
995 .get_port_pvid = b53_port_get_pvid,
996 .set_port_pvid = b53_port_set_pvid,
997 .apply_config = b53_global_apply_config,
998 .reset_switch = b53_global_reset_switch,
999 .get_port_link = b53_port_get_link,
1000 };
1001
1002 static const struct switch_dev_ops b53_switch_ops = {
1003 .attr_global = {
1004 .attr = b53_global_ops,
1005 .n_attr = ARRAY_SIZE(b53_global_ops),
1006 },
1007 .attr_port = {
1008 .attr = b53_port_ops,
1009 .n_attr = ARRAY_SIZE(b53_port_ops),
1010 },
1011 .attr_vlan = {
1012 .attr = b53_no_ops,
1013 .n_attr = ARRAY_SIZE(b53_no_ops),
1014 },
1015
1016 .get_vlan_ports = b53_vlan_get_ports,
1017 .set_vlan_ports = b53_vlan_set_ports,
1018 .get_port_pvid = b53_port_get_pvid,
1019 .set_port_pvid = b53_port_set_pvid,
1020 .apply_config = b53_global_apply_config,
1021 .reset_switch = b53_global_reset_switch,
1022 .get_port_link = b53_port_get_link,
1023 };
1024
1025 struct b53_chip_data {
1026 u32 chip_id;
1027 const char *dev_name;
1028 const char *alias;
1029 u16 vlans;
1030 u16 enabled_ports;
1031 u8 cpu_port;
1032 u8 vta_regs[3];
1033 u8 duplex_reg;
1034 u8 jumbo_pm_reg;
1035 u8 jumbo_size_reg;
1036 const struct switch_dev_ops *sw_ops;
1037 };
1038
1039 #define B53_VTA_REGS \
1040 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1041 #define B53_VTA_REGS_9798 \
1042 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1043 #define B53_VTA_REGS_63XX \
1044 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1045
1046 static const struct b53_chip_data b53_switch_chips[] = {
1047 {
1048 .chip_id = BCM5325_DEVICE_ID,
1049 .dev_name = "BCM5325",
1050 .alias = "bcm5325",
1051 .vlans = 16,
1052 .enabled_ports = 0x1f,
1053 .cpu_port = B53_CPU_PORT_25,
1054 .duplex_reg = B53_DUPLEX_STAT_FE,
1055 .sw_ops = &b53_switch_ops_25,
1056 },
1057 {
1058 .chip_id = BCM5365_DEVICE_ID,
1059 .dev_name = "BCM5365",
1060 .alias = "bcm5365",
1061 .vlans = 256,
1062 .enabled_ports = 0x1f,
1063 .cpu_port = B53_CPU_PORT_25,
1064 .duplex_reg = B53_DUPLEX_STAT_FE,
1065 .sw_ops = &b53_switch_ops_65,
1066 },
1067 {
1068 .chip_id = BCM5395_DEVICE_ID,
1069 .dev_name = "BCM5395",
1070 .alias = "bcm5395",
1071 .vlans = 4096,
1072 .enabled_ports = 0x1f,
1073 .cpu_port = B53_CPU_PORT,
1074 .vta_regs = B53_VTA_REGS,
1075 .duplex_reg = B53_DUPLEX_STAT_GE,
1076 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1077 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1078 .sw_ops = &b53_switch_ops,
1079 },
1080 {
1081 .chip_id = BCM5397_DEVICE_ID,
1082 .dev_name = "BCM5397",
1083 .alias = "bcm5397",
1084 .vlans = 4096,
1085 .enabled_ports = 0x1f,
1086 .cpu_port = B53_CPU_PORT,
1087 .vta_regs = B53_VTA_REGS_9798,
1088 .duplex_reg = B53_DUPLEX_STAT_GE,
1089 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1090 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1091 .sw_ops = &b53_switch_ops,
1092 },
1093 {
1094 .chip_id = BCM5398_DEVICE_ID,
1095 .dev_name = "BCM5398",
1096 .alias = "bcm5398",
1097 .vlans = 4096,
1098 .enabled_ports = 0x7f,
1099 .cpu_port = B53_CPU_PORT,
1100 .vta_regs = B53_VTA_REGS_9798,
1101 .duplex_reg = B53_DUPLEX_STAT_GE,
1102 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1103 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1104 .sw_ops = &b53_switch_ops,
1105 },
1106 {
1107 .chip_id = BCM53115_DEVICE_ID,
1108 .dev_name = "BCM53115",
1109 .alias = "bcm53115",
1110 .vlans = 4096,
1111 .enabled_ports = 0x1f,
1112 .vta_regs = B53_VTA_REGS,
1113 .cpu_port = B53_CPU_PORT,
1114 .duplex_reg = B53_DUPLEX_STAT_GE,
1115 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1116 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1117 .sw_ops = &b53_switch_ops,
1118 },
1119 {
1120 .chip_id = BCM53125_DEVICE_ID,
1121 .dev_name = "BCM53125",
1122 .alias = "bcm53125",
1123 .vlans = 4096,
1124 .enabled_ports = 0x1f,
1125 .cpu_port = B53_CPU_PORT,
1126 .vta_regs = B53_VTA_REGS,
1127 .duplex_reg = B53_DUPLEX_STAT_GE,
1128 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1129 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1130 .sw_ops = &b53_switch_ops,
1131 },
1132 {
1133 .chip_id = BCM53128_DEVICE_ID,
1134 .dev_name = "BCM53128",
1135 .alias = "bcm53128",
1136 .vlans = 4096,
1137 .enabled_ports = 0x1ff,
1138 .cpu_port = B53_CPU_PORT,
1139 .vta_regs = B53_VTA_REGS,
1140 .duplex_reg = B53_DUPLEX_STAT_GE,
1141 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1142 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1143 .sw_ops = &b53_switch_ops,
1144 },
1145 {
1146 .chip_id = BCM63XX_DEVICE_ID,
1147 .dev_name = "BCM63xx",
1148 .alias = "bcm63xx",
1149 .vlans = 4096,
1150 .enabled_ports = 0, /* pdata must provide them */
1151 .cpu_port = B53_CPU_PORT,
1152 .vta_regs = B53_VTA_REGS_63XX,
1153 .duplex_reg = B53_DUPLEX_STAT_63XX,
1154 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1155 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1156 .sw_ops = &b53_switch_ops,
1157 },
1158 {
1159 .chip_id = BCM53010_DEVICE_ID,
1160 .dev_name = "BCM53010",
1161 .alias = "bcm53011",
1162 .vlans = 4096,
1163 .enabled_ports = 0x1f,
1164 .cpu_port = B53_CPU_PORT_25, // TODO: auto detect
1165 .vta_regs = B53_VTA_REGS,
1166 .duplex_reg = B53_DUPLEX_STAT_GE,
1167 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1168 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1169 .sw_ops = &b53_switch_ops,
1170 },
1171 {
1172 .chip_id = BCM53011_DEVICE_ID,
1173 .dev_name = "BCM53011",
1174 .alias = "bcm53011",
1175 .vlans = 4096,
1176 .enabled_ports = 0x1f,
1177 .cpu_port = B53_CPU_PORT_25, // TODO: auto detect
1178 .vta_regs = B53_VTA_REGS,
1179 .duplex_reg = B53_DUPLEX_STAT_GE,
1180 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1181 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1182 .sw_ops = &b53_switch_ops,
1183 },
1184 {
1185 .chip_id = BCM53012_DEVICE_ID,
1186 .dev_name = "BCM53012",
1187 .alias = "bcm53011",
1188 .vlans = 4096,
1189 .enabled_ports = 0x1f,
1190 .cpu_port = B53_CPU_PORT_25, // TODO: auto detect
1191 .vta_regs = B53_VTA_REGS,
1192 .duplex_reg = B53_DUPLEX_STAT_GE,
1193 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1194 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1195 .sw_ops = &b53_switch_ops,
1196 },
1197 {
1198 .chip_id = BCM53018_DEVICE_ID,
1199 .dev_name = "BCM53018",
1200 .alias = "bcm53018",
1201 .vlans = 4096,
1202 .enabled_ports = 0x1f,
1203 .cpu_port = B53_CPU_PORT_25, // TODO: auto detect
1204 .vta_regs = B53_VTA_REGS,
1205 .duplex_reg = B53_DUPLEX_STAT_GE,
1206 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1207 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1208 .sw_ops = &b53_switch_ops,
1209 },
1210 {
1211 .chip_id = BCM53019_DEVICE_ID,
1212 .dev_name = "BCM53019",
1213 .alias = "bcm53019",
1214 .vlans = 4096,
1215 .enabled_ports = 0x1f,
1216 .cpu_port = B53_CPU_PORT_25, // TODO: auto detect
1217 .vta_regs = B53_VTA_REGS,
1218 .duplex_reg = B53_DUPLEX_STAT_GE,
1219 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1220 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1221 .sw_ops = &b53_switch_ops,
1222 },
1223 };
1224
1225 static int b53_switch_init(struct b53_device *dev)
1226 {
1227 struct switch_dev *sw_dev = &dev->sw_dev;
1228 unsigned i;
1229 int ret;
1230
1231 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1232 const struct b53_chip_data *chip = &b53_switch_chips[i];
1233
1234 if (chip->chip_id == dev->chip_id) {
1235 sw_dev->name = chip->dev_name;
1236 if (!sw_dev->alias)
1237 sw_dev->alias = chip->alias;
1238 if (!dev->enabled_ports)
1239 dev->enabled_ports = chip->enabled_ports;
1240 dev->duplex_reg = chip->duplex_reg;
1241 dev->vta_regs[0] = chip->vta_regs[0];
1242 dev->vta_regs[1] = chip->vta_regs[1];
1243 dev->vta_regs[2] = chip->vta_regs[2];
1244 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1245 sw_dev->ops = chip->sw_ops;
1246 sw_dev->cpu_port = chip->cpu_port;
1247 sw_dev->vlans = chip->vlans;
1248 break;
1249 }
1250 }
1251
1252 if (!sw_dev->name)
1253 return -EINVAL;
1254
1255 /* check which BCM5325x version we have */
1256 if (is5325(dev)) {
1257 u8 vc4;
1258
1259 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1260
1261 /* check reserved bits */
1262 switch (vc4 & 3) {
1263 case 1:
1264 /* BCM5325E */
1265 break;
1266 case 3:
1267 /* BCM5325F - do not use port 4 */
1268 dev->enabled_ports &= ~BIT(4);
1269 break;
1270 default:
1271 /* On the BCM47XX SoCs this is the supported internal switch.*/
1272 #ifndef CONFIG_BCM47XX
1273 /* BCM5325M */
1274 return -EINVAL;
1275 #else
1276 break;
1277 #endif
1278 }
1279 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1280 u64 strap_value;
1281
1282 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1283 /* use second IMP port if GMII is enabled */
1284 if (strap_value & SV_GMII_CTRL_115)
1285 sw_dev->cpu_port = 5;
1286 }
1287
1288 /* cpu port is always last */
1289 sw_dev->ports = sw_dev->cpu_port + 1;
1290 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1291
1292 dev->ports = devm_kzalloc(dev->dev,
1293 sizeof(struct b53_port) * sw_dev->ports,
1294 GFP_KERNEL);
1295 if (!dev->ports)
1296 return -ENOMEM;
1297
1298 dev->vlans = devm_kzalloc(dev->dev,
1299 sizeof(struct b53_vlan) * sw_dev->vlans,
1300 GFP_KERNEL);
1301 if (!dev->vlans)
1302 return -ENOMEM;
1303
1304 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1305 if (!dev->buf)
1306 return -ENOMEM;
1307
1308 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1309 if (dev->reset_gpio >= 0) {
1310 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, GPIOF_OUT_INIT_HIGH, "robo_reset");
1311 if (ret)
1312 return ret;
1313 }
1314
1315 return b53_switch_reset(dev);
1316 }
1317
1318 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1319 void *priv)
1320 {
1321 struct b53_device *dev;
1322
1323 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1324 if (!dev)
1325 return NULL;
1326
1327 dev->dev = base;
1328 dev->ops = ops;
1329 dev->priv = priv;
1330 mutex_init(&dev->reg_mutex);
1331
1332 return dev;
1333 }
1334 EXPORT_SYMBOL(b53_switch_alloc);
1335
1336 int b53_switch_detect(struct b53_device *dev)
1337 {
1338 u32 id32;
1339 u16 tmp;
1340 u8 id8;
1341 int ret;
1342
1343 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1344 if (ret)
1345 return ret;
1346
1347 switch (id8) {
1348 case 0:
1349 /*
1350 * BCM5325 and BCM5365 do not have this register so reads
1351 * return 0. But the read operation did succeed, so assume
1352 * this is one of them.
1353 *
1354 * Next check if we can write to the 5325's VTA register; for
1355 * 5365 it is read only.
1356 */
1357
1358 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1359 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1360
1361 if (tmp == 0xf)
1362 dev->chip_id = BCM5325_DEVICE_ID;
1363 else
1364 dev->chip_id = BCM5365_DEVICE_ID;
1365 break;
1366 case BCM5395_DEVICE_ID:
1367 case BCM5397_DEVICE_ID:
1368 case BCM5398_DEVICE_ID:
1369 dev->chip_id = id8;
1370 break;
1371 default:
1372 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1373 if (ret)
1374 return ret;
1375
1376 switch (id32) {
1377 case BCM53115_DEVICE_ID:
1378 case BCM53125_DEVICE_ID:
1379 case BCM53128_DEVICE_ID:
1380 case BCM53010_DEVICE_ID:
1381 case BCM53011_DEVICE_ID:
1382 case BCM53012_DEVICE_ID:
1383 case BCM53018_DEVICE_ID:
1384 case BCM53019_DEVICE_ID:
1385 dev->chip_id = id32;
1386 break;
1387 default:
1388 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1389 id8, id32);
1390 return -ENODEV;
1391 }
1392 }
1393
1394 if (dev->chip_id == BCM5325_DEVICE_ID)
1395 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1396 &dev->core_rev);
1397 else
1398 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1399 &dev->core_rev);
1400 }
1401 EXPORT_SYMBOL(b53_switch_detect);
1402
1403 int b53_switch_register(struct b53_device *dev)
1404 {
1405 int ret;
1406
1407 if (dev->pdata) {
1408 dev->chip_id = dev->pdata->chip_id;
1409 dev->enabled_ports = dev->pdata->enabled_ports;
1410 dev->sw_dev.alias = dev->pdata->alias;
1411 }
1412
1413 if (!dev->chip_id && b53_switch_detect(dev))
1414 return -EINVAL;
1415
1416 ret = b53_switch_init(dev);
1417 if (ret)
1418 return ret;
1419
1420 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1421
1422 return register_switch(&dev->sw_dev, NULL);
1423 }
1424 EXPORT_SYMBOL(b53_switch_register);
1425
1426 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1427 MODULE_DESCRIPTION("B53 switch library");
1428 MODULE_LICENSE("Dual BSD/GPL");
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