target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c

   1 /*
   2  * B53 register access through MII registers
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/phy.h>
  21 #include <linux/module.h>
  22
  23 #include "b53_priv.h"
  24
  25 #define B53_PSEUDO_PHY  0x1e /* Register Access Pseudo PHY */
  26
  27 /* MII registers */
  28 #define REG_MII_PAGE    0x10    /* MII Page register */
  29 #define REG_MII_ADDR    0x11    /* MII Address register */
  30 #define REG_MII_DATA0   0x18    /* MII Data register 0 */
  31 #define REG_MII_DATA1   0x19    /* MII Data register 1 */
  32 #define REG_MII_DATA2   0x1a    /* MII Data register 2 */
  33 #define REG_MII_DATA3   0x1b    /* MII Data register 3 */
  34
  35 #define REG_MII_PAGE_ENABLE     BIT(0)
  36 #define REG_MII_ADDR_WRITE      BIT(0)
  37 #define REG_MII_ADDR_READ       BIT(1)
  38
  39 static int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op)
  40 {
  41         int i;
  42         u16 v;
  43         int ret;
  44         struct mii_bus *bus = dev->priv;
  45
  46         if (dev->current_page != page) {
  47                 /* set page number */
  48                 v = (page << 8) | REG_MII_PAGE_ENABLE;
  49                 ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_PAGE, v);
  50                 if (ret)
  51                         return ret;
  52                 dev->current_page = page;
  53         }
  54
  55         /* set register address */
  56         v = (reg << 8) | op;
  57         ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_ADDR, v);
  58         if (ret)
  59                 return ret;
  60
  61         /* check if operation completed */
  62         for (i = 0; i < 5; ++i) {
  63                 v = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_ADDR);
  64                 if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
  65                         break;
  66                 usleep_range(10, 100);
  67         }
  68
  69         if (WARN_ON(i == 5))
  70                 return -EIO;
  71
  72         return 0;
  73 }
  74
  75 static int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)
  76 {
  77         struct mii_bus *bus = dev->priv;
  78         int ret;
  79
  80         ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
  81         if (ret)
  82                 return ret;
  83
  84         *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0) & 0xff;
  85
  86         return 0;
  87 }
  88
  89 static int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)
  90 {
  91         struct mii_bus *bus = dev->priv;
  92         int ret;
  93
  94         ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
  95         if (ret)
  96                 return ret;
  97
  98         *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0);
  99
 100         return 0;
 101 }
 102
 103 static int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)
 104 {
 105         struct mii_bus *bus = dev->priv;
 106         int ret;
 107
 108         ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
 109         if (ret)
 110                 return ret;
 111
 112         *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0);
 113         *val |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA1) << 16;
 114
 115         return 0;
 116 }
 117
 118 static int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)
 119 {
 120         struct mii_bus *bus = dev->priv;
 121         u64 temp = 0;
 122         int i;
 123         int ret;
 124
 125         ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
 126         if (ret)
 127                 return ret;
 128
 129         for (i = 2; i >= 0; i--) {
 130                 temp <<= 16;
 131                 temp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i);
 132         }
 133
 134         *val = temp;
 135
 136         return 0;
 137 }
 138
 139 static int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)
 140 {
 141         struct mii_bus *bus = dev->priv;
 142         u64 temp = 0;
 143         int i;
 144         int ret;
 145
 146         ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
 147         if (ret)
 148                 return ret;
 149
 150         for (i = 3; i >= 0; i--) {
 151                 temp <<= 16;
 152                 temp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i);
 153         }
 154
 155         *val = temp;
 156
 157         return 0;
 158 }
 159
 160 static int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)
 161 {
 162         struct mii_bus *bus = dev->priv;
 163         int ret;
 164
 165         ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value);
 166         if (ret)
 167                 return ret;
 168
 169         return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
 170 }
 171
 172 static int b53_mdio_write16(struct b53_device *dev, u8 page, u8 reg,
 173                              u16 value)
 174 {
 175         struct mii_bus *bus = dev->priv;
 176         int ret;
 177
 178         ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value);
 179         if (ret)
 180                 return ret;
 181
 182         return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
 183 }
 184
 185 static int b53_mdio_write32(struct b53_device *dev, u8 page, u8 reg,
 186                                     u32 value)
 187 {
 188         struct mii_bus *bus = dev->priv;
 189         unsigned int i;
 190         u32 temp = value;
 191
 192         for (i = 0; i < 2; i++) {
 193                 int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,
 194                                     temp & 0xffff);
 195                 if (ret)
 196                         return ret;
 197                 temp >>= 16;
 198         }
 199
 200         return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
 201
 202 }
 203
 204 static int b53_mdio_write48(struct b53_device *dev, u8 page, u8 reg,
 205                                     u64 value)
 206 {
 207         struct mii_bus *bus = dev->priv;
 208         unsigned i;
 209         u64 temp = value;
 210
 211         for (i = 0; i < 3; i++) {
 212                 int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,
 213                                     temp & 0xffff);
 214                 if (ret)
 215                         return ret;
 216                 temp >>= 16;
 217         }
 218
 219         return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
 220
 221 }
 222
 223 static int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg,
 224                              u64 value)
 225 {
 226         struct mii_bus *bus = dev->priv;
 227         unsigned i;
 228         u64 temp = value;
 229
 230         for (i = 0; i < 4; i++) {
 231                 int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,
 232                                     temp & 0xffff);
 233                 if (ret)
 234                         return ret;
 235                 temp >>= 16;
 236         }
 237
 238         return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
 239 }
 240
 241 static struct b53_io_ops b53_mdio_ops = {
 242         .read8 = b53_mdio_read8,
 243         .read16 = b53_mdio_read16,
 244         .read32 = b53_mdio_read32,
 245         .read48 = b53_mdio_read48,
 246         .read64 = b53_mdio_read64,
 247         .write8 = b53_mdio_write8,
 248         .write16 = b53_mdio_write16,
 249         .write32 = b53_mdio_write32,
 250         .write48 = b53_mdio_write48,
 251         .write64 = b53_mdio_write64,
 252 };
 253
 254 static int b53_phy_probe(struct phy_device *phydev)
 255 {
 256         struct b53_device dev;
 257         int ret;
 258
 259         /* allow the generic phy driver to take over */
 260         if (phydev->addr != B53_PSEUDO_PHY && phydev->addr != 0)
 261                 return -ENODEV;
 262
 263         dev.current_page = 0xff;
 264         dev.priv = phydev->bus;
 265         dev.ops = &b53_mdio_ops;
 266         dev.pdata = NULL;
 267         mutex_init(&dev.reg_mutex);
 268
 269         ret = b53_switch_detect(&dev);
 270         if (!ret)
 271                 return ret;
 272
 273         if (is5325(&dev) || is5365(&dev))
 274                 phydev->supported = SUPPORTED_100baseT_Full;
 275         else
 276                 phydev->supported = SUPPORTED_1000baseT_Full;
 277
 278         phydev->advertising = phydev->supported;
 279
 280         return 0;
 281 }
 282
 283 static int b53_phy_config_init(struct phy_device *phydev)
 284 {
 285         struct b53_device *dev;
 286         int ret;
 287
 288         dev = b53_switch_alloc(&phydev->dev, &b53_mdio_ops, phydev->bus);
 289         if (!dev)
 290                 return -ENOMEM;
 291
 292         /* we don't use page 0xff, so force a page set */
 293         dev->current_page = 0xff;
 294         /* force the ethX as alias */
 295         dev->sw_dev.alias = phydev->attached_dev->name;
 296
 297         ret = b53_switch_register(dev);
 298         if (ret) {
 299                 pr_info("failed to register switch: %i\n", ret);
 300                 return ret;
 301         }
 302
 303         phydev->priv = dev;
 304
 305         return 0;
 306 }
 307
 308 static void b53_phy_remove(struct phy_device *phydev)
 309 {
 310         struct b53_device *priv = phydev->priv;
 311
 312         if (!priv)
 313                 return;
 314
 315         b53_switch_remove(priv);
 316
 317         phydev->priv = NULL;
 318 }
 319
 320 static int b53_phy_config_aneg(struct phy_device *phydev)
 321 {
 322         return 0;
 323 }
 324
 325 static int b53_phy_read_status(struct phy_device *phydev)
 326 {
 327         struct b53_device *priv = phydev->priv;
 328
 329         if (is5325(priv) || is5365(priv))
 330                 phydev->speed = 100;
 331         else
 332                 phydev->speed = 1000;
 333
 334         phydev->duplex = DUPLEX_FULL;
 335         phydev->link = 1;
 336         phydev->state = PHY_RUNNING;
 337
 338         netif_carrier_on(phydev->attached_dev);
 339         phydev->adjust_link(phydev->attached_dev);
 340
 341         return 0;
 342 }
 343
 344 /* BCM5325, BCM539x */
 345 static struct phy_driver b53_phy_driver_id1 = {
 346         .phy_id         = 0x0143bc00,
 347         .name           = "Broadcom B53 (1)",
 348         .phy_id_mask    = 0x1ffffc00,
 349         .features       = 0,
 350         .probe          = b53_phy_probe,
 351         .remove         = b53_phy_remove,
 352         .config_aneg    = b53_phy_config_aneg,
 353         .config_init    = b53_phy_config_init,
 354         .read_status    = b53_phy_read_status,
 355         .driver = {
 356                 .owner = THIS_MODULE,
 357         },
 358 };
 359
 360 /* BCM53125 */
 361 static struct phy_driver b53_phy_driver_id2 = {
 362         .phy_id         = 0x03625c00,
 363         .name           = "Broadcom B53 (2)",
 364         .phy_id_mask    = 0x1ffffc00,
 365         .features       = 0,
 366         .probe          = b53_phy_probe,
 367         .remove         = b53_phy_remove,
 368         .config_aneg    = b53_phy_config_aneg,
 369         .config_init    = b53_phy_config_init,
 370         .read_status    = b53_phy_read_status,
 371         .driver = {
 372                 .owner = THIS_MODULE,
 373         },
 374 };
 375
 376 int __init b53_phy_driver_register(void)
 377 {
 378         int ret;
 379
 380         ret = phy_driver_register(&b53_phy_driver_id1);
 381         if (ret)
 382                 return ret;
 383
 384         ret = phy_driver_register(&b53_phy_driver_id2);
 385         if (ret)
 386                 phy_driver_unregister(&b53_phy_driver_id1);
 387
 388         return ret;
 389 }
 390
 391 void __exit b53_phy_driver_unregister(void)
 392 {
 393         phy_driver_unregister(&b53_phy_driver_id2);
 394         phy_driver_unregister(&b53_phy_driver_id1);
 395 }
 396
 397 module_init(b53_phy_driver_register);
 398 module_exit(b53_phy_driver_unregister);
 399
 400 MODULE_DESCRIPTION("B53 MDIO access driver");
 401 MODULE_LICENSE("Dual BSD/GPL");