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kernel: fix some mistakes in ssb patch refresh in r22766, r22767 and r22768.
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.33 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
4 {
5 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
6 }
7 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
8
9 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
10 {
11 --- a/drivers/ssb/driver_chipcommon_pmu.c
12 +++ b/drivers/ssb/driver_chipcommon_pmu.c
13 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
14 case 0x5354:
15 ssb_pmu0_pllinit_r0(cc, crystalfreq);
16 break;
17 + case 0x4322:
18 + if (cc->pmu.rev == 2) {
19 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
20 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
21 + }
22 + break;
23 default:
24 ssb_printk(KERN_ERR PFX
25 "ERROR: PLL init unknown for device %04X\n",
26 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
27
28 switch (bus->chip_id) {
29 case 0x4312:
30 + case 0x4322:
31 /* We keep the default settings:
32 * min_msk = 0xCBB
33 * max_msk = 0x7FFFF
34 --- a/drivers/ssb/driver_mipscore.c
35 +++ b/drivers/ssb/driver_mipscore.c
36 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
37 set_irq(dev, irq++);
38 }
39 break;
40 - /* fallthrough */
41 case SSB_DEV_PCI:
42 case SSB_DEV_ETHERNET:
43 case SSB_DEV_ETHERNET_GBIT:
44 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
45 set_irq(dev, irq++);
46 break;
47 }
48 + /* fallthrough */
49 + case SSB_DEV_EXTIF:
50 + set_irq(dev, 0);
51 + break;
52 }
53 }
54 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
55 --- a/drivers/ssb/driver_pcicore.c
56 +++ b/drivers/ssb/driver_pcicore.c
57 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
58 .pci_ops = &ssb_pcicore_pciops,
59 .io_resource = &ssb_pcicore_io_resource,
60 .mem_resource = &ssb_pcicore_mem_resource,
61 - .mem_offset = 0x24000000,
62 };
63
64 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
65 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
66 -
67 /* This function is called when doing a pci_enable_device().
68 * We must first check if the device is a device on the PCI-core bridge. */
69 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
70 {
71 - struct resource *res;
72 - int pos, size;
73 - u32 *base;
74 -
75 if (d->bus->ops != &ssb_pcicore_pciops) {
76 /* This is not a device on the PCI-core bridge. */
77 return -ENODEV;
78 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
79 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
80 pci_name(d));
81
82 - /* Fix up resource bases */
83 - for (pos = 0; pos < 6; pos++) {
84 - res = &d->resource[pos];
85 - if (res->flags & IORESOURCE_IO)
86 - base = &ssb_pcicore_pcibus_iobase;
87 - else
88 - base = &ssb_pcicore_pcibus_membase;
89 - res->flags |= IORESOURCE_PCI_FIXED;
90 - if (res->end) {
91 - size = res->end - res->start + 1;
92 - if (*base & (size - 1))
93 - *base = (*base + size) & ~(size - 1);
94 - res->start = *base;
95 - res->end = res->start + size - 1;
96 - *base += size;
97 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
98 - }
99 - /* Fix up PCI bridge BAR0 only */
100 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
101 - break;
102 - }
103 /* Fix up interrupt lines */
104 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
105 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
106 --- a/drivers/ssb/main.c
107 +++ b/drivers/ssb/main.c
108 @@ -833,6 +833,9 @@ int ssb_bus_pcibus_register(struct ssb_b
109 if (!err) {
110 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
111 "PCI device %s\n", dev_name(&host_pci->dev));
112 + } else {
113 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
114 + " of SSB with error %d\n", err);
115 }
116
117 return err;
118 --- a/drivers/ssb/ssb_private.h
119 +++ b/drivers/ssb/ssb_private.h
120 @@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f
121 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
122 extern int __init b43_pci_ssb_bridge_init(void);
123 extern void __exit b43_pci_ssb_bridge_exit(void);
124 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
125 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
126 static inline int b43_pci_ssb_bridge_init(void)
127 {
128 return 0;
129 @@ -204,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
130 static inline void b43_pci_ssb_bridge_exit(void)
131 {
132 }
133 -#endif /* CONFIG_SSB_PCIHOST */
134 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
135
136 #endif /* LINUX_SSB_PRIVATE_H_ */
137 --- a/include/linux/ssb/ssb_driver_chipcommon.h
138 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
139 @@ -54,6 +54,7 @@
140 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
141 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
142 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
143 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
144 #define SSB_CHIPCO_CORECTL 0x0008
145 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
146 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
147 @@ -386,6 +387,7 @@
148
149
150 /** Chip specific Chip-Status register contents. */
151 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
152 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
153 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
154 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
155 @@ -399,6 +401,18 @@
156 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
157 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
158
159 +/** Macros to determine SPROM presence based on Chip-Status register. */
160 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
161 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
162 + SSB_CHIPCO_CHST_4325_OTP_SEL)
163 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
164 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
165 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
166 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
167 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
168 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
169 + SSB_CHIPCO_CHST_4325_OTP_SEL))
170 +
171
172
173 /** Clockcontrol masks and values **/
174 --- a/include/linux/ssb/ssb_regs.h
175 +++ b/include/linux/ssb/ssb_regs.h
176 @@ -178,19 +178,19 @@
177 #define SSB_SPROM_REVISION_CRC_SHIFT 8
178
179 /* SPROM Revision 1 */
180 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
181 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
182 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
183 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
184 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
185 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
186 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
187 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
188 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
189 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
190 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
191 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
192 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
193 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
194 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
195 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
196 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
197 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
198 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
199 -#define SSB_SPROM1_BINF 0x105C /* Board info */
200 +#define SSB_SPROM1_BINF 0x005C /* Board info */
201 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
202 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
203 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
204 @@ -198,63 +198,63 @@
205 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
206 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
207 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
208 -#define SSB_SPROM1_PA0B0 0x105E
209 -#define SSB_SPROM1_PA0B1 0x1060
210 -#define SSB_SPROM1_PA0B2 0x1062
211 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
212 +#define SSB_SPROM1_PA0B0 0x005E
213 +#define SSB_SPROM1_PA0B1 0x0060
214 +#define SSB_SPROM1_PA0B2 0x0062
215 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
216 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
217 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
218 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
219 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
220 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
221 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
222 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
223 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
224 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
225 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
226 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
227 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
228 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
229 -#define SSB_SPROM1_PA1B0 0x106A
230 -#define SSB_SPROM1_PA1B1 0x106C
231 -#define SSB_SPROM1_PA1B2 0x106E
232 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
233 +#define SSB_SPROM1_PA1B0 0x006A
234 +#define SSB_SPROM1_PA1B1 0x006C
235 +#define SSB_SPROM1_PA1B2 0x006E
236 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
237 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
238 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
239 #define SSB_SPROM1_ITSSI_A_SHIFT 8
240 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
241 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
242 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
243 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
244 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
245 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
246 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
247 #define SSB_SPROM1_AGAIN_A_SHIFT 8
248
249 /* SPROM Revision 2 (inherits from rev 1) */
250 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
251 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
252 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
253 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
254 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
255 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
256 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
257 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
258 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
259 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
260 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
261 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
262 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
263 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
264 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
265 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
266 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
267 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
268 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
269 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
270 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
271 #define SSB_SPROM2_OPO_VALUE 0x00FF
272 #define SSB_SPROM2_OPO_UNUSED 0xFF00
273 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
274 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
275
276 /* SPROM Revision 3 (inherits most data from rev 2) */
277 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
278 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
279 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
280 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
281 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
282 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
283 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
284 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
285 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
286 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
287 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
288 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
289 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
290 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
291 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
292 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
293 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
294 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
295 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
296 @@ -265,100 +265,100 @@
297 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
298
299 /* SPROM Revision 4 */
300 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
301 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
302 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
303 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
304 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
305 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
306 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
307 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
308 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
309 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
310 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
311 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
312 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
313 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
314 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
315 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
316 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
317 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
318 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
319 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
320 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
321 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
322 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
323 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
324 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
325 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
326 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
327 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
328 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
329 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
330 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
331 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
332 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
333 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
334 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
335 #define SSB_SPROM4_AGAIN0_SHIFT 0
336 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
337 #define SSB_SPROM4_AGAIN1_SHIFT 8
338 -#define SSB_SPROM4_AGAIN23 0x1060
339 +#define SSB_SPROM4_AGAIN23 0x0060
340 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
341 #define SSB_SPROM4_AGAIN2_SHIFT 0
342 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
343 #define SSB_SPROM4_AGAIN3_SHIFT 8
344 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
345 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
346 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
347 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
348 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
349 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
350 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
351 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
352 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
353 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
354 #define SSB_SPROM4_ITSSI_A_SHIFT 8
355 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
356 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
357 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
358 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
359 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
360 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
361 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
362 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
363 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
364 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
365 -#define SSB_SPROM4_PA0B2 0x1086
366 -#define SSB_SPROM4_PA1B0 0x108E
367 -#define SSB_SPROM4_PA1B1 0x1090
368 -#define SSB_SPROM4_PA1B2 0x1092
369 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
370 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
371 +#define SSB_SPROM4_PA0B2 0x0086
372 +#define SSB_SPROM4_PA1B0 0x008E
373 +#define SSB_SPROM4_PA1B1 0x0090
374 +#define SSB_SPROM4_PA1B2 0x0092
375
376 /* SPROM Revision 5 (inherits most data from rev 4) */
377 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
378 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
379 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
380 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
381 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
382 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
383 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
384 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
385 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
386 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
387 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
388 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
389 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
390 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
391 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
392 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
393 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
394 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
395
396 /* SPROM Revision 8 */
397 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
398 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
399 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
400 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
401 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
402 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
403 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
404 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
405 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
406 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
407 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
408 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
409 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
410 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
411 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
412 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
413 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
414 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
415 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
416 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
417 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
418 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
419 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
420 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
421 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
422 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
423 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
424 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
425 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
426 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
427 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
428 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
429 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
430 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
431 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
432 #define SSB_SPROM8_AGAIN0_SHIFT 0
433 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
434 #define SSB_SPROM8_AGAIN1_SHIFT 8
435 -#define SSB_SPROM8_AGAIN23 0x10A0
436 +#define SSB_SPROM8_AGAIN23 0x00A0
437 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
438 #define SSB_SPROM8_AGAIN2_SHIFT 0
439 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
440 #define SSB_SPROM8_AGAIN3_SHIFT 8
441 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
442 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
443 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
444 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
445 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
446 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
447 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
448 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
449 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
450 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
451 #define SSB_SPROM8_RSSISMF2G 0x000F
452 #define SSB_SPROM8_RSSISMC2G 0x00F0
453 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
454 @@ -366,7 +366,7 @@
455 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
456 #define SSB_SPROM8_BXA2G 0x1800
457 #define SSB_SPROM8_BXA2G_SHIFT 11
458 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
459 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
460 #define SSB_SPROM8_RSSISMF5G 0x000F
461 #define SSB_SPROM8_RSSISMC5G 0x00F0
462 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
463 @@ -374,47 +374,47 @@
464 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
465 #define SSB_SPROM8_BXA5G 0x1800
466 #define SSB_SPROM8_BXA5G_SHIFT 11
467 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
468 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
469 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
470 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
471 #define SSB_SPROM8_TRI5G_SHIFT 8
472 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
473 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
474 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
475 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
476 #define SSB_SPROM8_TRI5GH_SHIFT 8
477 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
478 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
479 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
480 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
481 #define SSB_SPROM8_RXPO5G_SHIFT 8
482 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
483 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
484 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
485 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
486 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
487 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
488 -#define SSB_SPROM8_PA0B1 0x10C4
489 -#define SSB_SPROM8_PA0B2 0x10C6
490 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
491 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
492 +#define SSB_SPROM8_PA0B1 0x00C4
493 +#define SSB_SPROM8_PA0B2 0x00C6
494 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
495 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
496 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
497 #define SSB_SPROM8_ITSSI_A_SHIFT 8
498 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
499 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
500 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
501 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
502 #define SSB_SPROM8_MAXP_AL_SHIFT 8
503 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
504 -#define SSB_SPROM8_PA1B1 0x10CE
505 -#define SSB_SPROM8_PA1B2 0x10D0
506 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
507 -#define SSB_SPROM8_PA1LOB1 0x10D4
508 -#define SSB_SPROM8_PA1LOB2 0x10D6
509 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
510 -#define SSB_SPROM8_PA1HIB1 0x10DA
511 -#define SSB_SPROM8_PA1HIB2 0x10DC
512 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
513 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
514 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
515 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
516 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
517 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
518 +#define SSB_SPROM8_PA1B1 0x00CE
519 +#define SSB_SPROM8_PA1B2 0x00D0
520 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
521 +#define SSB_SPROM8_PA1LOB1 0x00D4
522 +#define SSB_SPROM8_PA1LOB2 0x00D6
523 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
524 +#define SSB_SPROM8_PA1HIB1 0x00DA
525 +#define SSB_SPROM8_PA1HIB2 0x00DC
526 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
527 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
528 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
529 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
530 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
531
532 /* Values for SSB_SPROM1_BINF_CCODE */
533 enum {
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