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404201a7827c416820a491245f1118bc53754e35
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.39 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -3,7 +3,7 @@
4 * Broadcom ChipCommon core driver
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
13 if (!ccdev)
14 return;
15 bus = ccdev->bus;
16 +
17 + /* We support SLOW only on 6..9 */
18 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
19 + mode = SSB_CLKMODE_DYNAMIC;
20 +
21 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
22 + return; /* PMU controls clockmode, separated function needed */
23 + SSB_WARN_ON(ccdev->id.revision >= 20);
24 +
25 /* chipcommon cores prior to rev6 don't support dynamic clock control */
26 if (ccdev->id.revision < 6)
27 return;
28 - /* chipcommon cores rev10 are a whole new ball game */
29 +
30 + /* ChipCommon cores rev10+ need testing */
31 if (ccdev->id.revision >= 10)
32 return;
33 +
34 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
35 return;
36
37 switch (mode) {
38 - case SSB_CLKMODE_SLOW:
39 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
40 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
41 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
42 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
43 break;
44 case SSB_CLKMODE_FAST:
45 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
46 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
47 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
48 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
49 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
50 + if (ccdev->id.revision < 10) {
51 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
52 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
53 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
54 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
55 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
56 + } else {
57 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
58 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
59 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
60 + /* udelay(150); TODO: not available in early init */
61 + }
62 break;
63 case SSB_CLKMODE_DYNAMIC:
64 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
65 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
66 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
67 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
68 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
69 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
70 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
71 -
72 - /* for dynamic control, we have to release our xtal_pu "force on" */
73 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
74 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
75 + if (ccdev->id.revision < 10) {
76 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
77 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
78 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
79 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
80 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
81 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
82 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
83 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
84 +
85 + /* For dynamic control, we have to release our xtal_pu
86 + * "force on" */
87 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
88 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
89 + } else {
90 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
91 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
92 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
93 + }
94 break;
95 default:
96 SSB_WARN_ON(1);
97 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
98 if (cc->dev->id.revision >= 11)
99 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
100 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
101 +
102 + if (cc->dev->id.revision >= 20) {
103 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
104 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
105 + }
106 +
107 ssb_pmu_init(cc);
108 chipco_powercontrol_init(cc);
109 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
110 --- a/drivers/ssb/driver_chipcommon_pmu.c
111 +++ b/drivers/ssb/driver_chipcommon_pmu.c
112 @@ -2,7 +2,7 @@
113 * Sonics Silicon Backplane
114 * Broadcom ChipCommon Power Management Unit driver
115 *
116 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
117 + * Copyright 2009, Michael Buesch <m@bues.ch>
118 * Copyright 2007, Broadcom Corporation
119 *
120 * Licensed under the GNU/GPL. See COPYING for details.
121 @@ -12,6 +12,9 @@
122 #include <linux/ssb/ssb_regs.h>
123 #include <linux/ssb/ssb_driver_chipcommon.h>
124 #include <linux/delay.h>
125 +#ifdef CONFIG_BCM47XX
126 +#include <asm/mach-bcm47xx/nvram.h>
127 +#endif
128
129 #include "ssb_private.h"
130
131 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
132 u32 pmuctl, tmp, pllctl;
133 unsigned int i;
134
135 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
136 - /* The 5354 crystal freq is 25MHz */
137 - crystalfreq = 25000;
138 - }
139 if (crystalfreq)
140 e = pmu0_plltab_find_entry(crystalfreq);
141 if (!e)
142 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
143 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
144
145 if (bus->bustype == SSB_BUSTYPE_SSB) {
146 - /* TODO: The user may override the crystal frequency. */
147 +#ifdef CONFIG_BCM47XX
148 + char buf[20];
149 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
150 + crystalfreq = simple_strtoul(buf, NULL, 0);
151 +#endif
152 }
153
154 switch (bus->chip_id) {
155 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
156 ssb_pmu1_pllinit_r0(cc, crystalfreq);
157 break;
158 case 0x4328:
159 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
160 + break;
161 case 0x5354:
162 + if (crystalfreq == 0)
163 + crystalfreq = 25000;
164 ssb_pmu0_pllinit_r0(cc, crystalfreq);
165 break;
166 case 0x4322:
167 @@ -417,12 +424,14 @@ static void ssb_pmu_resources_init(struc
168 u32 min_msk = 0, max_msk = 0;
169 unsigned int i;
170 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
171 - unsigned int updown_tab_size;
172 + unsigned int updown_tab_size = 0;
173 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
174 - unsigned int depend_tab_size;
175 + unsigned int depend_tab_size = 0;
176
177 switch (bus->chip_id) {
178 case 0x4312:
179 + min_msk = 0xCBB;
180 + break;
181 case 0x4322:
182 /* We keep the default settings:
183 * min_msk = 0xCBB
184 @@ -604,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
185
186 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
187 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
188 +
189 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
190 +{
191 + struct ssb_bus *bus = cc->dev->bus;
192 +
193 + switch (bus->chip_id) {
194 + case 0x5354:
195 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
196 + return 240000000;
197 + default:
198 + ssb_printk(KERN_ERR PFX
199 + "ERROR: PMU cpu clock unknown for device %04X\n",
200 + bus->chip_id);
201 + return 0;
202 + }
203 +}
204 +
205 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
206 +{
207 + struct ssb_bus *bus = cc->dev->bus;
208 +
209 + switch (bus->chip_id) {
210 + case 0x5354:
211 + return 120000000;
212 + default:
213 + ssb_printk(KERN_ERR PFX
214 + "ERROR: PMU controlclock unknown for device %04X\n",
215 + bus->chip_id);
216 + return 0;
217 + }
218 +}
219 --- a/drivers/ssb/driver_gige.c
220 +++ b/drivers/ssb/driver_gige.c
221 @@ -3,7 +3,7 @@
222 * Broadcom Gigabit Ethernet core driver
223 *
224 * Copyright 2008, Broadcom Corporation
225 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
226 + * Copyright 2008, Michael Buesch <m@bues.ch>
227 *
228 * Licensed under the GNU/GPL. See COPYING for details.
229 */
230 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
231 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
232 }
233
234 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
235 - int reg, int size, u32 *val)
236 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
237 + unsigned int devfn, int reg,
238 + int size, u32 *val)
239 {
240 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
241 unsigned long flags;
242 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
243 return PCIBIOS_SUCCESSFUL;
244 }
245
246 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
247 - int reg, int size, u32 val)
248 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
249 + unsigned int devfn, int reg,
250 + int size, u32 val)
251 {
252 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
253 unsigned long flags;
254 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
255 return PCIBIOS_SUCCESSFUL;
256 }
257
258 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
259 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
260 + const struct ssb_device_id *id)
261 {
262 struct ssb_gige *dev;
263 u32 base, tmslow, tmshigh;
264 --- a/drivers/ssb/driver_pcicore.c
265 +++ b/drivers/ssb/driver_pcicore.c
266 @@ -3,7 +3,7 @@
267 * Broadcom PCI-core driver
268 *
269 * Copyright 2005, Broadcom Corporation
270 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
271 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
272 *
273 * Licensed under the GNU/GPL. See COPYING for details.
274 */
275 @@ -15,6 +15,11 @@
276
277 #include "ssb_private.h"
278
279 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
280 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
281 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
282 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
283 + u8 address, u16 data);
284
285 static inline
286 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
287 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
288 u32 tmp;
289
290 /* We do only have one cardbus device behind the bridge. */
291 - if (pc->cardbusmode && (dev >= 1))
292 + if (pc->cardbusmode && (dev > 1))
293 goto out;
294
295 if (bus == 0) {
296 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
297 return ssb_mips_irq(extpci_core->dev) + 2;
298 }
299
300 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
301 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
302 {
303 u32 val;
304
305 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
306 register_pci_controller(&ssb_pcicore_controller);
307 }
308
309 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
310 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
311 {
312 struct ssb_bus *bus = pc->dev->bus;
313 u16 chipid_top;
314 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
315 }
316 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
317
318 +/**************************************************
319 + * Workarounds.
320 + **************************************************/
321 +
322 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
323 +{
324 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
325 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
326 + tmp &= ~0xF000;
327 + tmp |= (pc->dev->core_index << 12);
328 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
329 + }
330 +}
331 +
332 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
333 +{
334 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
335 +}
336 +
337 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
338 +{
339 + const u8 serdes_pll_device = 0x1D;
340 + const u8 serdes_rx_device = 0x1F;
341 + u16 tmp;
342 +
343 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
344 + ssb_pcicore_polarity_workaround(pc));
345 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
346 + if (tmp & 0x4000)
347 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
348 +}
349 +
350 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
351 +{
352 + struct ssb_device *pdev = pc->dev;
353 + struct ssb_bus *bus = pdev->bus;
354 + u32 tmp;
355 +
356 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
357 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
358 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
359 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
360 +
361 + if (pdev->id.revision < 5) {
362 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
363 + tmp &= ~SSB_IMCFGLO_SERTO;
364 + tmp |= 2;
365 + tmp &= ~SSB_IMCFGLO_REQTO;
366 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
367 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
368 + ssb_commit_settings(bus);
369 + } else if (pdev->id.revision >= 11) {
370 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
371 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
372 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
373 + }
374 +}
375 +
376 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
377 +{
378 + u32 tmp;
379 + u8 rev = pc->dev->id.revision;
380 +
381 + if (rev == 0 || rev == 1) {
382 + /* TLP Workaround register. */
383 + tmp = ssb_pcie_read(pc, 0x4);
384 + tmp |= 0x8;
385 + ssb_pcie_write(pc, 0x4, tmp);
386 + }
387 + if (rev == 1) {
388 + /* DLLP Link Control register. */
389 + tmp = ssb_pcie_read(pc, 0x100);
390 + tmp |= 0x40;
391 + ssb_pcie_write(pc, 0x100, tmp);
392 + }
393 +
394 + if (rev == 0) {
395 + const u8 serdes_rx_device = 0x1F;
396 +
397 + ssb_pcie_mdio_write(pc, serdes_rx_device,
398 + 2 /* Timer */, 0x8128);
399 + ssb_pcie_mdio_write(pc, serdes_rx_device,
400 + 6 /* CDR */, 0x0100);
401 + ssb_pcie_mdio_write(pc, serdes_rx_device,
402 + 7 /* CDR BW */, 0x1466);
403 + } else if (rev == 3 || rev == 4 || rev == 5) {
404 + /* TODO: DLLP Power Management Threshold */
405 + ssb_pcicore_serdes_workaround(pc);
406 + /* TODO: ASPM */
407 + } else if (rev == 7) {
408 + /* TODO: No PLL down */
409 + }
410 +
411 + if (rev >= 6) {
412 + /* Miscellaneous Configuration Fixup */
413 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
414 + if (!(tmp & 0x8000))
415 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
416 + tmp | 0x8000);
417 + }
418 +}
419
420 /**************************************************
421 * Generic and Clientmode operation code.
422 **************************************************/
423
424 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
425 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
426 {
427 + struct ssb_device *pdev = pc->dev;
428 + struct ssb_bus *bus = pdev->bus;
429 +
430 + if (bus->bustype == SSB_BUSTYPE_PCI)
431 + ssb_pcicore_fix_sprom_core_index(pc);
432 +
433 /* Disable PCI interrupts. */
434 - ssb_write32(pc->dev, SSB_INTVEC, 0);
435 + ssb_write32(pdev, SSB_INTVEC, 0);
436 +
437 + /* Additional PCIe always once-executed workarounds */
438 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
439 + ssb_pcicore_serdes_workaround(pc);
440 + /* TODO: ASPM */
441 + /* TODO: Clock Request Update */
442 + }
443 }
444
445 -void ssb_pcicore_init(struct ssb_pcicore *pc)
446 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
447 {
448 struct ssb_device *dev = pc->dev;
449 - struct ssb_bus *bus;
450
451 if (!dev)
452 return;
453 - bus = dev->bus;
454 if (!ssb_device_is_enabled(dev))
455 ssb_device_enable(dev, 0);
456
457 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
458 pcicore_write32(pc, 0x134, data);
459 }
460
461 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
462 - u8 address, u16 data)
463 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
464 +{
465 + const u16 mdio_control = 0x128;
466 + const u16 mdio_data = 0x12C;
467 + u32 v;
468 + int i;
469 +
470 + v = (1 << 30); /* Start of Transaction */
471 + v |= (1 << 28); /* Write Transaction */
472 + v |= (1 << 17); /* Turnaround */
473 + v |= (0x1F << 18);
474 + v |= (phy << 4);
475 + pcicore_write32(pc, mdio_data, v);
476 +
477 + udelay(10);
478 + for (i = 0; i < 200; i++) {
479 + v = pcicore_read32(pc, mdio_control);
480 + if (v & 0x100 /* Trans complete */)
481 + break;
482 + msleep(1);
483 + }
484 +}
485 +
486 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
487 {
488 const u16 mdio_control = 0x128;
489 const u16 mdio_data = 0x12C;
490 + int max_retries = 10;
491 + u16 ret = 0;
492 u32 v;
493 int i;
494
495 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
496 v |= 0x2; /* MDIO Clock Divisor */
497 pcicore_write32(pc, mdio_control, v);
498
499 + if (pc->dev->id.revision >= 10) {
500 + max_retries = 200;
501 + ssb_pcie_mdio_set_phy(pc, device);
502 + }
503 +
504 v = (1 << 30); /* Start of Transaction */
505 - v |= (1 << 28); /* Write Transaction */
506 + v |= (1 << 29); /* Read Transaction */
507 v |= (1 << 17); /* Turnaround */
508 - v |= (u32)device << 22;
509 + if (pc->dev->id.revision < 10)
510 + v |= (u32)device << 22;
511 v |= (u32)address << 18;
512 - v |= data;
513 pcicore_write32(pc, mdio_data, v);
514 /* Wait for the device to complete the transaction */
515 udelay(10);
516 - for (i = 0; i < 10; i++) {
517 + for (i = 0; i < max_retries; i++) {
518 v = pcicore_read32(pc, mdio_control);
519 - if (v & 0x100 /* Trans complete */)
520 + if (v & 0x100 /* Trans complete */) {
521 + udelay(10);
522 + ret = pcicore_read32(pc, mdio_data);
523 break;
524 + }
525 msleep(1);
526 }
527 pcicore_write32(pc, mdio_control, 0);
528 + return ret;
529 }
530
531 -static void ssb_broadcast_value(struct ssb_device *dev,
532 - u32 address, u32 data)
533 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
534 + u8 address, u16 data)
535 {
536 - /* This is used for both, PCI and ChipCommon core, so be careful. */
537 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
538 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
539 + const u16 mdio_control = 0x128;
540 + const u16 mdio_data = 0x12C;
541 + int max_retries = 10;
542 + u32 v;
543 + int i;
544
545 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
546 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
547 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
548 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
549 -}
550 + v = 0x80; /* Enable Preamble Sequence */
551 + v |= 0x2; /* MDIO Clock Divisor */
552 + pcicore_write32(pc, mdio_control, v);
553
554 -static void ssb_commit_settings(struct ssb_bus *bus)
555 -{
556 - struct ssb_device *dev;
557 + if (pc->dev->id.revision >= 10) {
558 + max_retries = 200;
559 + ssb_pcie_mdio_set_phy(pc, device);
560 + }
561
562 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
563 - if (WARN_ON(!dev))
564 - return;
565 - /* This forces an update of the cached registers. */
566 - ssb_broadcast_value(dev, 0xFD8, 0);
567 + v = (1 << 30); /* Start of Transaction */
568 + v |= (1 << 28); /* Write Transaction */
569 + v |= (1 << 17); /* Turnaround */
570 + if (pc->dev->id.revision < 10)
571 + v |= (u32)device << 22;
572 + v |= (u32)address << 18;
573 + v |= data;
574 + pcicore_write32(pc, mdio_data, v);
575 + /* Wait for the device to complete the transaction */
576 + udelay(10);
577 + for (i = 0; i < max_retries; i++) {
578 + v = pcicore_read32(pc, mdio_control);
579 + if (v & 0x100 /* Trans complete */)
580 + break;
581 + msleep(1);
582 + }
583 + pcicore_write32(pc, mdio_control, 0);
584 }
585
586 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
587 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
588 if (pc->setup_done)
589 goto out;
590 if (pdev->id.coreid == SSB_DEV_PCI) {
591 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
592 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
593 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
594 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
595 -
596 - if (pdev->id.revision < 5) {
597 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
598 - tmp &= ~SSB_IMCFGLO_SERTO;
599 - tmp |= 2;
600 - tmp &= ~SSB_IMCFGLO_REQTO;
601 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
602 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
603 - ssb_commit_settings(bus);
604 - } else if (pdev->id.revision >= 11) {
605 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
606 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
607 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
608 - }
609 + ssb_pcicore_pci_setup_workarounds(pc);
610 } else {
611 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
612 - //TODO: Better make defines for all these magic PCIE values.
613 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
614 - /* TLP Workaround register. */
615 - tmp = ssb_pcie_read(pc, 0x4);
616 - tmp |= 0x8;
617 - ssb_pcie_write(pc, 0x4, tmp);
618 - }
619 - if (pdev->id.revision == 0) {
620 - const u8 serdes_rx_device = 0x1F;
621 -
622 - ssb_pcie_mdio_write(pc, serdes_rx_device,
623 - 2 /* Timer */, 0x8128);
624 - ssb_pcie_mdio_write(pc, serdes_rx_device,
625 - 6 /* CDR */, 0x0100);
626 - ssb_pcie_mdio_write(pc, serdes_rx_device,
627 - 7 /* CDR BW */, 0x1466);
628 - } else if (pdev->id.revision == 1) {
629 - /* DLLP Link Control register. */
630 - tmp = ssb_pcie_read(pc, 0x100);
631 - tmp |= 0x40;
632 - ssb_pcie_write(pc, 0x100, tmp);
633 - }
634 + ssb_pcicore_pcie_setup_workarounds(pc);
635 }
636 pc->setup_done = 1;
637 out:
638 --- a/drivers/ssb/main.c
639 +++ b/drivers/ssb/main.c
640 @@ -3,7 +3,7 @@
641 * Subsystem core
642 *
643 * Copyright 2005, Broadcom Corporation
644 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
645 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
646 *
647 * Licensed under the GNU/GPL. See COPYING for details.
648 */
649 @@ -12,6 +12,7 @@
650
651 #include <linux/delay.h>
652 #include <linux/io.h>
653 +#include <linux/module.h>
654 #include <linux/ssb/ssb.h>
655 #include <linux/ssb/ssb_regs.h>
656 #include <linux/ssb/ssb_driver_gige.h>
657 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
658 put_device(dev->dev);
659 }
660
661 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
662 -{
663 - if (drv)
664 - get_driver(&drv->drv);
665 - return drv;
666 -}
667 -
668 -static inline void ssb_driver_put(struct ssb_driver *drv)
669 -{
670 - if (drv)
671 - put_driver(&drv->drv);
672 -}
673 -
674 static int ssb_device_resume(struct device *dev)
675 {
676 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
677 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
678 ssb_device_put(sdev);
679 continue;
680 }
681 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
682 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
683 - ssb_device_put(sdev);
684 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
685 + if (SSB_WARN_ON(!sdrv->remove))
686 continue;
687 - }
688 sdrv->remove(sdev);
689 ctx->device_frozen[i] = 1;
690 }
691 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
692 dev_name(sdev->dev));
693 result = err;
694 }
695 - ssb_driver_put(sdrv);
696 ssb_device_put(sdev);
697 }
698
699 @@ -557,7 +542,7 @@ error:
700 }
701
702 /* Needs ssb_buses_lock() */
703 -static int ssb_attach_queued_buses(void)
704 +static int __devinit ssb_attach_queued_buses(void)
705 {
706 struct ssb_bus *bus, *n;
707 int err = 0;
708 @@ -768,9 +753,9 @@ out:
709 return err;
710 }
711
712 -static int ssb_bus_register(struct ssb_bus *bus,
713 - ssb_invariants_func_t get_invariants,
714 - unsigned long baseaddr)
715 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
716 + ssb_invariants_func_t get_invariants,
717 + unsigned long baseaddr)
718 {
719 int err;
720
721 @@ -851,8 +836,8 @@ err_disable_xtal:
722 }
723
724 #ifdef CONFIG_SSB_PCIHOST
725 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
726 - struct pci_dev *host_pci)
727 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
728 + struct pci_dev *host_pci)
729 {
730 int err;
731
732 @@ -875,9 +860,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
733 #endif /* CONFIG_SSB_PCIHOST */
734
735 #ifdef CONFIG_SSB_PCMCIAHOST
736 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
737 - struct pcmcia_device *pcmcia_dev,
738 - unsigned long baseaddr)
739 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
740 + struct pcmcia_device *pcmcia_dev,
741 + unsigned long baseaddr)
742 {
743 int err;
744
745 @@ -897,8 +882,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
746 #endif /* CONFIG_SSB_PCMCIAHOST */
747
748 #ifdef CONFIG_SSB_SDIOHOST
749 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
750 - unsigned int quirks)
751 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
752 + struct sdio_func *func,
753 + unsigned int quirks)
754 {
755 int err;
756
757 @@ -918,9 +904,9 @@ int ssb_bus_sdiobus_register(struct ssb_
758 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
759 #endif /* CONFIG_SSB_PCMCIAHOST */
760
761 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
762 - unsigned long baseaddr,
763 - ssb_invariants_func_t get_invariants)
764 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
765 + unsigned long baseaddr,
766 + ssb_invariants_func_t get_invariants)
767 {
768 int err;
769
770 @@ -1001,8 +987,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
771 switch (plltype) {
772 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
773 if (m & SSB_CHIPCO_CLK_T6_MMASK)
774 - return SSB_CHIPCO_CLK_T6_M0;
775 - return SSB_CHIPCO_CLK_T6_M1;
776 + return SSB_CHIPCO_CLK_T6_M1;
777 + return SSB_CHIPCO_CLK_T6_M0;
778 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
779 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
780 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
781 @@ -1092,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
782 u32 plltype;
783 u32 clkctl_n, clkctl_m;
784
785 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
786 + return ssb_pmu_get_controlclock(&bus->chipco);
787 +
788 if (ssb_extif_available(&bus->extif))
789 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
790 &clkctl_n, &clkctl_m);
791 @@ -1117,23 +1106,22 @@ static u32 ssb_tmslow_reject_bitmask(str
792 {
793 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
794
795 - /* The REJECT bit changed position in TMSLOW between
796 - * Backplane revisions. */
797 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
798 switch (rev) {
799 case SSB_IDLOW_SSBREV_22:
800 - return SSB_TMSLOW_REJECT_22;
801 + case SSB_IDLOW_SSBREV_24:
802 + case SSB_IDLOW_SSBREV_26:
803 + return SSB_TMSLOW_REJECT;
804 case SSB_IDLOW_SSBREV_23:
805 return SSB_TMSLOW_REJECT_23;
806 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
807 - case SSB_IDLOW_SSBREV_25: /* same here */
808 - case SSB_IDLOW_SSBREV_26: /* same here */
809 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
810 case SSB_IDLOW_SSBREV_27: /* same here */
811 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
812 + return SSB_TMSLOW_REJECT; /* this is a guess */
813 default:
814 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
815 WARN_ON(1);
816 }
817 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
818 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
819 }
820
821 int ssb_device_is_enabled(struct ssb_device *dev)
822 @@ -1260,13 +1248,34 @@ void ssb_device_disable(struct ssb_devic
823 }
824 EXPORT_SYMBOL(ssb_device_disable);
825
826 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
827 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
828 +{
829 + u16 chip_id = dev->bus->chip_id;
830 +
831 + if (dev->id.coreid == SSB_DEV_80211) {
832 + return (chip_id == 0x4322 || chip_id == 43221 ||
833 + chip_id == 43231 || chip_id == 43222);
834 + }
835 +
836 + return 0;
837 +}
838 +
839 u32 ssb_dma_translation(struct ssb_device *dev)
840 {
841 switch (dev->bus->bustype) {
842 case SSB_BUSTYPE_SSB:
843 return 0;
844 case SSB_BUSTYPE_PCI:
845 - return SSB_PCI_DMA;
846 + if (pci_is_pcie(dev->bus->host_pci) &&
847 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
848 + return SSB_PCIE_DMA_H32;
849 + } else {
850 + if (ssb_dma_translation_special_bit(dev))
851 + return SSB_PCIE_DMA_H32;
852 + else
853 + return SSB_PCI_DMA;
854 + }
855 default:
856 __ssb_dma_not_implemented(dev);
857 }
858 @@ -1309,20 +1318,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
859
860 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
861 {
862 - struct ssb_chipcommon *cc;
863 int err;
864 enum ssb_clkmode mode;
865
866 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
867 if (err)
868 goto error;
869 - cc = &bus->chipco;
870 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
871 - ssb_chipco_set_clockmode(cc, mode);
872
873 #ifdef CONFIG_SSB_DEBUG
874 bus->powered_up = 1;
875 #endif
876 +
877 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
878 + ssb_chipco_set_clockmode(&bus->chipco, mode);
879 +
880 return 0;
881 error:
882 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
883 @@ -1330,6 +1339,37 @@ error:
884 }
885 EXPORT_SYMBOL(ssb_bus_powerup);
886
887 +static void ssb_broadcast_value(struct ssb_device *dev,
888 + u32 address, u32 data)
889 +{
890 +#ifdef CONFIG_SSB_DRIVER_PCICORE
891 + /* This is used for both, PCI and ChipCommon core, so be careful. */
892 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
893 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
894 +#endif
895 +
896 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
897 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
898 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
899 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
900 +}
901 +
902 +void ssb_commit_settings(struct ssb_bus *bus)
903 +{
904 + struct ssb_device *dev;
905 +
906 +#ifdef CONFIG_SSB_DRIVER_PCICORE
907 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
908 +#else
909 + dev = bus->chipco.dev;
910 +#endif
911 + if (WARN_ON(!dev))
912 + return;
913 + /* This forces an update of the cached registers. */
914 + ssb_broadcast_value(dev, 0xFD8, 0);
915 +}
916 +EXPORT_SYMBOL(ssb_commit_settings);
917 +
918 u32 ssb_admatch_base(u32 adm)
919 {
920 u32 base = 0;
921 --- a/drivers/ssb/pci.c
922 +++ b/drivers/ssb/pci.c
923 @@ -1,7 +1,7 @@
924 /*
925 * Sonics Silicon Backplane PCI-Hostbus related functions.
926 *
927 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
928 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
929 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
930 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
931 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
932 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
933 {
934 int i;
935 u16 v;
936 - s8 gain;
937 u16 loc[3];
938
939 if (out->revision == 3) /* rev 3 moved MAC */
940 @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
941 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
942
943 /* Extract the antenna gain values. */
944 - gain = r123_extract_antgain(out->revision, in,
945 - SSB_SPROM1_AGAIN_BG,
946 - SSB_SPROM1_AGAIN_BG_SHIFT);
947 - out->antenna_gain.ghz24.a0 = gain;
948 - out->antenna_gain.ghz24.a1 = gain;
949 - out->antenna_gain.ghz24.a2 = gain;
950 - out->antenna_gain.ghz24.a3 = gain;
951 - gain = r123_extract_antgain(out->revision, in,
952 - SSB_SPROM1_AGAIN_A,
953 - SSB_SPROM1_AGAIN_A_SHIFT);
954 - out->antenna_gain.ghz5.a0 = gain;
955 - out->antenna_gain.ghz5.a1 = gain;
956 - out->antenna_gain.ghz5.a2 = gain;
957 - out->antenna_gain.ghz5.a3 = gain;
958 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
959 + SSB_SPROM1_AGAIN_BG,
960 + SSB_SPROM1_AGAIN_BG_SHIFT);
961 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
962 + SSB_SPROM1_AGAIN_A,
963 + SSB_SPROM1_AGAIN_A_SHIFT);
964 }
965
966 /* Revs 4 5 and 8 have partially shared layout */
967 @@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
968 }
969
970 /* Extract the antenna gain values. */
971 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
972 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
973 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
974 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
975 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
976 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
977 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
978 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
979 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
980 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
981 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
982 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
983 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
984 - sizeof(out->antenna_gain.ghz5));
985
986 sprom_extract_r458(out, in);
987
988 @@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
989 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
990 {
991 int i;
992 - u16 v;
993 + u16 v, o;
994 + u16 pwr_info_offset[] = {
995 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
996 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
997 + };
998 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
999 + ARRAY_SIZE(out->core_pwr_info));
1000
1001 /* extract the MAC address */
1002 for (i = 0; i < 3; i++) {
1003 @@ -596,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
1004 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1005
1006 /* Extract the antenna gain values. */
1007 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1008 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1009 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1010 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1011 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1012 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1013 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1014 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1015 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1016 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1017 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1018 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1019 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1020 - sizeof(out->antenna_gain.ghz5));
1021 +
1022 + /* Extract cores power info info */
1023 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1024 + o = pwr_info_offset[i];
1025 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1026 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1027 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1028 + SSB_SPROM8_2G_MAXP, 0);
1029 +
1030 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1031 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1032 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1033 +
1034 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1035 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1036 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1037 + SSB_SPROM8_5G_MAXP, 0);
1038 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1039 + SSB_SPROM8_5GH_MAXP, 0);
1040 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1041 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1042 +
1043 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1044 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1045 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1046 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1047 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1048 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1049 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1050 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1051 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1052 + }
1053 +
1054 + /* Extract FEM info */
1055 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1056 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1057 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1058 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1059 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1060 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1061 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1062 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1063 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1064 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1065 +
1066 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1067 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1068 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1069 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1070 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1071 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1072 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1073 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1074 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1075 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1076
1077 sprom_extract_r458(out, in);
1078
1079 @@ -662,7 +710,6 @@ static int sprom_extract(struct ssb_bus
1080 static int ssb_pci_sprom_get(struct ssb_bus *bus,
1081 struct ssb_sprom *sprom)
1082 {
1083 - const struct ssb_sprom *fallback;
1084 int err;
1085 u16 *buf;
1086
1087 @@ -707,10 +754,17 @@ static int ssb_pci_sprom_get(struct ssb_
1088 if (err) {
1089 /* All CRC attempts failed.
1090 * Maybe there is no SPROM on the device?
1091 - * If we have a fallback, use that. */
1092 - fallback = ssb_get_fallback_sprom();
1093 - if (fallback) {
1094 - memcpy(sprom, fallback, sizeof(*sprom));
1095 + * Now we ask the arch code if there is some sprom
1096 + * available for this device in some other storage */
1097 + err = ssb_fill_sprom_with_fallback(bus, sprom);
1098 + if (err) {
1099 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
1100 + " fallback SPROM failed (err %d)\n",
1101 + err);
1102 + } else {
1103 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1104 + " revision %d provided by"
1105 + " platform.\n", sprom->revision);
1106 err = 0;
1107 goto out_free;
1108 }
1109 @@ -728,12 +782,9 @@ out_free:
1110 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
1111 struct ssb_boardinfo *bi)
1112 {
1113 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
1114 - &bi->vendor);
1115 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
1116 - &bi->type);
1117 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1118 - &bi->rev);
1119 + bi->vendor = bus->host_pci->subsystem_vendor;
1120 + bi->type = bus->host_pci->subsystem_device;
1121 + bi->rev = bus->host_pci->revision;
1122 }
1123
1124 int ssb_pci_get_invariants(struct ssb_bus *bus,
1125 --- a/drivers/ssb/pcihost_wrapper.c
1126 +++ b/drivers/ssb/pcihost_wrapper.c
1127 @@ -6,7 +6,7 @@
1128 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1129 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1130 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1131 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1132 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1133 *
1134 * Licensed under the GNU/GPL. See COPYING for details.
1135 */
1136 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
1137 # define ssb_pcihost_resume NULL
1138 #endif /* CONFIG_PM */
1139
1140 -static int ssb_pcihost_probe(struct pci_dev *dev,
1141 - const struct pci_device_id *id)
1142 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1143 + const struct pci_device_id *id)
1144 {
1145 struct ssb_bus *ssb;
1146 int err = -ENOMEM;
1147 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1148 pci_set_drvdata(dev, NULL);
1149 }
1150
1151 -int ssb_pcihost_register(struct pci_driver *driver)
1152 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1153 {
1154 driver->probe = ssb_pcihost_probe;
1155 driver->remove = ssb_pcihost_remove;
1156 --- a/drivers/ssb/scan.c
1157 +++ b/drivers/ssb/scan.c
1158 @@ -2,7 +2,7 @@
1159 * Sonics Silicon Backplane
1160 * Bus scanning
1161 *
1162 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
1163 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
1164 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1165 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1166 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1167 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
1168 #ifdef CONFIG_SSB_PCIHOST
1169 if (bus->bustype == SSB_BUSTYPE_PCI) {
1170 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1171 - bus->host_pci->device == 0x4324)
1172 + ((bus->host_pci->device == 0x4313) ||
1173 + (bus->host_pci->device == 0x431A) ||
1174 + (bus->host_pci->device == 0x4321) ||
1175 + (bus->host_pci->device == 0x4324)))
1176 return 1;
1177 }
1178 #endif /* CONFIG_SSB_PCIHOST */
1179 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1180 } else {
1181 if (bus->bustype == SSB_BUSTYPE_PCI) {
1182 bus->chip_id = pcidev_to_chipid(bus->host_pci);
1183 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1184 - &bus->chip_rev);
1185 + bus->chip_rev = bus->host_pci->revision;
1186 bus->chip_package = 0;
1187 } else {
1188 bus->chip_id = 0x4710;
1189 @@ -316,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
1190 bus->chip_package = 0;
1191 }
1192 }
1193 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1194 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1195 + bus->chip_package);
1196 if (!bus->nr_devices)
1197 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1198 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1199 --- a/drivers/ssb/sprom.c
1200 +++ b/drivers/ssb/sprom.c
1201 @@ -2,7 +2,7 @@
1202 * Sonics Silicon Backplane
1203 * Common SPROM support routines
1204 *
1205 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1206 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1207 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1208 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1209 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1210 @@ -17,7 +17,7 @@
1211 #include <linux/slab.h>
1212
1213
1214 -static const struct ssb_sprom *fallback_sprom;
1215 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1216
1217
1218 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1219 @@ -145,36 +145,43 @@ out:
1220 }
1221
1222 /**
1223 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1224 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1225 + * fallback SPROM if no SPROM is found.
1226 *
1227 - * @sprom: The SPROM data structure to register.
1228 + * @sprom_callback: The callback function.
1229 *
1230 - * With this function the architecture implementation may register a fallback
1231 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1232 - * where no valid SPROM can be found in the shadow registers.
1233 + * With this function the architecture implementation may register a
1234 + * callback handler which fills the SPROM data structure. The fallback is
1235 + * only used for PCI based SSB devices, where no valid SPROM can be found
1236 + * in the shadow registers.
1237 + *
1238 + * This function is useful for weird architectures that have a half-assed
1239 + * SSB device hardwired to their PCI bus.
1240 + *
1241 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1242 + * devices currently don't use this fallback.
1243 + * Architectures must provide the SPROM for native SSB devices anyway, so
1244 + * the fallback also isn't used for native devices.
1245 *
1246 - * This function is useful for weird architectures that have a half-assed SSB device
1247 - * hardwired to their PCI bus.
1248 - *
1249 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1250 - * don't use this fallback.
1251 - * Architectures must provide the SPROM for native SSB devices anyway,
1252 - * so the fallback also isn't used for native devices.
1253 - *
1254 - * This function is available for architecture code, only. So it is not exported.
1255 + * This function is available for architecture code, only. So it is not
1256 + * exported.
1257 */
1258 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1259 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1260 + struct ssb_sprom *out))
1261 {
1262 - if (fallback_sprom)
1263 + if (get_fallback_sprom)
1264 return -EEXIST;
1265 - fallback_sprom = sprom;
1266 + get_fallback_sprom = sprom_callback;
1267
1268 return 0;
1269 }
1270
1271 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1272 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1273 {
1274 - return fallback_sprom;
1275 + if (!get_fallback_sprom)
1276 + return -ENOENT;
1277 +
1278 + return get_fallback_sprom(bus, out);
1279 }
1280
1281 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1282 --- a/drivers/ssb/ssb_private.h
1283 +++ b/drivers/ssb/ssb_private.h
1284 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1285 const char *buf, size_t count,
1286 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1287 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1288 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1289 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1290 + struct ssb_sprom *out);
1291
1292
1293 /* core.c */
1294 @@ -206,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
1295 }
1296 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1297
1298 +/* driver_chipcommon_pmu.c */
1299 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
1300 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
1301 +
1302 #endif /* LINUX_SSB_PRIVATE_H_ */
1303 --- a/include/linux/ssb/ssb.h
1304 +++ b/include/linux/ssb/ssb.h
1305 @@ -16,6 +16,12 @@ struct pcmcia_device;
1306 struct ssb_bus;
1307 struct ssb_driver;
1308
1309 +struct ssb_sprom_core_pwr_info {
1310 + u8 itssi_2g, itssi_5g;
1311 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
1312 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
1313 +};
1314 +
1315 struct ssb_sprom {
1316 u8 revision;
1317 u8 il0mac[6]; /* MAC address for 802.11b/g */
1318 @@ -25,8 +31,13 @@ struct ssb_sprom {
1319 u8 et1phyaddr; /* MII address for enet1 */
1320 u8 et0mdcport; /* MDIO for enet0 */
1321 u8 et1mdcport; /* MDIO for enet1 */
1322 - u8 board_rev; /* Board revision number from SPROM. */
1323 + u16 board_rev; /* Board revision number from SPROM. */
1324 + u16 board_num; /* Board number from SPROM. */
1325 + u16 board_type; /* Board type from SPROM. */
1326 u8 country_code; /* Country Code */
1327 + char alpha2[2]; /* Country Code as two chars like EU or US */
1328 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1329 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1330 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1331 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1332 u16 pa0b0;
1333 @@ -45,10 +56,10 @@ struct ssb_sprom {
1334 u8 gpio1; /* GPIO pin 1 */
1335 u8 gpio2; /* GPIO pin 2 */
1336 u8 gpio3; /* GPIO pin 3 */
1337 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1338 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1339 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1340 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1341 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1342 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1343 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1344 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1345 u8 itssi_a; /* Idle TSSI Target for A-PHY */
1346 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
1347 u8 tri2g; /* 2.4GHz TX isolation */
1348 @@ -59,8 +70,8 @@ struct ssb_sprom {
1349 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
1350 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
1351 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
1352 - u8 rxpo2g; /* 2GHz RX power offset */
1353 - u8 rxpo5g; /* 5GHz RX power offset */
1354 + s8 rxpo2g; /* 2GHz RX power offset */
1355 + s8 rxpo5g; /* 5GHz RX power offset */
1356 u8 rssisav2g; /* 2GHz RSSI params */
1357 u8 rssismc2g;
1358 u8 rssismf2g;
1359 @@ -80,26 +91,104 @@ struct ssb_sprom {
1360 u16 boardflags2_hi; /* Board flags (bits 48-63) */
1361 /* TODO store board flags in a single u64 */
1362
1363 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
1364 +
1365 /* Antenna gain values for up to 4 antennas
1366 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
1367 * loss in the connectors is bigger than the gain. */
1368 struct {
1369 - struct {
1370 - s8 a0, a1, a2, a3;
1371 - } ghz24; /* 2.4GHz band */
1372 - struct {
1373 - s8 a0, a1, a2, a3;
1374 - } ghz5; /* 5GHz band */
1375 + s8 a0, a1, a2, a3;
1376 } antenna_gain;
1377
1378 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1379 + struct {
1380 + struct {
1381 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1382 + } ghz2;
1383 + struct {
1384 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1385 + } ghz5;
1386 + } fem;
1387 +
1388 + u16 mcs2gpo[8];
1389 + u16 mcs5gpo[8];
1390 + u16 mcs5glpo[8];
1391 + u16 mcs5ghpo[8];
1392 + u8 opo;
1393 +
1394 + u8 rxgainerr2ga[3];
1395 + u8 rxgainerr5gla[3];
1396 + u8 rxgainerr5gma[3];
1397 + u8 rxgainerr5gha[3];
1398 + u8 rxgainerr5gua[3];
1399 +
1400 + u8 noiselvl2ga[3];
1401 + u8 noiselvl5gla[3];
1402 + u8 noiselvl5gma[3];
1403 + u8 noiselvl5gha[3];
1404 + u8 noiselvl5gua[3];
1405 +
1406 + u8 regrev;
1407 + u8 txchain;
1408 + u8 rxchain;
1409 + u8 antswitch;
1410 + u16 cddpo;
1411 + u16 stbcpo;
1412 + u16 bw40po;
1413 + u16 bwduppo;
1414 +
1415 + u8 tempthresh;
1416 + u8 tempoffset;
1417 + u16 rawtempsense;
1418 + u8 measpower;
1419 + u8 tempsense_slope;
1420 + u8 tempcorrx;
1421 + u8 tempsense_option;
1422 + u8 freqoffset_corr;
1423 + u8 iqcal_swp_dis;
1424 + u8 hw_iqcal_en;
1425 + u8 elna2g;
1426 + u8 elna5g;
1427 + u8 phycal_tempdelta;
1428 + u8 temps_period;
1429 + u8 temps_hysteresis;
1430 + u8 measpower1;
1431 + u8 measpower2;
1432 + u8 pcieingress_war;
1433 +
1434 + /* power per rate from sromrev 9 */
1435 + u16 cckbw202gpo;
1436 + u16 cckbw20ul2gpo;
1437 + u32 legofdmbw202gpo;
1438 + u32 legofdmbw20ul2gpo;
1439 + u32 legofdmbw205glpo;
1440 + u32 legofdmbw20ul5glpo;
1441 + u32 legofdmbw205gmpo;
1442 + u32 legofdmbw20ul5gmpo;
1443 + u32 legofdmbw205ghpo;
1444 + u32 legofdmbw20ul5ghpo;
1445 + u32 mcsbw202gpo;
1446 + u32 mcsbw20ul2gpo;
1447 + u32 mcsbw402gpo;
1448 + u32 mcsbw205glpo;
1449 + u32 mcsbw20ul5glpo;
1450 + u32 mcsbw405glpo;
1451 + u32 mcsbw205gmpo;
1452 + u32 mcsbw20ul5gmpo;
1453 + u32 mcsbw405gmpo;
1454 + u32 mcsbw205ghpo;
1455 + u32 mcsbw20ul5ghpo;
1456 + u32 mcsbw405ghpo;
1457 + u16 mcs32po;
1458 + u16 legofdm40duppo;
1459 + u8 sar2g;
1460 + u8 sar5g;
1461 };
1462
1463 /* Information about the PCB the circuitry is soldered on. */
1464 struct ssb_boardinfo {
1465 u16 vendor;
1466 u16 type;
1467 - u16 rev;
1468 + u8 rev;
1469 };
1470
1471
1472 @@ -229,10 +318,9 @@ struct ssb_driver {
1473 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1474
1475 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1476 -static inline int ssb_driver_register(struct ssb_driver *drv)
1477 -{
1478 - return __ssb_driver_register(drv, THIS_MODULE);
1479 -}
1480 +#define ssb_driver_register(drv) \
1481 + __ssb_driver_register(drv, THIS_MODULE)
1482 +
1483 extern void ssb_driver_unregister(struct ssb_driver *drv);
1484
1485
1486 @@ -308,7 +396,7 @@ struct ssb_bus {
1487
1488 /* ID information about the Chip. */
1489 u16 chip_id;
1490 - u16 chip_rev;
1491 + u8 chip_rev;
1492 u16 sprom_offset;
1493 u16 sprom_size; /* number of words in sprom */
1494 u8 chip_package;
1495 @@ -404,7 +492,9 @@ extern bool ssb_is_sprom_available(struc
1496
1497 /* Set a fallback SPROM.
1498 * See kdoc at the function definition for complete documentation. */
1499 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1500 +extern int ssb_arch_register_fallback_sprom(
1501 + int (*sprom_callback)(struct ssb_bus *bus,
1502 + struct ssb_sprom *out));
1503
1504 /* Suspend a SSB bus.
1505 * Call this from the parent bus suspend routine. */
1506 @@ -518,6 +608,7 @@ extern int ssb_bus_may_powerdown(struct
1507 * Otherwise static always-on powercontrol will be used. */
1508 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1509
1510 +extern void ssb_commit_settings(struct ssb_bus *bus);
1511
1512 /* Various helper functions */
1513 extern u32 ssb_admatch_base(u32 adm);
1514 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1515 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1516 @@ -8,7 +8,7 @@
1517 * gpio interface, extbus, and support for serial and parallel flashes.
1518 *
1519 * Copyright 2005, Broadcom Corporation
1520 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1521 + * Copyright 2006, Michael Buesch <m@bues.ch>
1522 *
1523 * Licensed under the GPL version 2. See COPYING for details.
1524 */
1525 @@ -123,6 +123,8 @@
1526 #define SSB_CHIPCO_FLASHDATA 0x0048
1527 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1528 #define SSB_CHIPCO_BCAST_DATA 0x0054
1529 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1530 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1531 #define SSB_CHIPCO_GPIOIN 0x0060
1532 #define SSB_CHIPCO_GPIOOUT 0x0064
1533 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1534 @@ -131,6 +133,9 @@
1535 #define SSB_CHIPCO_GPIOIRQ 0x0074
1536 #define SSB_CHIPCO_WATCHDOG 0x0080
1537 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1538 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1539 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1540 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1541 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1542 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1543 #define SSB_CHIPCO_CLOCK_N 0x0090
1544 @@ -189,8 +194,10 @@
1545 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1546 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1547 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1548 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1549 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1550 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1551 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1552 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1553 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1554 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1555 #define SSB_CHIPCO_UART0_DATA 0x0300
1556 #define SSB_CHIPCO_UART0_IMR 0x0304
1557 --- a/include/linux/ssb/ssb_regs.h
1558 +++ b/include/linux/ssb/ssb_regs.h
1559 @@ -97,7 +97,7 @@
1560 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1561 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
1562 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
1563 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
1564 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
1565 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
1566 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
1567 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1568 @@ -432,6 +432,56 @@
1569 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1570 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1571 #define SSB_SPROM8_RXPO5G_SHIFT 8
1572 +#define SSB_SPROM8_FEM2G 0x00AE
1573 +#define SSB_SPROM8_FEM5G 0x00B0
1574 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
1575 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
1576 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
1577 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
1578 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
1579 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
1580 +#define SSB_SROM8_FEM_TR_ISO 0x0700
1581 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
1582 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
1583 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
1584 +#define SSB_SPROM8_THERMAL 0x00B2
1585 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
1586 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
1587 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
1588 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
1589 +
1590 +/* There are 4 blocks with power info sharing the same layout */
1591 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
1592 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
1593 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
1594 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
1595 +
1596 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
1597 +#define SSB_SPROM8_2G_MAXP 0x00FF
1598 +#define SSB_SPROM8_2G_ITSSI 0xFF00
1599 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
1600 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
1601 +#define SSB_SROM8_2G_PA_1 0x04
1602 +#define SSB_SROM8_2G_PA_2 0x06
1603 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
1604 +#define SSB_SPROM8_5G_MAXP 0x00FF
1605 +#define SSB_SPROM8_5G_ITSSI 0xFF00
1606 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
1607 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
1608 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1609 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1610 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1611 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1612 +#define SSB_SROM8_5G_PA_1 0x0E
1613 +#define SSB_SROM8_5G_PA_2 0x10
1614 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1615 +#define SSB_SROM8_5GL_PA_1 0x14
1616 +#define SSB_SROM8_5GL_PA_2 0x16
1617 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1618 +#define SSB_SROM8_5GH_PA_1 0x1A
1619 +#define SSB_SROM8_5GH_PA_2 0x1C
1620 +
1621 +/* TODO: Make it deprecated */
1622 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1623 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1624 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1625 @@ -456,12 +506,53 @@
1626 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1627 #define SSB_SPROM8_PA1HIB1 0x00DA
1628 #define SSB_SPROM8_PA1HIB2 0x00DC
1629 +
1630 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1631 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1632 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1633 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1634 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1635
1636 +/* Values for boardflags_lo read from SPROM */
1637 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1638 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1639 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1640 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1641 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1642 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1643 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1644 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1645 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1646 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1647 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1648 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1649 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1650 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1651 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1652 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1653 +
1654 +/* Values for boardflags_hi read from SPROM */
1655 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1656 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1657 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1658 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1659 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1660 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1661 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1662 +
1663 +/* Values for boardflags2_lo read from SPROM */
1664 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1665 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1666 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1667 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1668 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1669 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1670 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1671 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1672 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1673 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1674 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1675 +
1676 /* Values for SSB_SPROM1_BINF_CCODE */
1677 enum {
1678 SSB_SPROM1CCODE_WORLD = 0,
1679 --- a/drivers/ssb/b43_pci_bridge.c
1680 +++ b/drivers/ssb/b43_pci_bridge.c
1681 @@ -5,12 +5,13 @@
1682 * because of its small size we include it in the SSB core
1683 * instead of creating a standalone module.
1684 *
1685 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1686 + * Copyright 2007 Michael Buesch <m@bues.ch>
1687 *
1688 * Licensed under the GNU/GPL. See COPYING for details.
1689 */
1690
1691 #include <linux/pci.h>
1692 +#include <linux/module.h>
1693 #include <linux/ssb/ssb.h>
1694
1695 #include "ssb_private.h"
1696 --- a/drivers/ssb/driver_extif.c
1697 +++ b/drivers/ssb/driver_extif.c
1698 @@ -3,7 +3,7 @@
1699 * Broadcom EXTIF core driver
1700 *
1701 * Copyright 2005, Broadcom Corporation
1702 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1703 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1704 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1705 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1706 *
1707 --- a/drivers/ssb/driver_mipscore.c
1708 +++ b/drivers/ssb/driver_mipscore.c
1709 @@ -3,7 +3,7 @@
1710 * Broadcom MIPS core driver
1711 *
1712 * Copyright 2005, Broadcom Corporation
1713 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1714 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1715 *
1716 * Licensed under the GNU/GPL. See COPYING for details.
1717 */
1718 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1719 struct ssb_bus *bus = mcore->dev->bus;
1720 u32 pll_type, n, m, rate = 0;
1721
1722 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1723 + return ssb_pmu_get_cpu_clock(&bus->chipco);
1724 +
1725 if (bus->extif.dev) {
1726 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1727 } else if (bus->chipco.dev) {
1728 --- a/drivers/ssb/embedded.c
1729 +++ b/drivers/ssb/embedded.c
1730 @@ -3,7 +3,7 @@
1731 * Embedded systems support code
1732 *
1733 * Copyright 2005-2008, Broadcom Corporation
1734 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1735 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1736 *
1737 * Licensed under the GNU/GPL. See COPYING for details.
1738 */
1739 --- a/drivers/ssb/pcmcia.c
1740 +++ b/drivers/ssb/pcmcia.c
1741 @@ -3,7 +3,7 @@
1742 * PCMCIA-Hostbus related functions
1743 *
1744 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1745 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1746 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1747 *
1748 * Licensed under the GNU/GPL. See COPYING for details.
1749 */
1750 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
1751 case SSB_PCMCIA_CIS_ANTGAIN:
1752 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1753 "antg tpl size");
1754 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
1755 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
1756 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
1757 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
1758 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
1759 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
1760 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
1761 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
1762 + sprom->antenna_gain.a0 = tuple->TupleData[1];
1763 + sprom->antenna_gain.a1 = tuple->TupleData[1];
1764 + sprom->antenna_gain.a2 = tuple->TupleData[1];
1765 + sprom->antenna_gain.a3 = tuple->TupleData[1];
1766 break;
1767 case SSB_PCMCIA_CIS_BFLAGS:
1768 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1769 --- a/drivers/ssb/sdio.c
1770 +++ b/drivers/ssb/sdio.c
1771 @@ -6,7 +6,7 @@
1772 *
1773 * Based on drivers/ssb/pcmcia.c
1774 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1775 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1776 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1777 *
1778 * Licensed under the GNU/GPL. See COPYING for details.
1779 *
1780 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
1781 case SSB_SDIO_CIS_ANTGAIN:
1782 GOTO_ERROR_ON(tuple->size != 2,
1783 "antg tpl size");
1784 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
1785 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
1786 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
1787 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
1788 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
1789 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
1790 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
1791 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
1792 + sprom->antenna_gain.a0 = tuple->data[1];
1793 + sprom->antenna_gain.a1 = tuple->data[1];
1794 + sprom->antenna_gain.a2 = tuple->data[1];
1795 + sprom->antenna_gain.a3 = tuple->data[1];
1796 break;
1797 case SSB_SDIO_CIS_BFLAGS:
1798 GOTO_ERROR_ON((tuple->size != 3) &&
1799 --- a/include/linux/ssb/ssb_driver_gige.h
1800 +++ b/include/linux/ssb/ssb_driver_gige.h
1801 @@ -2,6 +2,7 @@
1802 #define LINUX_SSB_DRIVER_GIGE_H_
1803
1804 #include <linux/ssb/ssb.h>
1805 +#include <linux/bug.h>
1806 #include <linux/pci.h>
1807 #include <linux/spinlock.h>
1808
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