71ecc96acdb69f15d73e931e471d45c2a8f5ef58
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.39 / 022-ssb_pcicore_build_breakage.patch
1 From 1159024d4c0aafecaa0c6635c55153b4b39cc1c8 Mon Sep 17 00:00:00 2001
2 From: "John W. Linville" <linville@tuxdriver.com>
3 Date: Fri, 13 May 2011 09:23:47 -0400
4 Subject: [PATCH] ssb: fix pcicore build breakage
5
6 drivers/ssb/main.c:1336: error: 'SSB_PCICORE_BCAST_ADDR' undeclared (first use in this function)
7 drivers/ssb/main.c:1337: error: 'SSB_PCICORE_BCAST_DATA' undeclared (first use in this function)
8 drivers/ssb/main.c:1349: error: 'struct ssb_pcicore' has no member named 'dev'
9
10 Reported-by: Randy Dunlap <randy.dunlap@oracle.com>
11 Signed-off-by: John W. Linville <linville@tuxdriver.com>
12 ---
13 drivers/ssb/main.c | 14 ++++++++++----
14 1 files changed, 10 insertions(+), 4 deletions(-)
15
16 --- a/drivers/ssb/main.c
17 +++ b/drivers/ssb/main.c
18 @@ -1333,21 +1333,27 @@ EXPORT_SYMBOL(ssb_bus_powerup);
19 static void ssb_broadcast_value(struct ssb_device *dev,
20 u32 address, u32 data)
21 {
22 +#ifdef CONFIG_SSB_DRIVER_PCICORE
23 /* This is used for both, PCI and ChipCommon core, so be careful. */
24 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
25 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
26 +#endif
27
28 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
29 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
30 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
31 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
32 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
33 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
34 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
35 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
36 }
37
38 void ssb_commit_settings(struct ssb_bus *bus)
39 {
40 struct ssb_device *dev;
41
42 +#ifdef CONFIG_SSB_DRIVER_PCICORE
43 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
44 +#else
45 + dev = bus->chipco.dev;
46 +#endif
47 if (WARN_ON(!dev))
48 return;
49 /* This forces an update of the cached registers. */