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kernel: ssb/bcma: update to version from wireless-testing tag master-2012-05-16-2
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.2 / 020-ssb_update.patch
1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
3 @@ -29,6 +29,8 @@ static const struct pci_device_id b43_pc
4 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
5 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
6 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
7 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
8 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
9 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
10 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
11 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
12 --- a/drivers/ssb/driver_chipcommon_pmu.c
13 +++ b/drivers/ssb/driver_chipcommon_pmu.c
14 @@ -13,6 +13,9 @@
15 #include <linux/ssb/ssb_driver_chipcommon.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 +#ifdef CONFIG_BCM47XX
19 +#include <asm/mach-bcm47xx/nvram.h>
20 +#endif
21
22 #include "ssb_private.h"
23
24 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
25 u32 pmuctl, tmp, pllctl;
26 unsigned int i;
27
28 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
29 - /* The 5354 crystal freq is 25MHz */
30 - crystalfreq = 25000;
31 - }
32 if (crystalfreq)
33 e = pmu0_plltab_find_entry(crystalfreq);
34 if (!e)
35 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
36 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
37
38 if (bus->bustype == SSB_BUSTYPE_SSB) {
39 - /* TODO: The user may override the crystal frequency. */
40 +#ifdef CONFIG_BCM47XX
41 + char buf[20];
42 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
43 + crystalfreq = simple_strtoul(buf, NULL, 0);
44 +#endif
45 }
46
47 switch (bus->chip_id) {
48 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
49 ssb_pmu1_pllinit_r0(cc, crystalfreq);
50 break;
51 case 0x4328:
52 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
53 + break;
54 case 0x5354:
55 + if (crystalfreq == 0)
56 + crystalfreq = 25000;
57 ssb_pmu0_pllinit_r0(cc, crystalfreq);
58 break;
59 case 0x4322:
60 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
61
62 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
63 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
64 +
65 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
66 +{
67 + struct ssb_bus *bus = cc->dev->bus;
68 +
69 + switch (bus->chip_id) {
70 + case 0x5354:
71 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
72 + return 240000000;
73 + default:
74 + ssb_printk(KERN_ERR PFX
75 + "ERROR: PMU cpu clock unknown for device %04X\n",
76 + bus->chip_id);
77 + return 0;
78 + }
79 +}
80 +
81 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
82 +{
83 + struct ssb_bus *bus = cc->dev->bus;
84 +
85 + switch (bus->chip_id) {
86 + case 0x5354:
87 + return 120000000;
88 + default:
89 + ssb_printk(KERN_ERR PFX
90 + "ERROR: PMU controlclock unknown for device %04X\n",
91 + bus->chip_id);
92 + return 0;
93 + }
94 +}
95 --- a/drivers/ssb/driver_mipscore.c
96 +++ b/drivers/ssb/driver_mipscore.c
97 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
98 struct ssb_bus *bus = mcore->dev->bus;
99 u32 pll_type, n, m, rate = 0;
100
101 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
102 + return ssb_pmu_get_cpu_clock(&bus->chipco);
103 +
104 if (bus->extif.dev) {
105 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
106 } else if (bus->chipco.dev) {
107 --- a/drivers/ssb/driver_pcicore.c
108 +++ b/drivers/ssb/driver_pcicore.c
109 @@ -75,7 +75,7 @@ static u32 get_cfgspace_addr(struct ssb_
110 u32 tmp;
111
112 /* We do only have one cardbus device behind the bridge. */
113 - if (pc->cardbusmode && (dev >= 1))
114 + if (pc->cardbusmode && (dev > 1))
115 goto out;
116
117 if (bus == 0) {
118 --- a/drivers/ssb/main.c
119 +++ b/drivers/ssb/main.c
120 @@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
121 put_device(dev->dev);
122 }
123
124 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
125 -{
126 - if (drv)
127 - get_driver(&drv->drv);
128 - return drv;
129 -}
130 -
131 -static inline void ssb_driver_put(struct ssb_driver *drv)
132 -{
133 - if (drv)
134 - put_driver(&drv->drv);
135 -}
136 -
137 static int ssb_device_resume(struct device *dev)
138 {
139 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
140 @@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
141 ssb_device_put(sdev);
142 continue;
143 }
144 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
145 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
146 - ssb_device_put(sdev);
147 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
148 + if (SSB_WARN_ON(!sdrv->remove))
149 continue;
150 - }
151 sdrv->remove(sdev);
152 ctx->device_frozen[i] = 1;
153 }
154 @@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
155 dev_name(sdev->dev));
156 result = err;
157 }
158 - ssb_driver_put(sdrv);
159 ssb_device_put(sdev);
160 }
161
162 @@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
163 u32 plltype;
164 u32 clkctl_n, clkctl_m;
165
166 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
167 + return ssb_pmu_get_controlclock(&bus->chipco);
168 +
169 if (ssb_extif_available(&bus->extif))
170 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
171 &clkctl_n, &clkctl_m);
172 --- a/drivers/ssb/pci.c
173 +++ b/drivers/ssb/pci.c
174 @@ -178,6 +178,18 @@ err_pci:
175 #define SPEX(_outvar, _offset, _mask, _shift) \
176 SPEX16(_outvar, _offset, _mask, _shift)
177
178 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
179 + do { \
180 + SPEX(_field[0], _offset + 0, _mask, _shift); \
181 + SPEX(_field[1], _offset + 2, _mask, _shift); \
182 + SPEX(_field[2], _offset + 4, _mask, _shift); \
183 + SPEX(_field[3], _offset + 6, _mask, _shift); \
184 + SPEX(_field[4], _offset + 8, _mask, _shift); \
185 + SPEX(_field[5], _offset + 10, _mask, _shift); \
186 + SPEX(_field[6], _offset + 12, _mask, _shift); \
187 + SPEX(_field[7], _offset + 14, _mask, _shift); \
188 + } while (0)
189 +
190
191 static inline u8 ssb_crc8(u8 crc, u8 data)
192 {
193 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
194 {
195 int i;
196 u16 v;
197 - s8 gain;
198 u16 loc[3];
199
200 if (out->revision == 3) /* rev 3 moved MAC */
201 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
202 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
203 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
204 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
205 - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
206 - SSB_SPROM1_BINF_CCODE_SHIFT);
207 + if (out->revision == 1)
208 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
209 + SSB_SPROM1_BINF_CCODE_SHIFT);
210 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
211 SSB_SPROM1_BINF_ANTA_SHIFT);
212 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
213 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
214 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
215 if (out->revision >= 2)
216 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
217 + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
218 + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
219
220 /* Extract the antenna gain values. */
221 - gain = r123_extract_antgain(out->revision, in,
222 - SSB_SPROM1_AGAIN_BG,
223 - SSB_SPROM1_AGAIN_BG_SHIFT);
224 - out->antenna_gain.ghz24.a0 = gain;
225 - out->antenna_gain.ghz24.a1 = gain;
226 - out->antenna_gain.ghz24.a2 = gain;
227 - out->antenna_gain.ghz24.a3 = gain;
228 - gain = r123_extract_antgain(out->revision, in,
229 - SSB_SPROM1_AGAIN_A,
230 - SSB_SPROM1_AGAIN_A_SHIFT);
231 - out->antenna_gain.ghz5.a0 = gain;
232 - out->antenna_gain.ghz5.a1 = gain;
233 - out->antenna_gain.ghz5.a2 = gain;
234 - out->antenna_gain.ghz5.a3 = gain;
235 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
236 + SSB_SPROM1_AGAIN_BG,
237 + SSB_SPROM1_AGAIN_BG_SHIFT);
238 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
239 + SSB_SPROM1_AGAIN_A,
240 + SSB_SPROM1_AGAIN_A_SHIFT);
241 }
242
243 /* Revs 4 5 and 8 have partially shared layout */
244 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
245 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
246 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
247 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
248 + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
249 if (out->revision == 4) {
250 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
251 + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
252 + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
253 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
254 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
255 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
256 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
257 } else {
258 - SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
259 + SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
260 + SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
261 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
262 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
263 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
264 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
265 }
266
267 /* Extract the antenna gain values. */
268 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
269 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
270 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
271 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
272 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
273 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
274 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
275 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
276 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
277 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
278 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
279 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
280 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
281 - sizeof(out->antenna_gain.ghz5));
282
283 sprom_extract_r458(out, in);
284
285 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
286 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
287 {
288 int i;
289 - u16 v;
290 + u16 v, o;
291 + u16 pwr_info_offset[] = {
292 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
293 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
294 + };
295 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
296 + ARRAY_SIZE(out->core_pwr_info));
297
298 /* extract the MAC address */
299 for (i = 0; i < 3; i++) {
300 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
301 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
302 }
303 - SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
304 + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
305 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
306 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
307 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
308 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
309 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
310 @@ -596,17 +611,127 @@ static void sprom_extract_r8(struct ssb_
311 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
312
313 /* Extract the antenna gain values. */
314 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
315 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
316 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
317 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
318 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
319 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
320 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
321 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
322 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
323 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
324 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
325 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
326 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
327 - sizeof(out->antenna_gain.ghz5));
328
329 + /* Extract cores power info info */
330 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
331 + o = pwr_info_offset[i];
332 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
333 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
334 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
335 + SSB_SPROM8_2G_MAXP, 0);
336 +
337 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
338 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
339 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
340 +
341 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
342 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
343 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
344 + SSB_SPROM8_5G_MAXP, 0);
345 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
346 + SSB_SPROM8_5GH_MAXP, 0);
347 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
348 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
349 +
350 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
351 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
352 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
353 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
354 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
355 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
356 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
357 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
358 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
359 + }
360 +
361 + /* Extract FEM info */
362 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
363 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
364 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
365 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
366 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
367 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
368 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
369 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
370 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
371 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
372 +
373 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
374 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
375 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
376 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
377 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
378 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
379 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
380 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
381 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
382 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
383 +
384 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
385 + SSB_SPROM8_LEDDC_ON_SHIFT);
386 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
387 + SSB_SPROM8_LEDDC_OFF_SHIFT);
388 +
389 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
390 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
391 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
392 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
393 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
394 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
395 +
396 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
397 +
398 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
399 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
400 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
401 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
402 +
403 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
404 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
405 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
406 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
407 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
408 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
409 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
410 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
411 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
412 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
413 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
414 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
415 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
416 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
417 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
418 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
419 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
420 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
421 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
422 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
423 +
424 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
425 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
426 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
427 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
428 +
429 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
430 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
431 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
432 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
433 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
434 + SSB_SPROM8_TEMPDELTA_PHYCAL,
435 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
436 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
437 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
438 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
439 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
440 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
441 sprom_extract_r458(out, in);
442
443 /* TODO - get remaining rev 8 stuff needed */
444 @@ -736,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
445 {
446 bi->vendor = bus->host_pci->subsystem_vendor;
447 bi->type = bus->host_pci->subsystem_device;
448 - bi->rev = bus->host_pci->revision;
449 }
450
451 int ssb_pci_get_invariants(struct ssb_bus *bus,
452 --- a/drivers/ssb/pcmcia.c
453 +++ b/drivers/ssb/pcmcia.c
454 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
455 case SSB_PCMCIA_CIS_ANTGAIN:
456 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
457 "antg tpl size");
458 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
459 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
460 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
461 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
462 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
463 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
464 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
465 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
466 + sprom->antenna_gain.a0 = tuple->TupleData[1];
467 + sprom->antenna_gain.a1 = tuple->TupleData[1];
468 + sprom->antenna_gain.a2 = tuple->TupleData[1];
469 + sprom->antenna_gain.a3 = tuple->TupleData[1];
470 break;
471 case SSB_PCMCIA_CIS_BFLAGS:
472 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
473 --- a/drivers/ssb/scan.c
474 +++ b/drivers/ssb/scan.c
475 @@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
476 bus->chip_package = 0;
477 }
478 }
479 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
480 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
481 + bus->chip_package);
482 if (!bus->nr_devices)
483 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
484 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
485 --- a/drivers/ssb/sdio.c
486 +++ b/drivers/ssb/sdio.c
487 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
488 case SSB_SDIO_CIS_ANTGAIN:
489 GOTO_ERROR_ON(tuple->size != 2,
490 "antg tpl size");
491 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
492 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
493 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
494 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
495 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
496 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
497 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
498 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
499 + sprom->antenna_gain.a0 = tuple->data[1];
500 + sprom->antenna_gain.a1 = tuple->data[1];
501 + sprom->antenna_gain.a2 = tuple->data[1];
502 + sprom->antenna_gain.a3 = tuple->data[1];
503 break;
504 case SSB_SDIO_CIS_BFLAGS:
505 GOTO_ERROR_ON((tuple->size != 3) &&
506 --- a/drivers/ssb/ssb_private.h
507 +++ b/drivers/ssb/ssb_private.h
508 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
509 }
510 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
511
512 +/* driver_chipcommon_pmu.c */
513 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
514 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
515 +
516 #endif /* LINUX_SSB_PRIVATE_H_ */
517 --- a/include/linux/ssb/ssb.h
518 +++ b/include/linux/ssb/ssb.h
519 @@ -16,6 +16,12 @@ struct pcmcia_device;
520 struct ssb_bus;
521 struct ssb_driver;
522
523 +struct ssb_sprom_core_pwr_info {
524 + u8 itssi_2g, itssi_5g;
525 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
526 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
527 +};
528 +
529 struct ssb_sprom {
530 u8 revision;
531 u8 il0mac[6]; /* MAC address for 802.11b/g */
532 @@ -26,9 +32,12 @@ struct ssb_sprom {
533 u8 et0mdcport; /* MDIO for enet0 */
534 u8 et1mdcport; /* MDIO for enet1 */
535 u16 board_rev; /* Board revision number from SPROM. */
536 + u16 board_num; /* Board number from SPROM. */
537 + u16 board_type; /* Board type from SPROM. */
538 u8 country_code; /* Country Code */
539 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
540 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
541 + char alpha2[2]; /* Country Code as two chars like EU or US */
542 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
543 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
544 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
545 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
546 u16 pa0b0;
547 @@ -47,10 +56,10 @@ struct ssb_sprom {
548 u8 gpio1; /* GPIO pin 1 */
549 u8 gpio2; /* GPIO pin 2 */
550 u8 gpio3; /* GPIO pin 3 */
551 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
552 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
553 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
554 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
555 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
556 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
557 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
558 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
559 u8 itssi_a; /* Idle TSSI Target for A-PHY */
560 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
561 u8 tri2g; /* 2.4GHz TX isolation */
562 @@ -61,8 +70,8 @@ struct ssb_sprom {
563 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
564 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
565 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
566 - u8 rxpo2g; /* 2GHz RX power offset */
567 - u8 rxpo5g; /* 5GHz RX power offset */
568 + s8 rxpo2g; /* 2GHz RX power offset */
569 + s8 rxpo5g; /* 5GHz RX power offset */
570 u8 rssisav2g; /* 2GHz RSSI params */
571 u8 rssismc2g;
572 u8 rssismf2g;
573 @@ -82,26 +91,103 @@ struct ssb_sprom {
574 u16 boardflags2_hi; /* Board flags (bits 48-63) */
575 /* TODO store board flags in a single u64 */
576
577 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
578 +
579 /* Antenna gain values for up to 4 antennas
580 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
581 * loss in the connectors is bigger than the gain. */
582 struct {
583 - struct {
584 - s8 a0, a1, a2, a3;
585 - } ghz24; /* 2.4GHz band */
586 - struct {
587 - s8 a0, a1, a2, a3;
588 - } ghz5; /* 5GHz band */
589 + s8 a0, a1, a2, a3;
590 } antenna_gain;
591
592 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
593 + struct {
594 + struct {
595 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
596 + } ghz2;
597 + struct {
598 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
599 + } ghz5;
600 + } fem;
601 +
602 + u16 mcs2gpo[8];
603 + u16 mcs5gpo[8];
604 + u16 mcs5glpo[8];
605 + u16 mcs5ghpo[8];
606 + u8 opo;
607 +
608 + u8 rxgainerr2ga[3];
609 + u8 rxgainerr5gla[3];
610 + u8 rxgainerr5gma[3];
611 + u8 rxgainerr5gha[3];
612 + u8 rxgainerr5gua[3];
613 +
614 + u8 noiselvl2ga[3];
615 + u8 noiselvl5gla[3];
616 + u8 noiselvl5gma[3];
617 + u8 noiselvl5gha[3];
618 + u8 noiselvl5gua[3];
619 +
620 + u8 regrev;
621 + u8 txchain;
622 + u8 rxchain;
623 + u8 antswitch;
624 + u16 cddpo;
625 + u16 stbcpo;
626 + u16 bw40po;
627 + u16 bwduppo;
628 +
629 + u8 tempthresh;
630 + u8 tempoffset;
631 + u16 rawtempsense;
632 + u8 measpower;
633 + u8 tempsense_slope;
634 + u8 tempcorrx;
635 + u8 tempsense_option;
636 + u8 freqoffset_corr;
637 + u8 iqcal_swp_dis;
638 + u8 hw_iqcal_en;
639 + u8 elna2g;
640 + u8 elna5g;
641 + u8 phycal_tempdelta;
642 + u8 temps_period;
643 + u8 temps_hysteresis;
644 + u8 measpower1;
645 + u8 measpower2;
646 + u8 pcieingress_war;
647 +
648 + /* power per rate from sromrev 9 */
649 + u16 cckbw202gpo;
650 + u16 cckbw20ul2gpo;
651 + u32 legofdmbw202gpo;
652 + u32 legofdmbw20ul2gpo;
653 + u32 legofdmbw205glpo;
654 + u32 legofdmbw20ul5glpo;
655 + u32 legofdmbw205gmpo;
656 + u32 legofdmbw20ul5gmpo;
657 + u32 legofdmbw205ghpo;
658 + u32 legofdmbw20ul5ghpo;
659 + u32 mcsbw202gpo;
660 + u32 mcsbw20ul2gpo;
661 + u32 mcsbw402gpo;
662 + u32 mcsbw205glpo;
663 + u32 mcsbw20ul5glpo;
664 + u32 mcsbw405glpo;
665 + u32 mcsbw205gmpo;
666 + u32 mcsbw20ul5gmpo;
667 + u32 mcsbw405gmpo;
668 + u32 mcsbw205ghpo;
669 + u32 mcsbw20ul5ghpo;
670 + u32 mcsbw405ghpo;
671 + u16 mcs32po;
672 + u16 legofdm40duppo;
673 + u8 sar2g;
674 + u8 sar5g;
675 };
676
677 /* Information about the PCB the circuitry is soldered on. */
678 struct ssb_boardinfo {
679 u16 vendor;
680 u16 type;
681 - u8 rev;
682 };
683
684
685 --- a/include/linux/ssb/ssb_driver_gige.h
686 +++ b/include/linux/ssb/ssb_driver_gige.h
687 @@ -2,6 +2,7 @@
688 #define LINUX_SSB_DRIVER_GIGE_H_
689
690 #include <linux/ssb/ssb.h>
691 +#include <linux/bug.h>
692 #include <linux/pci.h>
693 #include <linux/spinlock.h>
694
695 --- a/include/linux/ssb/ssb_regs.h
696 +++ b/include/linux/ssb/ssb_regs.h
697 @@ -228,6 +228,7 @@
698 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
699 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
700 #define SSB_SPROM1_AGAIN_A_SHIFT 8
701 +#define SSB_SPROM1_CCODE 0x0076
702
703 /* SPROM Revision 2 (inherits from rev 1) */
704 #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
705 @@ -267,6 +268,7 @@
706 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
707
708 /* SPROM Revision 4 */
709 +#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
710 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
711 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
712 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
713 @@ -389,6 +391,11 @@
714 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
715 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
716 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
717 +#define SSB_SPROM8_LEDDC 0x009A
718 +#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
719 +#define SSB_SPROM8_LEDDC_ON_SHIFT 8
720 +#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
721 +#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
722 #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
723 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
724 #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
725 @@ -404,6 +411,13 @@
726 #define SSB_SPROM8_AGAIN2_SHIFT 0
727 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
728 #define SSB_SPROM8_AGAIN3_SHIFT 8
729 +#define SSB_SPROM8_TXRXC 0x00A2
730 +#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
731 +#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
732 +#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
733 +#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
734 +#define SSB_SPROM8_TXRXC_SWITCH 0xff00
735 +#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
736 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
737 #define SSB_SPROM8_RSSISMF2G 0x000F
738 #define SSB_SPROM8_RSSISMC2G 0x00F0
739 @@ -430,8 +444,87 @@
740 #define SSB_SPROM8_TRI5GH_SHIFT 8
741 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
742 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
743 +#define SSB_SPROM8_RXPO2G_SHIFT 0
744 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
745 #define SSB_SPROM8_RXPO5G_SHIFT 8
746 +#define SSB_SPROM8_FEM2G 0x00AE
747 +#define SSB_SPROM8_FEM5G 0x00B0
748 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
749 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
750 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
751 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
752 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
753 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
754 +#define SSB_SROM8_FEM_TR_ISO 0x0700
755 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
756 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
757 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
758 +#define SSB_SPROM8_THERMAL 0x00B2
759 +#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
760 +#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
761 +#define SSB_SPROM8_THERMAL_TRESH 0xff00
762 +#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
763 +/* Temp sense related entries */
764 +#define SSB_SPROM8_RAWTS 0x00B4
765 +#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
766 +#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
767 +#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
768 +#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
769 +#define SSB_SPROM8_OPT_CORRX 0x00B6
770 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
771 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
772 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
773 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
774 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
775 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
776 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
777 +#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
778 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
779 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
780 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
781 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
782 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
783 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
784 +#define SSB_SPROM8_TEMPDELTA 0x00BA
785 +#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
786 +#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
787 +#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
788 +#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
789 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
790 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
791 +
792 +/* There are 4 blocks with power info sharing the same layout */
793 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
794 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
795 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
796 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
797 +
798 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
799 +#define SSB_SPROM8_2G_MAXP 0x00FF
800 +#define SSB_SPROM8_2G_ITSSI 0xFF00
801 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
802 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
803 +#define SSB_SROM8_2G_PA_1 0x04
804 +#define SSB_SROM8_2G_PA_2 0x06
805 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
806 +#define SSB_SPROM8_5G_MAXP 0x00FF
807 +#define SSB_SPROM8_5G_ITSSI 0xFF00
808 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
809 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
810 +#define SSB_SPROM8_5GH_MAXP 0x00FF
811 +#define SSB_SPROM8_5GL_MAXP 0xFF00
812 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
813 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
814 +#define SSB_SROM8_5G_PA_1 0x0E
815 +#define SSB_SROM8_5G_PA_2 0x10
816 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
817 +#define SSB_SROM8_5GL_PA_1 0x14
818 +#define SSB_SROM8_5GL_PA_2 0x16
819 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
820 +#define SSB_SROM8_5GH_PA_1 0x1A
821 +#define SSB_SROM8_5GH_PA_2 0x1C
822 +
823 +/* TODO: Make it deprecated */
824 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
825 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
826 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
827 @@ -456,12 +549,23 @@
828 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
829 #define SSB_SPROM8_PA1HIB1 0x00DA
830 #define SSB_SPROM8_PA1HIB2 0x00DC
831 +
832 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
833 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
834 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
835 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
836 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
837
838 +#define SSB_SPROM8_2G_MCSPO 0x0152
839 +#define SSB_SPROM8_5G_MCSPO 0x0162
840 +#define SSB_SPROM8_5GL_MCSPO 0x0172
841 +#define SSB_SPROM8_5GH_MCSPO 0x0182
842 +
843 +#define SSB_SPROM8_CDDPO 0x0192
844 +#define SSB_SPROM8_STBCPO 0x0194
845 +#define SSB_SPROM8_BW40PO 0x0196
846 +#define SSB_SPROM8_BWDUPPO 0x0198
847 +
848 /* Values for boardflags_lo read from SPROM */
849 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
850 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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