kernel: update linux 3.2 to 3.2.12
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.2 / 994-mpcore_wdt_fix_timer_mode_setup.patch
1 Allow watchdog to set its iterrupt as pending when it is configured
2 for timer mode (in other words, allow emitting interrupt).
3 Also add macros for all Watchdog Control Register flags.
4
5 Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
6 ---
7 arch/arm/include/asm/smp_twd.h | 6 ++++++
8 drivers/watchdog/mpcore_wdt.c | 15 +++++++++++----
9 2 files changed, 17 insertions(+), 4 deletions(-)
10
11 --- a/arch/arm/include/asm/smp_twd.h
12 +++ b/arch/arm/include/asm/smp_twd.h
13 @@ -18,6 +18,12 @@
14 #define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
15 #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
16
17 +#define TWD_WDOG_CONTROL_ENABLE (1 << 0)
18 +#define TWD_WDOG_CONTROL_PERIODIC (1 << 1)
19 +#define TWD_WDOG_CONTROL_IT_ENABLE (1 << 2)
20 +#define TWD_WDOG_CONTROL_TIMER_MODE (0 << 3)
21 +#define TWD_WDOG_CONTROL_WATCHDOG_MODE (1 << 3)
22 +
23 struct clock_event_device;
24
25 extern void __iomem *twd_base;
26 --- a/drivers/watchdog/mpcore_wdt.c
27 +++ b/drivers/watchdog/mpcore_wdt.c
28 @@ -118,18 +118,25 @@ static void mpcore_wdt_stop(struct mpcor
29
30 static void mpcore_wdt_start(struct mpcore_wdt *wdt)
31 {
32 + u32 mode;
33 +
34 dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n");
35
36 /* This loads the count register but does NOT start the count yet */
37 mpcore_wdt_keepalive(wdt);
38
39 + /* Setup watchdog - prescale=256, enable=1 */
40 + mode = (255 << 8) | TWD_WDOG_CONTROL_ENABLE;
41 +
42 if (mpcore_noboot) {
43 - /* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
44 - writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
45 + /* timer mode, send interrupt */
46 + mode |= TWD_WDOG_CONTROL_TIMER_MODE |
47 + TWD_WDOG_CONTROL_IT_ENABLE;
48 } else {
49 - /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
50 - writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
51 + /* watchdog mode */
52 + mode |= TWD_WDOG_CONTROL_WATCHDOG_MODE;
53 }
54 + writel(mode, wdt->base + TWD_WDOG_CONTROL);
55 }
56
57 static int mpcore_wdt_set_heartbeat(int t)