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kernel: update bcma and ssb to wireless-testing/master master-2013-07-03
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/arch/mips/bcm47xx/gpio.c
13 +++ b/arch/mips/bcm47xx/gpio.c
14 @@ -94,7 +94,7 @@ int gpio_to_irq(unsigned gpio)
15 #endif
16 #ifdef CONFIG_BCM47XX_BCMA
17 case BCM47XX_BUS_TYPE_BCMA:
18 - return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2;
19 + return bcma_core_irq(bcm47xx_bus.bcma.bus.drv_cc.core);
20 #endif
21 }
22 return -EINVAL;
23 --- a/drivers/bcma/Kconfig
24 +++ b/drivers/bcma/Kconfig
25 @@ -26,10 +26,11 @@ config BCMA_HOST_PCI_POSSIBLE
26 config BCMA_HOST_PCI
27 bool "Support for BCMA on PCI-host bus"
28 depends on BCMA_HOST_PCI_POSSIBLE
29 + default y
30
31 config BCMA_DRIVER_PCI_HOSTMODE
32 bool "Driver for PCI core working in hostmode"
33 - depends on BCMA && MIPS
34 + depends on BCMA && MIPS && BCMA_HOST_PCI
35 help
36 PCI core hostmode operation (external PCI bus).
37
38 @@ -46,6 +47,23 @@ config BCMA_DRIVER_MIPS
39
40 If unsure, say N
41
42 +config BCMA_DRIVER_GMAC_CMN
43 + bool "BCMA Broadcom GBIT MAC COMMON core driver"
44 + depends on BCMA
45 + help
46 + Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
47 + specific Advanced Microcontroller Bus.
48 +
49 + If unsure, say N
50 +
51 +config BCMA_DRIVER_GPIO
52 + bool "BCMA GPIO driver"
53 + depends on BCMA && GPIOLIB
54 + help
55 + Driver to provide access to the GPIO pins of the bcma bus.
56 +
57 + If unsure, say N
58 +
59 config BCMA_DEBUG
60 bool "BCMA debugging"
61 depends on BCMA
62 --- a/drivers/bcma/Makefile
63 +++ b/drivers/bcma/Makefile
64 @@ -3,6 +3,8 @@ bcma-y += driver_chipcommon.o driver
65 bcma-y += driver_pci.o
66 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
67 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
68 +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
69 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
70 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
71 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
72 obj-$(CONFIG_BCMA) += bcma.o
73 --- a/drivers/bcma/bcma_private.h
74 +++ b/drivers/bcma/bcma_private.h
75 @@ -10,10 +10,21 @@
76
77 #define BCMA_CORE_SIZE 0x1000
78
79 +#define bcma_err(bus, fmt, ...) \
80 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
81 +#define bcma_warn(bus, fmt, ...) \
82 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
83 +#define bcma_info(bus, fmt, ...) \
84 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
85 +#define bcma_debug(bus, fmt, ...) \
86 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
87 +
88 struct bcma_bus;
89
90 /* main.c */
91 -int bcma_bus_register(struct bcma_bus *bus);
92 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
93 + int timeout);
94 +int __devinit bcma_bus_register(struct bcma_bus *bus);
95 void bcma_bus_unregister(struct bcma_bus *bus);
96 int __init bcma_bus_early_register(struct bcma_bus *bus,
97 struct bcma_device *core_cc,
98 @@ -22,6 +33,8 @@ int __init bcma_bus_early_register(struc
99 int bcma_bus_suspend(struct bcma_bus *bus);
100 int bcma_bus_resume(struct bcma_bus *bus);
101 #endif
102 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
103 + u8 unit);
104
105 /* scan.c */
106 int bcma_bus_scan(struct bcma_bus *bus);
107 @@ -39,8 +52,8 @@ void bcma_chipco_serial_init(struct bcma
108 #endif /* CONFIG_BCMA_DRIVER_MIPS */
109
110 /* driver_chipcommon_pmu.c */
111 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
112 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
113 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
114 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
115
116 #ifdef CONFIG_BCMA_HOST_PCI
117 /* host_pci.c */
118 @@ -48,8 +61,29 @@ extern int __init bcma_host_pci_init(voi
119 extern void __exit bcma_host_pci_exit(void);
120 #endif /* CONFIG_BCMA_HOST_PCI */
121
122 +/* driver_pci.c */
123 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
124 +
125 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
126 +
127 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
128 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
129 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
130 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
131 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
132
133 +#ifdef CONFIG_BCMA_DRIVER_GPIO
134 +/* driver_gpio.c */
135 +int bcma_gpio_init(struct bcma_drv_cc *cc);
136 +int bcma_gpio_unregister(struct bcma_drv_cc *cc);
137 +#else
138 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
139 +{
140 + return -ENOTSUPP;
141 +}
142 +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
143 +{
144 + return 0;
145 +}
146 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
147 +
148 #endif
149 --- a/drivers/bcma/core.c
150 +++ b/drivers/bcma/core.c
151 @@ -9,6 +9,25 @@
152 #include <linux/export.h>
153 #include <linux/bcma/bcma.h>
154
155 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
156 + u32 value, int timeout)
157 +{
158 + unsigned long deadline = jiffies + timeout;
159 + u32 val;
160 +
161 + do {
162 + val = bcma_aread32(core, reg);
163 + if ((val & mask) == value)
164 + return true;
165 + cpu_relax();
166 + udelay(10);
167 + } while (!time_after_eq(jiffies, deadline));
168 +
169 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
170 +
171 + return false;
172 +}
173 +
174 bool bcma_core_is_enabled(struct bcma_device *core)
175 {
176 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
177 @@ -25,12 +44,15 @@ void bcma_core_disable(struct bcma_devic
178 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
179 return;
180
181 - bcma_awrite32(core, BCMA_IOCTL, flags);
182 - bcma_aread32(core, BCMA_IOCTL);
183 - udelay(10);
184 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
185
186 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
187 + bcma_aread32(core, BCMA_RESET_CTL);
188 udelay(1);
189 +
190 + bcma_awrite32(core, BCMA_IOCTL, flags);
191 + bcma_aread32(core, BCMA_IOCTL);
192 + udelay(10);
193 }
194 EXPORT_SYMBOL_GPL(bcma_core_disable);
195
196 @@ -42,6 +64,7 @@ int bcma_core_enable(struct bcma_device
197 bcma_aread32(core, BCMA_IOCTL);
198
199 bcma_awrite32(core, BCMA_RESET_CTL, 0);
200 + bcma_aread32(core, BCMA_RESET_CTL);
201 udelay(1);
202
203 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
204 @@ -64,7 +87,7 @@ void bcma_core_set_clockmode(struct bcma
205 switch (clkmode) {
206 case BCMA_CLKMODE_FAST:
207 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
208 - udelay(64);
209 + usleep_range(64, 300);
210 for (i = 0; i < 1500; i++) {
211 if (bcma_read32(core, BCMA_CLKCTLST) &
212 BCMA_CLKCTLST_HAVEHT) {
213 @@ -74,10 +97,10 @@ void bcma_core_set_clockmode(struct bcma
214 udelay(10);
215 }
216 if (i)
217 - pr_err("HT force timeout\n");
218 + bcma_err(core->bus, "HT force timeout\n");
219 break;
220 case BCMA_CLKMODE_DYNAMIC:
221 - pr_warn("Dynamic clockmode not supported yet!\n");
222 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
223 break;
224 }
225 }
226 @@ -101,9 +124,15 @@ void bcma_core_pll_ctl(struct bcma_devic
227 udelay(10);
228 }
229 if (i)
230 - pr_err("PLL enable timeout\n");
231 + bcma_err(core->bus, "PLL enable timeout\n");
232 } else {
233 - pr_warn("Disabling PLL not supported yet!\n");
234 + /*
235 + * Mask the PLL but don't wait for it to be disabled. PLL may be
236 + * shared between cores and will be still up if there is another
237 + * core using it.
238 + */
239 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
240 + bcma_read32(core, BCMA_CLKCTLST);
241 }
242 }
243 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
244 @@ -119,8 +148,8 @@ u32 bcma_core_dma_translation(struct bcm
245 else
246 return BCMA_DMA_TRANSLATION_DMA32_CMT;
247 default:
248 - pr_err("DMA translation unknown for host %d\n",
249 - core->bus->hosttype);
250 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
251 + core->bus->hosttype);
252 }
253 return BCMA_DMA_TRANSLATION_NONE;
254 }
255 --- a/drivers/bcma/driver_chipcommon.c
256 +++ b/drivers/bcma/driver_chipcommon.c
257 @@ -4,12 +4,15 @@
258 *
259 * Copyright 2005, Broadcom Corporation
260 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
261 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
262 *
263 * Licensed under the GNU/GPL. See COPYING for details.
264 */
265
266 #include "bcma_private.h"
267 +#include <linux/bcm47xx_wdt.h>
268 #include <linux/export.h>
269 +#include <linux/platform_device.h>
270 #include <linux/bcma/bcma.h>
271
272 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
273 @@ -22,29 +25,136 @@ static inline u32 bcma_cc_write32_masked
274 return value;
275 }
276
277 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
278 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
279 {
280 - u32 leddc_on = 10;
281 - u32 leddc_off = 90;
282 + if (cc->capabilities & BCMA_CC_CAP_PMU)
283 + return bcma_pmu_get_alp_clock(cc);
284
285 - if (cc->setup_done)
286 + return 20000000;
287 +}
288 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
289 +
290 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
291 +{
292 + struct bcma_bus *bus = cc->core->bus;
293 + u32 nb;
294 +
295 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
296 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
297 + nb = 32;
298 + else if (cc->core->id.rev < 26)
299 + nb = 16;
300 + else
301 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
302 + } else {
303 + nb = 28;
304 + }
305 + if (nb == 32)
306 + return 0xffffffff;
307 + else
308 + return (1 << nb) - 1;
309 +}
310 +
311 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
312 + u32 ticks)
313 +{
314 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
315 +
316 + return bcma_chipco_watchdog_timer_set(cc, ticks);
317 +}
318 +
319 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
320 + u32 ms)
321 +{
322 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
323 + u32 ticks;
324 +
325 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
326 + return ticks / cc->ticks_per_ms;
327 +}
328 +
329 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
330 +{
331 + struct bcma_bus *bus = cc->core->bus;
332 +
333 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
334 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
335 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
336 + return bcma_chipco_get_alp_clock(cc) / 4000;
337 + else
338 + /* based on 32KHz ILP clock */
339 + return 32;
340 + } else {
341 + return bcma_chipco_get_alp_clock(cc) / 1000;
342 + }
343 +}
344 +
345 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
346 +{
347 + struct bcm47xx_wdt wdt = {};
348 + struct platform_device *pdev;
349 +
350 + wdt.driver_data = cc;
351 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
352 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
353 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
354 +
355 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
356 + cc->core->bus->num, &wdt,
357 + sizeof(wdt));
358 + if (IS_ERR(pdev))
359 + return PTR_ERR(pdev);
360 +
361 + cc->watchdog = pdev;
362 +
363 + return 0;
364 +}
365 +
366 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
367 +{
368 + if (cc->early_setup_done)
369 return;
370
371 + spin_lock_init(&cc->gpio_lock);
372 +
373 if (cc->core->id.rev >= 11)
374 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
375 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
376 if (cc->core->id.rev >= 35)
377 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
378
379 + if (cc->capabilities & BCMA_CC_CAP_PMU)
380 + bcma_pmu_early_init(cc);
381 +
382 + cc->early_setup_done = true;
383 +}
384 +
385 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
386 +{
387 + u32 leddc_on = 10;
388 + u32 leddc_off = 90;
389 +
390 + if (cc->setup_done)
391 + return;
392 +
393 + bcma_core_chipcommon_early_init(cc);
394 +
395 if (cc->core->id.rev >= 20) {
396 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
397 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
398 + u32 pullup = 0, pulldown = 0;
399 +
400 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
401 + pullup = 0x402e0;
402 + pulldown = 0x20500;
403 + }
404 +
405 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
406 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
407 }
408
409 if (cc->capabilities & BCMA_CC_CAP_PMU)
410 bcma_pmu_init(cc);
411 if (cc->capabilities & BCMA_CC_CAP_PCTL)
412 - pr_err("Power control not implemented!\n");
413 + bcma_err(cc->core->bus, "Power control not implemented!\n");
414
415 if (cc->core->id.rev >= 16) {
416 if (cc->core->bus->sprom.leddc_on_time &&
417 @@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
418 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
419 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
420 }
421 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
422
423 cc->setup_done = true;
424 }
425
426 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
427 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
428 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
429 {
430 - /* instant NMI */
431 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
432 + u32 maxt;
433 + enum bcma_clkmode clkmode;
434 +
435 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
436 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
437 + if (ticks == 1)
438 + ticks = 2;
439 + else if (ticks > maxt)
440 + ticks = maxt;
441 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
442 + } else {
443 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
444 + bcma_core_set_clockmode(cc->core, clkmode);
445 + if (ticks > maxt)
446 + ticks = maxt;
447 + /* instant NMI */
448 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
449 + }
450 + return ticks;
451 }
452
453 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
454 @@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
455
456 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
457 {
458 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
459 + unsigned long flags;
460 + u32 res;
461 +
462 + spin_lock_irqsave(&cc->gpio_lock, flags);
463 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
464 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
465 +
466 + return res;
467 }
468 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
469
470 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
471 {
472 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
473 + unsigned long flags;
474 + u32 res;
475 +
476 + spin_lock_irqsave(&cc->gpio_lock, flags);
477 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
478 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
479 +
480 + return res;
481 }
482 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
483
484 +/*
485 + * If the bit is set to 0, chipcommon controlls this GPIO,
486 + * if the bit is set to 1, it is used by some part of the chip and not our code.
487 + */
488 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
489 {
490 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
491 + unsigned long flags;
492 + u32 res;
493 +
494 + spin_lock_irqsave(&cc->gpio_lock, flags);
495 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
496 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
497 +
498 + return res;
499 }
500 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
501
502 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
503 {
504 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
505 + unsigned long flags;
506 + u32 res;
507 +
508 + spin_lock_irqsave(&cc->gpio_lock, flags);
509 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
510 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
511 +
512 + return res;
513 }
514
515 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
516 {
517 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
518 + unsigned long flags;
519 + u32 res;
520 +
521 + spin_lock_irqsave(&cc->gpio_lock, flags);
522 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
523 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
524 +
525 + return res;
526 +}
527 +
528 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
529 +{
530 + unsigned long flags;
531 + u32 res;
532 +
533 + if (cc->core->id.rev < 20)
534 + return 0;
535 +
536 + spin_lock_irqsave(&cc->gpio_lock, flags);
537 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
538 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
539 +
540 + return res;
541 +}
542 +
543 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
544 +{
545 + unsigned long flags;
546 + u32 res;
547 +
548 + if (cc->core->id.rev < 20)
549 + return 0;
550 +
551 + spin_lock_irqsave(&cc->gpio_lock, flags);
552 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
553 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
554 +
555 + return res;
556 }
557
558 #ifdef CONFIG_BCMA_DRIVER_MIPS
559 @@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
560 struct bcma_serial_port *ports = cc->serial_ports;
561
562 if (ccrev >= 11 && ccrev != 15) {
563 - /* Fixed ALP clock */
564 - baud_base = bcma_pmu_alp_clock(cc);
565 + baud_base = bcma_chipco_get_alp_clock(cc);
566 if (ccrev >= 21) {
567 /* Turn off UART clock before switching clocksource. */
568 bcma_cc_write32(cc, BCMA_CC_CORECTL,
569 @@ -137,12 +335,11 @@ void bcma_chipco_serial_init(struct bcma
570 | BCMA_CC_CORECTL_UARTCLKEN);
571 }
572 } else {
573 - pr_err("serial not supported on this device ccrev: 0x%x\n",
574 - ccrev);
575 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
576 return;
577 }
578
579 - irq = bcma_core_mips_irq(cc->core);
580 + irq = bcma_core_irq(cc->core);
581
582 /* Determine the registers of the UARTs */
583 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
584 --- a/drivers/bcma/driver_chipcommon_pmu.c
585 +++ b/drivers/bcma/driver_chipcommon_pmu.c
586 @@ -3,7 +3,8 @@
587 * ChipCommon Power Management Unit driver
588 *
589 * Copyright 2009, Michael Buesch <m@bues.ch>
590 - * Copyright 2007, Broadcom Corporation
591 + * Copyright 2007, 2011, Broadcom Corporation
592 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
593 *
594 * Licensed under the GNU/GPL. See COPYING for details.
595 */
596 @@ -12,12 +13,13 @@
597 #include <linux/export.h>
598 #include <linux/bcma/bcma.h>
599
600 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
601 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
602 {
603 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
604 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
605 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
606 }
607 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
608
609 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
610 {
611 @@ -54,19 +56,106 @@ void bcma_chipco_regctl_maskset(struct b
612 }
613 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
614
615 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
616 +{
617 + u32 ilp_ctl, alp_hz;
618 +
619 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
620 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
621 + return 0;
622 +
623 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
624 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
625 + usleep_range(1000, 2000);
626 +
627 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
628 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
629 +
630 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
631 +
632 + alp_hz = ilp_ctl * 32768 / 4;
633 + return (alp_hz + 50000) / 100000 * 100;
634 +}
635 +
636 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
637 +{
638 + struct bcma_bus *bus = cc->core->bus;
639 + u32 freq_tgt_target = 0, freq_tgt_current;
640 + u32 pll0, mask;
641 +
642 + switch (bus->chipinfo.id) {
643 + case BCMA_CHIP_ID_BCM43142:
644 + /* pmu2_xtaltab0_adfll_485 */
645 + switch (xtalfreq) {
646 + case 12000:
647 + freq_tgt_target = 0x50D52;
648 + break;
649 + case 20000:
650 + freq_tgt_target = 0x307FE;
651 + break;
652 + case 26000:
653 + freq_tgt_target = 0x254EA;
654 + break;
655 + case 37400:
656 + freq_tgt_target = 0x19EF8;
657 + break;
658 + case 52000:
659 + freq_tgt_target = 0x12A75;
660 + break;
661 + }
662 + break;
663 + }
664 +
665 + if (!freq_tgt_target) {
666 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
667 + xtalfreq);
668 + return;
669 + }
670 +
671 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
672 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
673 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
674 +
675 + if (freq_tgt_current == freq_tgt_target) {
676 + bcma_debug(bus, "Target TGT frequency already set\n");
677 + return;
678 + }
679 +
680 + /* Turn off PLL */
681 + switch (bus->chipinfo.id) {
682 + case BCMA_CHIP_ID_BCM43142:
683 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
684 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
685 +
686 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
687 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
688 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
689 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
690 + break;
691 + }
692 +
693 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
694 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
695 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
696 +
697 + /* Flush */
698 + if (cc->pmu.rev >= 2)
699 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
700 +
701 + /* TODO: Do we need to update OTP? */
702 +}
703 +
704 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
705 {
706 struct bcma_bus *bus = cc->core->bus;
707 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
708
709 switch (bus->chipinfo.id) {
710 - case 0x4313:
711 - case 0x4331:
712 - case 43224:
713 - case 43225:
714 + case BCMA_CHIP_ID_BCM43142:
715 + if (xtalfreq == 0)
716 + xtalfreq = 20000;
717 + bcma_pmu2_pll_init0(cc, xtalfreq);
718 break;
719 - default:
720 - pr_err("PLL init unknown for device 0x%04X\n",
721 - bus->chipinfo.id);
722 }
723 }
724
725 @@ -76,16 +165,32 @@ static void bcma_pmu_resources_init(stru
726 u32 min_msk = 0, max_msk = 0;
727
728 switch (bus->chipinfo.id) {
729 - case 0x4313:
730 + case BCMA_CHIP_ID_BCM4313:
731 min_msk = 0x200D;
732 max_msk = 0xFFFF;
733 break;
734 - case 43224:
735 - case 43225:
736 + case BCMA_CHIP_ID_BCM43142:
737 + min_msk = BCMA_RES_4314_LPLDO_PU |
738 + BCMA_RES_4314_PMU_SLEEP_DIS |
739 + BCMA_RES_4314_PMU_BG_PU |
740 + BCMA_RES_4314_CBUCK_LPOM_PU |
741 + BCMA_RES_4314_CBUCK_PFM_PU |
742 + BCMA_RES_4314_CLDO_PU |
743 + BCMA_RES_4314_LPLDO2_LVM |
744 + BCMA_RES_4314_WL_PMU_PU |
745 + BCMA_RES_4314_LDO3P3_PU |
746 + BCMA_RES_4314_OTP_PU |
747 + BCMA_RES_4314_WL_PWRSW_PU |
748 + BCMA_RES_4314_LQ_AVAIL |
749 + BCMA_RES_4314_LOGIC_RET |
750 + BCMA_RES_4314_MEM_SLEEP |
751 + BCMA_RES_4314_MACPHY_RET |
752 + BCMA_RES_4314_WL_CORE_READY;
753 + max_msk = 0x3FFFFFFF;
754 break;
755 default:
756 - pr_err("PMU resource config unknown for device 0x%04X\n",
757 - bus->chipinfo.id);
758 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
759 + bus->chipinfo.id);
760 }
761
762 /* Set the resource masks. */
763 @@ -93,22 +198,12 @@ static void bcma_pmu_resources_init(stru
764 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
765 if (max_msk)
766 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
767 -}
768
769 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
770 -{
771 - struct bcma_bus *bus = cc->core->bus;
772 -
773 - switch (bus->chipinfo.id) {
774 - case 0x4313:
775 - case 0x4331:
776 - case 43224:
777 - case 43225:
778 - break;
779 - default:
780 - pr_err("PMU switch/regulators init unknown for device "
781 - "0x%04X\n", bus->chipinfo.id);
782 - }
783 + /*
784 + * Add some delay; allow resources to come up and settle.
785 + * Delay is required for SoC (early init).
786 + */
787 + mdelay(2);
788 }
789
790 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
791 @@ -122,51 +217,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
792 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
793 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
794 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
795 + else if (bus->chipinfo.rev > 0)
796 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
797 } else {
798 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
799 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
800 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
801 }
802 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
803 }
804
805 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
806 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
807 {
808 struct bcma_bus *bus = cc->core->bus;
809
810 switch (bus->chipinfo.id) {
811 - case 0x4313:
812 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
813 + case BCMA_CHIP_ID_BCM4313:
814 + /* enable 12 mA drive strenth for 4313 and set chipControl
815 + register bit 1 */
816 + bcma_chipco_chipctl_maskset(cc, 0,
817 + ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
818 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
819 break;
820 - case 0x4331:
821 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
822 + case BCMA_CHIP_ID_BCM4331:
823 + case BCMA_CHIP_ID_BCM43431:
824 + /* Ext PA lines must be enabled for tx on BCM4331 */
825 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
826 break;
827 - case 43224:
828 + case BCMA_CHIP_ID_BCM43224:
829 + case BCMA_CHIP_ID_BCM43421:
830 + /* enable 12 mA drive strenth for 43224 and set chipControl
831 + register bit 15 */
832 if (bus->chipinfo.rev == 0) {
833 - pr_err("Workarounds for 43224 rev 0 not fully "
834 - "implemented\n");
835 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
836 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
837 + ~BCMA_CCTRL_43224_GPIO_TOGGLE,
838 + BCMA_CCTRL_43224_GPIO_TOGGLE);
839 + bcma_chipco_chipctl_maskset(cc, 0,
840 + ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
841 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
842 } else {
843 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
844 + bcma_chipco_chipctl_maskset(cc, 0,
845 + ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
846 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
847 }
848 break;
849 - case 43225:
850 - break;
851 default:
852 - pr_err("Workarounds unknown for device 0x%04X\n",
853 - bus->chipinfo.id);
854 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
855 + bus->chipinfo.id);
856 }
857 }
858
859 -void bcma_pmu_init(struct bcma_drv_cc *cc)
860 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
861 {
862 u32 pmucap;
863
864 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
865 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
866
867 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
868 - pmucap);
869 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
870 + cc->pmu.rev, pmucap);
871 +}
872
873 +void bcma_pmu_init(struct bcma_drv_cc *cc)
874 +{
875 if (cc->pmu.rev == 1)
876 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
877 ~BCMA_CC_PMU_CTL_NOILPONW);
878 @@ -174,37 +287,48 @@ void bcma_pmu_init(struct bcma_drv_cc *c
879 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
880 BCMA_CC_PMU_CTL_NOILPONW);
881
882 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
883 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
884 -
885 bcma_pmu_pll_init(cc);
886 bcma_pmu_resources_init(cc);
887 - bcma_pmu_swreg_init(cc);
888 bcma_pmu_workarounds(cc);
889 }
890
891 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
892 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
893 {
894 struct bcma_bus *bus = cc->core->bus;
895
896 switch (bus->chipinfo.id) {
897 - case 0x4716:
898 - case 0x4748:
899 - case 47162:
900 - case 0x4313:
901 - case 0x5357:
902 - case 0x4749:
903 - case 53572:
904 + case BCMA_CHIP_ID_BCM4313:
905 + case BCMA_CHIP_ID_BCM43224:
906 + case BCMA_CHIP_ID_BCM43225:
907 + case BCMA_CHIP_ID_BCM43227:
908 + case BCMA_CHIP_ID_BCM43228:
909 + case BCMA_CHIP_ID_BCM4331:
910 + case BCMA_CHIP_ID_BCM43421:
911 + case BCMA_CHIP_ID_BCM43428:
912 + case BCMA_CHIP_ID_BCM43431:
913 + case BCMA_CHIP_ID_BCM4716:
914 + case BCMA_CHIP_ID_BCM47162:
915 + case BCMA_CHIP_ID_BCM4748:
916 + case BCMA_CHIP_ID_BCM4749:
917 + case BCMA_CHIP_ID_BCM5357:
918 + case BCMA_CHIP_ID_BCM53572:
919 + case BCMA_CHIP_ID_BCM6362:
920 /* always 20Mhz */
921 return 20000 * 1000;
922 - case 0x5356:
923 - case 0x5300:
924 + case BCMA_CHIP_ID_BCM4706:
925 + case BCMA_CHIP_ID_BCM5356:
926 /* always 25Mhz */
927 return 25000 * 1000;
928 + case BCMA_CHIP_ID_BCM43460:
929 + case BCMA_CHIP_ID_BCM4352:
930 + case BCMA_CHIP_ID_BCM4360:
931 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
932 + return 40000 * 1000;
933 + else
934 + return 20000 * 1000;
935 default:
936 - pr_warn("No ALP clock specified for %04X device, "
937 - "pmu rev. %d, using default %d Hz\n",
938 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
939 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
940 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
941 }
942 return BCMA_CC_PMU_ALP_CLOCK;
943 }
944 @@ -212,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
945 /* Find the output of the "m" pll divider given pll controls that start with
946 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
947 */
948 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
949 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
950 {
951 u32 tmp, div, ndiv, p1, p2, fc;
952 struct bcma_bus *bus = cc->core->bus;
953 @@ -221,7 +345,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
954
955 BUG_ON(!m || m > 4);
956
957 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
958 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
959 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
960 /* Detect failure in clock setting */
961 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
962 if (tmp & 0x40000)
963 @@ -240,60 +365,96 @@ static u32 bcma_pmu_clock(struct bcma_dr
964 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
965
966 /* Do calculation in Mhz */
967 - fc = bcma_pmu_alp_clock(cc) / 1000000;
968 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
969 fc = (p1 * ndiv * fc) / p2;
970
971 /* Return clock in Hertz */
972 return (fc / div) * 1000000;
973 }
974
975 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
976 +{
977 + u32 tmp, ndiv, p1div, p2div;
978 + u32 clock;
979 +
980 + BUG_ON(!m || m > 4);
981 +
982 + /* Get N, P1 and P2 dividers to determine CPU clock */
983 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
984 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
985 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
986 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
987 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
988 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
989 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
990 +
991 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
992 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
993 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
994 + clock = (25000000 / 4) * ndiv * p2div / p1div;
995 + else
996 + /* Fixed reference clock 25MHz and m = 2 */
997 + clock = (25000000 / 2) * ndiv * p2div / p1div;
998 +
999 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
1000 + clock = clock / 4;
1001 +
1002 + return clock;
1003 +}
1004 +
1005 /* query bus clock frequency for PMU-enabled chipcommon */
1006 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
1007 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
1008 {
1009 struct bcma_bus *bus = cc->core->bus;
1010
1011 switch (bus->chipinfo.id) {
1012 - case 0x4716:
1013 - case 0x4748:
1014 - case 47162:
1015 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
1016 - BCMA_CC_PMU5_MAINPLL_SSB);
1017 - case 0x5356:
1018 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
1019 - BCMA_CC_PMU5_MAINPLL_SSB);
1020 - case 0x5357:
1021 - case 0x4749:
1022 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
1023 - BCMA_CC_PMU5_MAINPLL_SSB);
1024 - case 0x5300:
1025 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
1026 - BCMA_CC_PMU5_MAINPLL_SSB);
1027 - case 53572:
1028 + case BCMA_CHIP_ID_BCM4716:
1029 + case BCMA_CHIP_ID_BCM4748:
1030 + case BCMA_CHIP_ID_BCM47162:
1031 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
1032 + BCMA_CC_PMU5_MAINPLL_SSB);
1033 + case BCMA_CHIP_ID_BCM5356:
1034 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
1035 + BCMA_CC_PMU5_MAINPLL_SSB);
1036 + case BCMA_CHIP_ID_BCM5357:
1037 + case BCMA_CHIP_ID_BCM4749:
1038 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
1039 + BCMA_CC_PMU5_MAINPLL_SSB);
1040 + case BCMA_CHIP_ID_BCM4706:
1041 + return bcma_pmu_pll_clock_bcm4706(cc,
1042 + BCMA_CC_PMU4706_MAINPLL_PLL0,
1043 + BCMA_CC_PMU5_MAINPLL_SSB);
1044 + case BCMA_CHIP_ID_BCM53572:
1045 return 75000000;
1046 default:
1047 - pr_warn("No backplane clock specified for %04X device, "
1048 - "pmu rev. %d, using default %d Hz\n",
1049 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
1050 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
1051 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
1052 }
1053 return BCMA_CC_PMU_HT_CLOCK;
1054 }
1055 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
1056
1057 /* query cpu clock frequency for PMU-enabled chipcommon */
1058 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
1059 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
1060 {
1061 struct bcma_bus *bus = cc->core->bus;
1062
1063 - if (bus->chipinfo.id == 53572)
1064 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
1065 return 300000000;
1066
1067 + /* New PMUs can have different clock for bus and CPU */
1068 if (cc->pmu.rev >= 5) {
1069 u32 pll;
1070 switch (bus->chipinfo.id) {
1071 - case 0x5356:
1072 + case BCMA_CHIP_ID_BCM4706:
1073 + return bcma_pmu_pll_clock_bcm4706(cc,
1074 + BCMA_CC_PMU4706_MAINPLL_PLL0,
1075 + BCMA_CC_PMU5_MAINPLL_CPU);
1076 + case BCMA_CHIP_ID_BCM5356:
1077 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
1078 break;
1079 - case 0x5357:
1080 - case 0x4749:
1081 + case BCMA_CHIP_ID_BCM5357:
1082 + case BCMA_CHIP_ID_BCM4749:
1083 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
1084 break;
1085 default:
1086 @@ -301,10 +462,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
1087 break;
1088 }
1089
1090 - /* TODO: if (bus->chipinfo.id == 0x5300)
1091 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
1092 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
1093 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
1094 + }
1095 +
1096 + /* On old PMUs CPU has the same clock as the bus */
1097 + return bcma_pmu_get_bus_clock(cc);
1098 +}
1099 +
1100 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
1101 + u32 value)
1102 +{
1103 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
1104 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
1105 +}
1106 +
1107 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
1108 +{
1109 + u32 tmp = 0;
1110 + u8 phypll_offset = 0;
1111 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
1112 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
1113 + struct bcma_bus *bus = cc->core->bus;
1114 +
1115 + switch (bus->chipinfo.id) {
1116 + case BCMA_CHIP_ID_BCM5357:
1117 + case BCMA_CHIP_ID_BCM4749:
1118 + case BCMA_CHIP_ID_BCM53572:
1119 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
1120 +
1121 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
1122 + so offset PLL0_PLLCTL[02] by 6 */
1123 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1124 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
1125 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
1126 +
1127 + /* RMW only the P1 divider */
1128 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1129 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
1130 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1131 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
1132 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
1133 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1134 +
1135 + /* RMW only the int feedback divider */
1136 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1137 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
1138 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1139 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
1140 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1141 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1142 +
1143 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1144 + break;
1145 +
1146 + case BCMA_CHIP_ID_BCM4331:
1147 + case BCMA_CHIP_ID_BCM43431:
1148 + if (spuravoid == 2) {
1149 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1150 + 0x11500014);
1151 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1152 + 0x0FC00a08);
1153 + } else if (spuravoid == 1) {
1154 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1155 + 0x11500014);
1156 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1157 + 0x0F600a08);
1158 + } else {
1159 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1160 + 0x11100014);
1161 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1162 + 0x03000a08);
1163 + }
1164 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1165 + break;
1166 +
1167 + case BCMA_CHIP_ID_BCM43224:
1168 + case BCMA_CHIP_ID_BCM43225:
1169 + case BCMA_CHIP_ID_BCM43421:
1170 + if (spuravoid == 1) {
1171 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1172 + 0x11500010);
1173 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1174 + 0x000C0C06);
1175 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1176 + 0x0F600a08);
1177 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1178 + 0x00000000);
1179 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1180 + 0x2001E920);
1181 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1182 + 0x88888815);
1183 + } else {
1184 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1185 + 0x11100010);
1186 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1187 + 0x000c0c06);
1188 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1189 + 0x03000a08);
1190 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1191 + 0x00000000);
1192 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1193 + 0x200005c0);
1194 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1195 + 0x88888815);
1196 + }
1197 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1198 + break;
1199 +
1200 + case BCMA_CHIP_ID_BCM4716:
1201 + case BCMA_CHIP_ID_BCM4748:
1202 + case BCMA_CHIP_ID_BCM47162:
1203 + if (spuravoid == 1) {
1204 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1205 + 0x11500060);
1206 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1207 + 0x080C0C06);
1208 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1209 + 0x0F600000);
1210 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1211 + 0x00000000);
1212 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1213 + 0x2001E924);
1214 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1215 + 0x88888815);
1216 + } else {
1217 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1218 + 0x11100060);
1219 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1220 + 0x080c0c06);
1221 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1222 + 0x03000000);
1223 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1224 + 0x00000000);
1225 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1226 + 0x200005c0);
1227 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1228 + 0x88888815);
1229 + }
1230 +
1231 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
1232 + break;
1233 +
1234 + case BCMA_CHIP_ID_BCM43227:
1235 + case BCMA_CHIP_ID_BCM43228:
1236 + case BCMA_CHIP_ID_BCM43428:
1237 + /* LCNXN */
1238 + /* PLL Settings for spur avoidance on/off mode,
1239 + no on2 support for 43228A0 */
1240 + if (spuravoid == 1) {
1241 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1242 + 0x01100014);
1243 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1244 + 0x040C0C06);
1245 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1246 + 0x03140A08);
1247 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1248 + 0x00333333);
1249 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1250 + 0x202C2820);
1251 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1252 + 0x88888815);
1253 + } else {
1254 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1255 + 0x11100014);
1256 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1257 + 0x040c0c06);
1258 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1259 + 0x03000a08);
1260 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1261 + 0x00000000);
1262 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1263 + 0x200005c0);
1264 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1265 + 0x88888815);
1266 + }
1267 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1268 + break;
1269 + default:
1270 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
1271 + bus->chipinfo.id);
1272 + break;
1273 }
1274
1275 - return bcma_pmu_get_clockcontrol(cc);
1276 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
1277 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
1278 }
1279 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
1280 --- /dev/null
1281 +++ b/drivers/bcma/driver_gmac_cmn.c
1282 @@ -0,0 +1,14 @@
1283 +/*
1284 + * Broadcom specific AMBA
1285 + * GBIT MAC COMMON Core
1286 + *
1287 + * Licensed under the GNU/GPL. See COPYING for details.
1288 + */
1289 +
1290 +#include "bcma_private.h"
1291 +#include <linux/bcma/bcma.h>
1292 +
1293 +void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
1294 +{
1295 + mutex_init(&gc->phy_mutex);
1296 +}
1297 --- /dev/null
1298 +++ b/drivers/bcma/driver_gpio.c
1299 @@ -0,0 +1,114 @@
1300 +/*
1301 + * Broadcom specific AMBA
1302 + * GPIO driver
1303 + *
1304 + * Copyright 2011, Broadcom Corporation
1305 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1306 + *
1307 + * Licensed under the GNU/GPL. See COPYING for details.
1308 + */
1309 +
1310 +#include <linux/gpio.h>
1311 +#include <linux/export.h>
1312 +#include <linux/bcma/bcma.h>
1313 +
1314 +#include "bcma_private.h"
1315 +
1316 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1317 +{
1318 + return container_of(chip, struct bcma_drv_cc, gpio);
1319 +}
1320 +
1321 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1322 +{
1323 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1324 +
1325 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1326 +}
1327 +
1328 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1329 + int value)
1330 +{
1331 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1332 +
1333 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1334 +}
1335 +
1336 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1337 +{
1338 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1339 +
1340 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1341 + return 0;
1342 +}
1343 +
1344 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1345 + int value)
1346 +{
1347 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1348 +
1349 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1350 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1351 + return 0;
1352 +}
1353 +
1354 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1355 +{
1356 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1357 +
1358 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1359 + /* clear pulldown */
1360 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1361 + /* Set pullup */
1362 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1363 +
1364 + return 0;
1365 +}
1366 +
1367 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1368 +{
1369 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1370 +
1371 + /* clear pullup */
1372 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1373 +}
1374 +
1375 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
1376 +{
1377 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1378 +
1379 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1380 + return bcma_core_irq(cc->core);
1381 + else
1382 + return -EINVAL;
1383 +}
1384 +
1385 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1386 +{
1387 + struct gpio_chip *chip = &cc->gpio;
1388 +
1389 + chip->label = "bcma_gpio";
1390 + chip->owner = THIS_MODULE;
1391 + chip->request = bcma_gpio_request;
1392 + chip->free = bcma_gpio_free;
1393 + chip->get = bcma_gpio_get_value;
1394 + chip->set = bcma_gpio_set_value;
1395 + chip->direction_input = bcma_gpio_direction_input;
1396 + chip->direction_output = bcma_gpio_direction_output;
1397 + chip->to_irq = bcma_gpio_to_irq;
1398 + chip->ngpio = 16;
1399 + /* There is just one SoC in one device and its GPIO addresses should be
1400 + * deterministic to address them more easily. The other buses could get
1401 + * a random base number. */
1402 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1403 + chip->base = 0;
1404 + else
1405 + chip->base = -1;
1406 +
1407 + return gpiochip_add(chip);
1408 +}
1409 +
1410 +int bcma_gpio_unregister(struct bcma_drv_cc *cc)
1411 +{
1412 + return gpiochip_remove(&cc->gpio);
1413 +}
1414 --- a/drivers/bcma/driver_mips.c
1415 +++ b/drivers/bcma/driver_mips.c
1416 @@ -22,15 +22,15 @@
1417 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1418 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1419 {
1420 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
1421 - dev->id.id == BCMA_CORE_MIPS_74K;
1422 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
1423 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
1424 }
1425
1426 /* The 5357b0 hangs when reading USB20H DMP registers */
1427 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
1428 {
1429 - return (dev->bus->chipinfo.id == 0x5357 ||
1430 - dev->bus->chipinfo.id == 0x4749) &&
1431 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1432 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
1433 dev->bus->chipinfo.pkg == 11 &&
1434 dev->id.id == BCMA_CORE_USB20_HOST;
1435 }
1436 @@ -74,28 +74,41 @@ static u32 bcma_core_mips_irqflag(struct
1437 return dev->core_index;
1438 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1439
1440 - return flag & 0x1F;
1441 + if (flag)
1442 + return flag & 0x1F;
1443 + else
1444 + return 0x3f;
1445 }
1446
1447 /* Get the MIPS IRQ assignment for a specified device.
1448 * If unassigned, 0 is returned.
1449 + * If disabled, 5 is returned.
1450 + * If not supported, 6 is returned.
1451 */
1452 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1453 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1454 {
1455 struct bcma_device *mdev = dev->bus->drv_mips.core;
1456 u32 irqflag;
1457 unsigned int irq;
1458
1459 irqflag = bcma_core_mips_irqflag(dev);
1460 + if (irqflag == 0x3f)
1461 + return 6;
1462
1463 - for (irq = 1; irq <= 4; irq++)
1464 + for (irq = 0; irq <= 4; irq++)
1465 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1466 (1 << irqflag))
1467 return irq;
1468
1469 - return 0;
1470 + return 5;
1471 +}
1472 +
1473 +unsigned int bcma_core_irq(struct bcma_device *dev)
1474 +{
1475 + unsigned int mips_irq = bcma_core_mips_irq(dev);
1476 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1477 }
1478 -EXPORT_SYMBOL(bcma_core_mips_irq);
1479 +EXPORT_SYMBOL(bcma_core_irq);
1480
1481 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1482 {
1483 @@ -114,8 +127,8 @@ static void bcma_core_mips_set_irq(struc
1484 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1485 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1486 ~(1 << irqflag));
1487 - else
1488 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1489 + else if (oldirq != 5)
1490 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1491
1492 /* assign the new one */
1493 if (irq == 0) {
1494 @@ -123,17 +136,17 @@ static void bcma_core_mips_set_irq(struc
1495 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1496 (1 << irqflag));
1497 } else {
1498 - u32 oldirqflag = bcma_read32(mdev,
1499 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1500 - if (oldirqflag) {
1501 + u32 irqinitmask = bcma_read32(mdev,
1502 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1503 + if (irqinitmask) {
1504 struct bcma_device *core;
1505
1506 /* backplane irq line is in use, find out who uses
1507 * it and set user to irq 0
1508 */
1509 - list_for_each_entry_reverse(core, &bus->cores, list) {
1510 + list_for_each_entry(core, &bus->cores, list) {
1511 if ((1 << bcma_core_mips_irqflag(core)) ==
1512 - oldirqflag) {
1513 + irqinitmask) {
1514 bcma_core_mips_set_irq(core, 0);
1515 break;
1516 }
1517 @@ -143,15 +156,31 @@ static void bcma_core_mips_set_irq(struc
1518 1 << irqflag);
1519 }
1520
1521 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
1522 - dev->id.id, oldirq + 2, irq + 2);
1523 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1524 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1525 +}
1526 +
1527 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1528 + u16 coreid, u8 unit)
1529 +{
1530 + struct bcma_device *core;
1531 +
1532 + core = bcma_find_core_unit(bus, coreid, unit);
1533 + if (!core) {
1534 + bcma_warn(bus,
1535 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1536 + coreid, unit);
1537 + return;
1538 + }
1539 +
1540 + bcma_core_mips_set_irq(core, irq);
1541 }
1542
1543 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1544 {
1545 int i;
1546 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1547 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1548 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1549 for (i = 0; i <= 6; i++)
1550 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1551 printk("\n");
1552 @@ -161,7 +190,7 @@ static void bcma_core_mips_dump_irq(stru
1553 {
1554 struct bcma_device *core;
1555
1556 - list_for_each_entry_reverse(core, &bus->cores, list) {
1557 + list_for_each_entry(core, &bus->cores, list) {
1558 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
1559 }
1560 }
1561 @@ -171,9 +200,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1562 struct bcma_bus *bus = mcore->core->bus;
1563
1564 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1565 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1566 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1567
1568 - pr_err("No PMU available, need this to get the cpu clock\n");
1569 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1570 return 0;
1571 }
1572 EXPORT_SYMBOL(bcma_cpu_clock);
1573 @@ -185,10 +214,10 @@ static void bcma_core_mips_flash_detect(
1574 switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1575 case BCMA_CC_FLASHT_STSER:
1576 case BCMA_CC_FLASHT_ATSER:
1577 - pr_err("Serial flash not supported.\n");
1578 + bcma_err(bus, "Serial flash not supported.\n");
1579 break;
1580 case BCMA_CC_FLASHT_PARA:
1581 - pr_info("found parallel flash.\n");
1582 + bcma_info(bus, "found parallel flash.\n");
1583 bus->drv_cc.pflash.window = 0x1c000000;
1584 bus->drv_cc.pflash.window_size = 0x02000000;
1585
1586 @@ -199,7 +228,46 @@ static void bcma_core_mips_flash_detect(
1587 bus->drv_cc.pflash.buswidth = 2;
1588 break;
1589 default:
1590 - pr_err("flash not supported.\n");
1591 + bcma_err(bus, "flash not supported.\n");
1592 + }
1593 +}
1594 +
1595 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1596 +{
1597 + struct bcma_bus *bus = mcore->core->bus;
1598 +
1599 + if (mcore->early_setup_done)
1600 + return;
1601 +
1602 + bcma_chipco_serial_init(&bus->drv_cc);
1603 + bcma_core_mips_flash_detect(mcore);
1604 +
1605 + mcore->early_setup_done = true;
1606 +}
1607 +
1608 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
1609 +{
1610 + struct bcma_device *cpu, *pcie, *i2s;
1611 +
1612 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
1613 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
1614 + */
1615 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
1616 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
1617 + return;
1618 +
1619 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1620 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
1621 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
1622 + if (cpu && pcie && i2s &&
1623 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1624 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1625 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
1626 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
1627 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
1628 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
1629 + bcma_debug(bus,
1630 + "Moved i2s interrupt to oob line 7 instead of 8\n");
1631 }
1632 }
1633
1634 @@ -209,48 +277,59 @@ void bcma_core_mips_init(struct bcma_drv
1635 struct bcma_device *core;
1636 bus = mcore->core->bus;
1637
1638 - pr_info("Initializing MIPS core...\n");
1639 + if (mcore->setup_done)
1640 + return;
1641 +
1642 + bcma_debug(bus, "Initializing MIPS core...\n");
1643
1644 - if (!mcore->setup_done)
1645 - mcore->assigned_irqs = 1;
1646 + bcma_core_mips_early_init(mcore);
1647
1648 - /* Assign IRQs to all cores on the bus */
1649 - list_for_each_entry_reverse(core, &bus->cores, list) {
1650 - int mips_irq;
1651 - if (core->irq)
1652 - continue;
1653 -
1654 - mips_irq = bcma_core_mips_irq(core);
1655 - if (mips_irq > 4)
1656 - core->irq = 0;
1657 - else
1658 - core->irq = mips_irq + 2;
1659 - if (core->irq > 5)
1660 - continue;
1661 - switch (core->id.id) {
1662 - case BCMA_CORE_PCI:
1663 - case BCMA_CORE_PCIE:
1664 - case BCMA_CORE_ETHERNET:
1665 - case BCMA_CORE_ETHERNET_GBIT:
1666 - case BCMA_CORE_MAC_GBIT:
1667 - case BCMA_CORE_80211:
1668 - case BCMA_CORE_USB20_HOST:
1669 - /* These devices get their own IRQ line if available,
1670 - * the rest goes on IRQ0
1671 - */
1672 - if (mcore->assigned_irqs <= 4)
1673 - bcma_core_mips_set_irq(core,
1674 - mcore->assigned_irqs++);
1675 - break;
1676 + bcma_fix_i2s_irqflag(bus);
1677 +
1678 + switch (bus->chipinfo.id) {
1679 + case BCMA_CHIP_ID_BCM4716:
1680 + case BCMA_CHIP_ID_BCM4748:
1681 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1682 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1683 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1684 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1685 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1686 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1687 + break;
1688 + case BCMA_CHIP_ID_BCM5356:
1689 + case BCMA_CHIP_ID_BCM47162:
1690 + case BCMA_CHIP_ID_BCM53572:
1691 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1692 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1693 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1694 + break;
1695 + case BCMA_CHIP_ID_BCM5357:
1696 + case BCMA_CHIP_ID_BCM4749:
1697 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1698 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1699 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1700 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1701 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1702 + break;
1703 + case BCMA_CHIP_ID_BCM4706:
1704 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1705 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1706 + 0);
1707 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1708 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1709 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1710 + 0);
1711 + break;
1712 + default:
1713 + list_for_each_entry(core, &bus->cores, list) {
1714 + core->irq = bcma_core_irq(core);
1715 }
1716 + bcma_err(bus,
1717 + "Unknown device (0x%x) found, can not configure IRQs\n",
1718 + bus->chipinfo.id);
1719 }
1720 - pr_info("IRQ reconfiguration done\n");
1721 + bcma_debug(bus, "IRQ reconfiguration done\n");
1722 bcma_core_mips_dump_irq(bus);
1723
1724 - if (mcore->setup_done)
1725 - return;
1726 -
1727 - bcma_chipco_serial_init(&bus->drv_cc);
1728 - bcma_core_mips_flash_detect(mcore);
1729 mcore->setup_done = true;
1730 }
1731 --- a/drivers/bcma/driver_pci.c
1732 +++ b/drivers/bcma/driver_pci.c
1733 @@ -2,8 +2,9 @@
1734 * Broadcom specific AMBA
1735 * PCI Core
1736 *
1737 - * Copyright 2005, Broadcom Corporation
1738 + * Copyright 2005, 2011, Broadcom Corporation
1739 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1740 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1741 *
1742 * Licensed under the GNU/GPL. See COPYING for details.
1743 */
1744 @@ -16,120 +17,124 @@
1745 * R/W ops.
1746 **************************************************/
1747
1748 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1749 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1750 {
1751 - pcicore_write32(pc, 0x130, address);
1752 - pcicore_read32(pc, 0x130);
1753 - return pcicore_read32(pc, 0x134);
1754 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1755 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1756 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
1757 }
1758
1759 -#if 0
1760 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
1761 {
1762 - pcicore_write32(pc, 0x130, address);
1763 - pcicore_read32(pc, 0x130);
1764 - pcicore_write32(pc, 0x134, data);
1765 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1766 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1767 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1768 }
1769 -#endif
1770
1771 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1772 {
1773 - const u16 mdio_control = 0x128;
1774 - const u16 mdio_data = 0x12C;
1775 u32 v;
1776 int i;
1777
1778 - v = (1 << 30); /* Start of Transaction */
1779 - v |= (1 << 28); /* Write Transaction */
1780 - v |= (1 << 17); /* Turnaround */
1781 - v |= (0x1F << 18);
1782 + v = BCMA_CORE_PCI_MDIODATA_START;
1783 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1784 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1785 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1786 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
1787 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1788 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1789 v |= (phy << 4);
1790 - pcicore_write32(pc, mdio_data, v);
1791 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1792
1793 udelay(10);
1794 for (i = 0; i < 200; i++) {
1795 - v = pcicore_read32(pc, mdio_control);
1796 - if (v & 0x100 /* Trans complete */)
1797 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1798 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1799 break;
1800 - msleep(1);
1801 + usleep_range(1000, 2000);
1802 }
1803 }
1804
1805 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1806 {
1807 - const u16 mdio_control = 0x128;
1808 - const u16 mdio_data = 0x12C;
1809 int max_retries = 10;
1810 u16 ret = 0;
1811 u32 v;
1812 int i;
1813
1814 - v = 0x80; /* Enable Preamble Sequence */
1815 - v |= 0x2; /* MDIO Clock Divisor */
1816 - pcicore_write32(pc, mdio_control, v);
1817 + /* enable mdio access to SERDES */
1818 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1819 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1820 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1821
1822 if (pc->core->id.rev >= 10) {
1823 max_retries = 200;
1824 bcma_pcie_mdio_set_phy(pc, device);
1825 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1826 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1827 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1828 + } else {
1829 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1830 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1831 }
1832
1833 - v = (1 << 30); /* Start of Transaction */
1834 - v |= (1 << 29); /* Read Transaction */
1835 - v |= (1 << 17); /* Turnaround */
1836 - if (pc->core->id.rev < 10)
1837 - v |= (u32)device << 22;
1838 - v |= (u32)address << 18;
1839 - pcicore_write32(pc, mdio_data, v);
1840 + v = BCMA_CORE_PCI_MDIODATA_START;
1841 + v |= BCMA_CORE_PCI_MDIODATA_READ;
1842 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1843 +
1844 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1845 /* Wait for the device to complete the transaction */
1846 udelay(10);
1847 for (i = 0; i < max_retries; i++) {
1848 - v = pcicore_read32(pc, mdio_control);
1849 - if (v & 0x100 /* Trans complete */) {
1850 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1851 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
1852 udelay(10);
1853 - ret = pcicore_read32(pc, mdio_data);
1854 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1855 break;
1856 }
1857 - msleep(1);
1858 + usleep_range(1000, 2000);
1859 }
1860 - pcicore_write32(pc, mdio_control, 0);
1861 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1862 return ret;
1863 }
1864
1865 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1866 u8 address, u16 data)
1867 {
1868 - const u16 mdio_control = 0x128;
1869 - const u16 mdio_data = 0x12C;
1870 int max_retries = 10;
1871 u32 v;
1872 int i;
1873
1874 - v = 0x80; /* Enable Preamble Sequence */
1875 - v |= 0x2; /* MDIO Clock Divisor */
1876 - pcicore_write32(pc, mdio_control, v);
1877 + /* enable mdio access to SERDES */
1878 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1879 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1880 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1881
1882 if (pc->core->id.rev >= 10) {
1883 max_retries = 200;
1884 bcma_pcie_mdio_set_phy(pc, device);
1885 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1886 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1887 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1888 + } else {
1889 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1890 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1891 }
1892
1893 - v = (1 << 30); /* Start of Transaction */
1894 - v |= (1 << 28); /* Write Transaction */
1895 - v |= (1 << 17); /* Turnaround */
1896 - if (pc->core->id.rev < 10)
1897 - v |= (u32)device << 22;
1898 - v |= (u32)address << 18;
1899 + v = BCMA_CORE_PCI_MDIODATA_START;
1900 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1901 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1902 v |= data;
1903 - pcicore_write32(pc, mdio_data, v);
1904 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1905 /* Wait for the device to complete the transaction */
1906 udelay(10);
1907 for (i = 0; i < max_retries; i++) {
1908 - v = pcicore_read32(pc, mdio_control);
1909 - if (v & 0x100 /* Trans complete */)
1910 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1911 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1912 break;
1913 - msleep(1);
1914 + usleep_range(1000, 2000);
1915 }
1916 - pcicore_write32(pc, mdio_control, 0);
1917 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1918 }
1919
1920 /**************************************************
1921 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
1922
1923 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
1924 {
1925 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1926 + u32 tmp;
1927 +
1928 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
1929 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
1930 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
1931 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
1932 + else
1933 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
1934 }
1935
1936 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
1937 {
1938 - const u8 serdes_pll_device = 0x1D;
1939 - const u8 serdes_rx_device = 0x1F;
1940 u16 tmp;
1941
1942 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1943 - bcma_pcicore_polarity_workaround(pc));
1944 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1945 - if (tmp & 0x4000)
1946 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1947 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
1948 + BCMA_CORE_PCI_SERDES_RX_CTRL,
1949 + bcma_pcicore_polarity_workaround(pc));
1950 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1951 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
1952 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
1953 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1954 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
1955 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
1956 +}
1957 +
1958 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
1959 +{
1960 + struct bcma_device *core = pc->core;
1961 + u16 val16, core_index;
1962 + uint regoff;
1963 +
1964 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
1965 + core_index = (u16)core->core_index;
1966 +
1967 + val16 = pcicore_read16(pc, regoff);
1968 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
1969 + != core_index) {
1970 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
1971 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
1972 + pcicore_write16(pc, regoff, val16);
1973 + }
1974 +}
1975 +
1976 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
1977 +/* Needs to happen when coming out of 'standby'/'hibernate' */
1978 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
1979 +{
1980 + u16 val16;
1981 + uint regoff;
1982 +
1983 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
1984 +
1985 + val16 = pcicore_read16(pc, regoff);
1986 +
1987 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
1988 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
1989 + pcicore_write16(pc, regoff, val16);
1990 + }
1991 }
1992
1993 /**************************************************
1994 * Init.
1995 **************************************************/
1996
1997 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1998 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1999 {
2000 + bcma_core_pci_fixcfg(pc);
2001 bcma_pcicore_serdes_workaround(pc);
2002 + bcma_core_pci_config_fixup(pc);
2003 }
2004
2005 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2006 -{
2007 - struct bcma_bus *bus = pc->core->bus;
2008 - u16 chipid_top;
2009 -
2010 - chipid_top = (bus->chipinfo.id & 0xFF00);
2011 - if (chipid_top != 0x4700 &&
2012 - chipid_top != 0x5300)
2013 - return false;
2014 -
2015 -#ifdef CONFIG_SSB_DRIVER_PCICORE
2016 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
2017 - return false;
2018 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
2019 -
2020 -#if 0
2021 - /* TODO: on BCMA we use address from EROM instead of magic formula */
2022 - u32 tmp;
2023 - return !mips_busprobe32(tmp, (bus->mmio +
2024 - (pc->core->core_index * BCMA_CORE_SIZE)));
2025 -#endif
2026 -
2027 - return true;
2028 -}
2029 -
2030 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
2031 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
2032 {
2033 if (pc->setup_done)
2034 return;
2035
2036 - if (bcma_core_pci_is_in_hostmode(pc)) {
2037 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2038 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
2039 + if (pc->hostmode)
2040 bcma_core_pci_hostmode_init(pc);
2041 -#else
2042 - pr_err("Driver compiled without support for hostmode PCI\n");
2043 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
2044 - } else {
2045 - bcma_core_pci_clientmode_init(pc);
2046 - }
2047
2048 - pc->setup_done = true;
2049 + if (!pc->hostmode)
2050 + bcma_core_pci_clientmode_init(pc);
2051 }
2052
2053 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
2054 bool enable)
2055 {
2056 - struct pci_dev *pdev = pc->core->bus->host_pci;
2057 + struct pci_dev *pdev;
2058 u32 coremask, tmp;
2059 int err = 0;
2060
2061 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2062 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2063 /* This bcma device is not on a PCI host-bus. So the IRQs are
2064 * not routed through the PCI core.
2065 * So we must not enable routing through the PCI core. */
2066 goto out;
2067 }
2068
2069 + pdev = pc->core->bus->host_pci;
2070 +
2071 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
2072 if (err)
2073 goto out;
2074 @@ -236,3 +261,17 @@ out:
2075 return err;
2076 }
2077 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
2078 +
2079 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
2080 +{
2081 + u32 w;
2082 +
2083 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2084 + if (extend)
2085 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2086 + else
2087 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2088 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
2089 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2090 +}
2091 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
2092 --- a/drivers/bcma/driver_pci_host.c
2093 +++ b/drivers/bcma/driver_pci_host.c
2094 @@ -2,13 +2,616 @@
2095 * Broadcom specific AMBA
2096 * PCI Core in hostmode
2097 *
2098 + * Copyright 2005 - 2011, Broadcom Corporation
2099 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2100 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2101 + *
2102 * Licensed under the GNU/GPL. See COPYING for details.
2103 */
2104
2105 #include "bcma_private.h"
2106 +#include <linux/pci.h>
2107 +#include <linux/export.h>
2108 #include <linux/bcma/bcma.h>
2109 +#include <asm/paccess.h>
2110 +
2111 +/* Probe a 32bit value on the bus and catch bus exceptions.
2112 + * Returns nonzero on a bus exception.
2113 + * This is MIPS specific */
2114 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
2115 +
2116 +/* Assume one-hot slot wiring */
2117 +#define BCMA_PCI_SLOT_MAX 16
2118 +#define PCI_CONFIG_SPACE_SIZE 256
2119 +
2120 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2121 +{
2122 + struct bcma_bus *bus = pc->core->bus;
2123 + u16 chipid_top;
2124 + u32 tmp;
2125 +
2126 + chipid_top = (bus->chipinfo.id & 0xFF00);
2127 + if (chipid_top != 0x4700 &&
2128 + chipid_top != 0x5300)
2129 + return false;
2130 +
2131 + bcma_core_enable(pc->core, 0);
2132 +
2133 + return !mips_busprobe32(tmp, pc->core->io_addr);
2134 +}
2135 +
2136 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
2137 +{
2138 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2139 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2140 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
2141 +}
2142 +
2143 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
2144 + u32 data)
2145 +{
2146 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2147 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2148 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
2149 +}
2150 +
2151 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
2152 + unsigned int func, unsigned int off)
2153 +{
2154 + u32 addr = 0;
2155 +
2156 + /* Issue config commands only when the data link is up (atleast
2157 + * one external pcie device is present).
2158 + */
2159 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
2160 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
2161 + goto out;
2162 +
2163 + /* Type 0 transaction */
2164 + /* Slide the PCI window to the appropriate slot */
2165 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2166 + /* Calculate the address */
2167 + addr = pc->host_controller->host_cfg_addr;
2168 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
2169 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
2170 + addr |= (off & ~3);
2171 +
2172 +out:
2173 + return addr;
2174 +}
2175 +
2176 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
2177 + unsigned int func, unsigned int off,
2178 + void *buf, int len)
2179 +{
2180 + int err = -EINVAL;
2181 + u32 addr, val;
2182 + void __iomem *mmio = 0;
2183 +
2184 + WARN_ON(!pc->hostmode);
2185 + if (unlikely(len != 1 && len != 2 && len != 4))
2186 + goto out;
2187 + if (dev == 0) {
2188 + /* we support only two functions on device 0 */
2189 + if (func > 1)
2190 + goto out;
2191 +
2192 + /* accesses to config registers with offsets >= 256
2193 + * requires indirect access.
2194 + */
2195 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2196 + addr = (func << 12);
2197 + addr |= (off & 0x0FFC);
2198 + val = bcma_pcie_read_config(pc, addr);
2199 + } else {
2200 + addr = BCMA_CORE_PCI_PCICFG0;
2201 + addr |= (func << 8);
2202 + addr |= (off & 0xFC);
2203 + val = pcicore_read32(pc, addr);
2204 + }
2205 + } else {
2206 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2207 + if (unlikely(!addr))
2208 + goto out;
2209 + err = -ENOMEM;
2210 + mmio = ioremap_nocache(addr, sizeof(val));
2211 + if (!mmio)
2212 + goto out;
2213 +
2214 + if (mips_busprobe32(val, mmio)) {
2215 + val = 0xFFFFFFFF;
2216 + goto unmap;
2217 + }
2218 + }
2219 + val >>= (8 * (off & 3));
2220 +
2221 + switch (len) {
2222 + case 1:
2223 + *((u8 *)buf) = (u8)val;
2224 + break;
2225 + case 2:
2226 + *((u16 *)buf) = (u16)val;
2227 + break;
2228 + case 4:
2229 + *((u32 *)buf) = (u32)val;
2230 + break;
2231 + }
2232 + err = 0;
2233 +unmap:
2234 + if (mmio)
2235 + iounmap(mmio);
2236 +out:
2237 + return err;
2238 +}
2239
2240 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2241 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
2242 + unsigned int func, unsigned int off,
2243 + const void *buf, int len)
2244 {
2245 - pr_err("No support for PCI core in hostmode yet\n");
2246 + int err = -EINVAL;
2247 + u32 addr, val;
2248 + void __iomem *mmio = 0;
2249 + u16 chipid = pc->core->bus->chipinfo.id;
2250 +
2251 + WARN_ON(!pc->hostmode);
2252 + if (unlikely(len != 1 && len != 2 && len != 4))
2253 + goto out;
2254 + if (dev == 0) {
2255 + /* we support only two functions on device 0 */
2256 + if (func > 1)
2257 + goto out;
2258 +
2259 + /* accesses to config registers with offsets >= 256
2260 + * requires indirect access.
2261 + */
2262 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2263 + addr = (func << 12);
2264 + addr |= (off & 0x0FFC);
2265 + val = bcma_pcie_read_config(pc, addr);
2266 + } else {
2267 + addr = BCMA_CORE_PCI_PCICFG0;
2268 + addr |= (func << 8);
2269 + addr |= (off & 0xFC);
2270 + val = pcicore_read32(pc, addr);
2271 + }
2272 + } else {
2273 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2274 + if (unlikely(!addr))
2275 + goto out;
2276 + err = -ENOMEM;
2277 + mmio = ioremap_nocache(addr, sizeof(val));
2278 + if (!mmio)
2279 + goto out;
2280 +
2281 + if (mips_busprobe32(val, mmio)) {
2282 + val = 0xFFFFFFFF;
2283 + goto unmap;
2284 + }
2285 + }
2286 +
2287 + switch (len) {
2288 + case 1:
2289 + val &= ~(0xFF << (8 * (off & 3)));
2290 + val |= *((const u8 *)buf) << (8 * (off & 3));
2291 + break;
2292 + case 2:
2293 + val &= ~(0xFFFF << (8 * (off & 3)));
2294 + val |= *((const u16 *)buf) << (8 * (off & 3));
2295 + break;
2296 + case 4:
2297 + val = *((const u32 *)buf);
2298 + break;
2299 + }
2300 + if (dev == 0) {
2301 + /* accesses to config registers with offsets >= 256
2302 + * requires indirect access.
2303 + */
2304 + if (off >= PCI_CONFIG_SPACE_SIZE)
2305 + bcma_pcie_write_config(pc, addr, val);
2306 + else
2307 + pcicore_write32(pc, addr, val);
2308 + } else {
2309 + writel(val, mmio);
2310 +
2311 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
2312 + chipid == BCMA_CHIP_ID_BCM4748)
2313 + readl(mmio);
2314 + }
2315 +
2316 + err = 0;
2317 +unmap:
2318 + if (mmio)
2319 + iounmap(mmio);
2320 +out:
2321 + return err;
2322 +}
2323 +
2324 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
2325 + unsigned int devfn,
2326 + int reg, int size, u32 *val)
2327 +{
2328 + unsigned long flags;
2329 + int err;
2330 + struct bcma_drv_pci *pc;
2331 + struct bcma_drv_pci_host *pc_host;
2332 +
2333 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2334 + pc = pc_host->pdev;
2335 +
2336 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2337 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
2338 + PCI_FUNC(devfn), reg, val, size);
2339 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2340 +
2341 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2342 +}
2343 +
2344 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
2345 + unsigned int devfn,
2346 + int reg, int size, u32 val)
2347 +{
2348 + unsigned long flags;
2349 + int err;
2350 + struct bcma_drv_pci *pc;
2351 + struct bcma_drv_pci_host *pc_host;
2352 +
2353 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2354 + pc = pc_host->pdev;
2355 +
2356 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2357 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
2358 + PCI_FUNC(devfn), reg, &val, size);
2359 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2360 +
2361 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2362 +}
2363 +
2364 +/* return cap_offset if requested capability exists in the PCI config space */
2365 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
2366 + unsigned int dev,
2367 + unsigned int func, u8 req_cap_id,
2368 + unsigned char *buf, u32 *buflen)
2369 +{
2370 + u8 cap_id;
2371 + u8 cap_ptr = 0;
2372 + u32 bufsize;
2373 + u8 byte_val;
2374 +
2375 + /* check for Header type 0 */
2376 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
2377 + sizeof(u8));
2378 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
2379 + return cap_ptr;
2380 +
2381 + /* check if the capability pointer field exists */
2382 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
2383 + sizeof(u8));
2384 + if (!(byte_val & PCI_STATUS_CAP_LIST))
2385 + return cap_ptr;
2386 +
2387 + /* check if the capability pointer is 0x00 */
2388 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
2389 + sizeof(u8));
2390 + if (cap_ptr == 0x00)
2391 + return cap_ptr;
2392 +
2393 + /* loop thr'u the capability list and see if the requested capabilty
2394 + * exists */
2395 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
2396 + while (cap_id != req_cap_id) {
2397 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
2398 + sizeof(u8));
2399 + if (cap_ptr == 0x00)
2400 + return cap_ptr;
2401 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
2402 + sizeof(u8));
2403 + }
2404 +
2405 + /* found the caller requested capability */
2406 + if ((buf != NULL) && (buflen != NULL)) {
2407 + u8 cap_data;
2408 +
2409 + bufsize = *buflen;
2410 + if (!bufsize)
2411 + return cap_ptr;
2412 +
2413 + *buflen = 0;
2414 +
2415 + /* copy the cpability data excluding cap ID and next ptr */
2416 + cap_data = cap_ptr + 2;
2417 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
2418 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
2419 + *buflen = bufsize;
2420 + while (bufsize--) {
2421 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
2422 + sizeof(u8));
2423 + cap_data++;
2424 + buf++;
2425 + }
2426 + }
2427 +
2428 + return cap_ptr;
2429 +}
2430 +
2431 +/* If the root port is capable of returning Config Request
2432 + * Retry Status (CRS) Completion Status to software then
2433 + * enable the feature.
2434 + */
2435 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
2436 +{
2437 + struct bcma_bus *bus = pc->core->bus;
2438 + u8 cap_ptr, root_ctrl, root_cap, dev;
2439 + u16 val16;
2440 + int i;
2441 +
2442 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
2443 + NULL);
2444 + root_cap = cap_ptr + PCI_EXP_RTCAP;
2445 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
2446 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
2447 + /* Enable CRS software visibility */
2448 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
2449 + val16 = PCI_EXP_RTCTL_CRSSVE;
2450 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
2451 + sizeof(u16));
2452 +
2453 + /* Initiate a configuration request to read the vendor id
2454 + * field of the device function's config space header after
2455 + * 100 ms wait time from the end of Reset. If the device is
2456 + * not done with its internal initialization, it must at
2457 + * least return a completion TLP, with a completion status
2458 + * of "Configuration Request Retry Status (CRS)". The root
2459 + * complex must complete the request to the host by returning
2460 + * a read-data value of 0001h for the Vendor ID field and
2461 + * all 1s for any additional bytes included in the request.
2462 + * Poll using the config reads for max wait time of 1 sec or
2463 + * until we receive the successful completion status. Repeat
2464 + * the procedure for all the devices.
2465 + */
2466 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
2467 + for (i = 0; i < 100000; i++) {
2468 + bcma_extpci_read_config(pc, dev, 0,
2469 + PCI_VENDOR_ID, &val16,
2470 + sizeof(val16));
2471 + if (val16 != 0x1)
2472 + break;
2473 + udelay(10);
2474 + }
2475 + if (val16 == 0x1)
2476 + bcma_err(bus, "PCI: Broken device in slot %d\n",
2477 + dev);
2478 + }
2479 + }
2480 +}
2481 +
2482 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2483 +{
2484 + struct bcma_bus *bus = pc->core->bus;
2485 + struct bcma_drv_pci_host *pc_host;
2486 + u32 tmp;
2487 + u32 pci_membase_1G;
2488 + unsigned long io_map_base;
2489 +
2490 + bcma_info(bus, "PCIEcore in host mode found\n");
2491 +
2492 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
2493 + bcma_info(bus, "This PCIE core is disabled and not working\n");
2494 + return;
2495 + }
2496 +
2497 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
2498 + if (!pc_host) {
2499 + bcma_err(bus, "can not allocate memory");
2500 + return;
2501 + }
2502 +
2503 + spin_lock_init(&pc_host->cfgspace_lock);
2504 +
2505 + pc->host_controller = pc_host;
2506 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
2507 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
2508 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
2509 + pc_host->pdev = pc;
2510 +
2511 + pci_membase_1G = BCMA_SOC_PCI_DMA;
2512 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
2513 +
2514 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
2515 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
2516 +
2517 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
2518 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
2519 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
2520 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
2521 +
2522 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
2523 + pc_host->io_resource.start = 0x100;
2524 + pc_host->io_resource.end = 0x7FF;
2525 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
2526 +
2527 + /* Reset RC */
2528 + usleep_range(3000, 5000);
2529 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
2530 + msleep(50);
2531 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
2532 + BCMA_CORE_PCI_CTL_RST_OE);
2533 +
2534 + /* 64 MB I/O access window. On 4716, use
2535 + * sbtopcie0 to access the device registers. We
2536 + * can't use address match 2 (1 GB window) region
2537 + * as mips can't generate 64-bit address on the
2538 + * backplane.
2539 + */
2540 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
2541 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
2542 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2543 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2544 + BCMA_SOC_PCI_MEM_SZ - 1;
2545 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2546 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
2547 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
2548 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
2549 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
2550 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
2551 + if (pc->core->core_unit == 0) {
2552 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2553 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2554 + BCMA_SOC_PCI_MEM_SZ - 1;
2555 + pc_host->io_resource.start = 0x100;
2556 + pc_host->io_resource.end = 0x47F;
2557 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
2558 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2559 + tmp | BCMA_SOC_PCI_MEM);
2560 + } else if (pc->core->core_unit == 1) {
2561 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
2562 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
2563 + BCMA_SOC_PCI_MEM_SZ - 1;
2564 + pc_host->io_resource.start = 0x480;
2565 + pc_host->io_resource.end = 0x7FF;
2566 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
2567 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
2568 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2569 + tmp | BCMA_SOC_PCI1_MEM);
2570 + }
2571 + } else
2572 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2573 + BCMA_CORE_PCI_SBTOPCI_IO);
2574 +
2575 + /* 64 MB configuration access window */
2576 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2577 +
2578 + /* 1 GB memory access window */
2579 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
2580 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
2581 +
2582 +
2583 + /* As per PCI Express Base Spec 1.1 we need to wait for
2584 + * at least 100 ms from the end of a reset (cold/warm/hot)
2585 + * before issuing configuration requests to PCI Express
2586 + * devices.
2587 + */
2588 + msleep(100);
2589 +
2590 + bcma_core_pci_enable_crs(pc);
2591 +
2592 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
2593 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
2594 + u16 val16;
2595 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
2596 + &val16, sizeof(val16));
2597 + val16 |= (2 << 5); /* Max payload size of 512 */
2598 + val16 |= (2 << 12); /* MRRS 512 */
2599 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
2600 + &val16, sizeof(val16));
2601 + }
2602 +
2603 + /* Enable PCI bridge BAR0 memory & master access */
2604 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2605 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
2606 +
2607 + /* Enable PCI interrupts */
2608 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
2609 +
2610 + /* Ok, ready to run, register it to the system.
2611 + * The following needs change, if we want to port hostmode
2612 + * to non-MIPS platform. */
2613 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
2614 + resource_size(&pc_host->mem_resource));
2615 + pc_host->pci_controller.io_map_base = io_map_base;
2616 + set_io_port_base(pc_host->pci_controller.io_map_base);
2617 + /* Give some time to the PCI controller to configure itself with the new
2618 + * values. Not waiting at this point causes crashes of the machine. */
2619 + usleep_range(10000, 15000);
2620 + register_pci_controller(&pc_host->pci_controller);
2621 + return;
2622 +}
2623 +
2624 +/* Early PCI fixup for a device on the PCI-core bridge. */
2625 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
2626 +{
2627 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2628 + /* This is not a device on the PCI-core bridge. */
2629 + return;
2630 + }
2631 + if (PCI_SLOT(dev->devfn) != 0)
2632 + return;
2633 +
2634 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
2635 +
2636 + /* Enable PCI bridge bus mastering and memory space */
2637 + pci_set_master(dev);
2638 + if (pcibios_enable_device(dev, ~0) < 0) {
2639 + pr_err("PCI: BCMA bridge enable failed\n");
2640 + return;
2641 + }
2642 +
2643 + /* Enable PCI bridge BAR1 prefetch and burst */
2644 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
2645 +}
2646 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
2647 +
2648 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
2649 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
2650 +{
2651 + struct resource *res;
2652 + int pos, err;
2653 +
2654 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2655 + /* This is not a device on the PCI-core bridge. */
2656 + return;
2657 + }
2658 + if (PCI_SLOT(dev->devfn) == 0)
2659 + return;
2660 +
2661 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
2662 +
2663 + for (pos = 0; pos < 6; pos++) {
2664 + res = &dev->resource[pos];
2665 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
2666 + err = pci_assign_resource(dev, pos);
2667 + if (err)
2668 + pr_err("PCI: Problem fixing up the addresses on %s\n",
2669 + pci_name(dev));
2670 + }
2671 + }
2672 +}
2673 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
2674 +
2675 +/* This function is called when doing a pci_enable_device().
2676 + * We must first check if the device is a device on the PCI-core bridge. */
2677 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
2678 +{
2679 + struct bcma_drv_pci_host *pc_host;
2680 +
2681 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2682 + /* This is not a device on the PCI-core bridge. */
2683 + return -ENODEV;
2684 + }
2685 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2686 + pci_ops);
2687 +
2688 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
2689 +
2690 + /* Fix up interrupt lines */
2691 + dev->irq = bcma_core_irq(pc_host->pdev->core);
2692 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2693 +
2694 + return 0;
2695 +}
2696 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
2697 +
2698 +/* PCI device IRQ mapping. */
2699 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
2700 +{
2701 + struct bcma_drv_pci_host *pc_host;
2702 +
2703 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2704 + /* This is not a device on the PCI-core bridge. */
2705 + return -ENODEV;
2706 + }
2707 +
2708 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2709 + pci_ops);
2710 + return bcma_core_irq(pc_host->pdev->core);
2711 }
2712 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
2713 --- a/drivers/bcma/host_pci.c
2714 +++ b/drivers/bcma/host_pci.c
2715 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
2716 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
2717 core->wrap);
2718 core->bus->mapped_core = core;
2719 - pr_debug("Switched to core: 0x%X\n", core->id.id);
2720 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
2721 }
2722
2723 /* Provides access to the requested core. Returns base offset that has to be
2724 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
2725 }
2726
2727 #ifdef CONFIG_BCMA_BLOCKIO
2728 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2729 - size_t count, u16 offset, u8 reg_width)
2730 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2731 + size_t count, u16 offset, u8 reg_width)
2732 {
2733 void __iomem *addr = core->bus->mmio + offset;
2734 if (core->bus->mapped_core != core)
2735 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
2736 }
2737 }
2738
2739 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
2740 - size_t count, u16 offset, u8 reg_width)
2741 +static void bcma_host_pci_block_write(struct bcma_device *core,
2742 + const void *buffer, size_t count,
2743 + u16 offset, u8 reg_width)
2744 {
2745 void __iomem *addr = core->bus->mmio + offset;
2746 if (core->bus->mapped_core != core)
2747 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
2748 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
2749 }
2750
2751 -const struct bcma_host_ops bcma_host_pci_ops = {
2752 +static const struct bcma_host_ops bcma_host_pci_ops = {
2753 .read8 = bcma_host_pci_read8,
2754 .read16 = bcma_host_pci_read16,
2755 .read32 = bcma_host_pci_read32,
2756 @@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci
2757 .awrite32 = bcma_host_pci_awrite32,
2758 };
2759
2760 -static int bcma_host_pci_probe(struct pci_dev *dev,
2761 - const struct pci_device_id *id)
2762 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
2763 + const struct pci_device_id *id)
2764 {
2765 struct bcma_bus *bus;
2766 int err = -ENOMEM;
2767 @@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc
2768
2769 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
2770 if (!pci_is_pcie(dev))
2771 - pr_err("PCI card detected, report problems.\n");
2772 + bcma_err(bus, "PCI card detected, report problems.\n");
2773
2774 /* Map MMIO */
2775 err = -ENOMEM;
2776 @@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc
2777 bus->hosttype = BCMA_HOSTTYPE_PCI;
2778 bus->ops = &bcma_host_pci_ops;
2779
2780 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
2781 + bus->boardinfo.type = bus->host_pci->subsystem_device;
2782 +
2783 /* Register */
2784 err = bcma_bus_register(bus);
2785 if (err)
2786 @@ -222,7 +226,7 @@ err_kfree_bus:
2787 return err;
2788 }
2789
2790 -static void bcma_host_pci_remove(struct pci_dev *dev)
2791 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
2792 {
2793 struct bcma_bus *bus = pci_get_drvdata(dev);
2794
2795 @@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
2796 pci_set_drvdata(dev, NULL);
2797 }
2798
2799 -#ifdef CONFIG_PM
2800 +#ifdef CONFIG_PM_SLEEP
2801 static int bcma_host_pci_suspend(struct device *dev)
2802 {
2803 struct pci_dev *pdev = to_pci_dev(dev);
2804 @@ -257,17 +261,21 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
2805 bcma_host_pci_resume);
2806 #define BCMA_PM_OPS (&bcma_pm_ops)
2807
2808 -#else /* CONFIG_PM */
2809 +#else /* CONFIG_PM_SLEEP */
2810
2811 #define BCMA_PM_OPS NULL
2812
2813 -#endif /* CONFIG_PM */
2814 +#endif /* CONFIG_PM_SLEEP */
2815
2816 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
2817 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
2818 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
2819 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
2820 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
2821 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
2822 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
2823 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
2824 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
2825 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
2826 { 0, },
2827 };
2828 @@ -277,7 +285,7 @@ static struct pci_driver bcma_pci_bridge
2829 .name = "bcma-pci-bridge",
2830 .id_table = bcma_pci_bridge_tbl,
2831 .probe = bcma_host_pci_probe,
2832 - .remove = bcma_host_pci_remove,
2833 + .remove = __devexit_p(bcma_host_pci_remove),
2834 .driver.pm = BCMA_PM_OPS,
2835 };
2836
2837 --- a/drivers/bcma/host_soc.c
2838 +++ b/drivers/bcma/host_soc.c
2839 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
2840 writel(value, core->io_wrap + offset);
2841 }
2842
2843 -const struct bcma_host_ops bcma_host_soc_ops = {
2844 +static const struct bcma_host_ops bcma_host_soc_ops = {
2845 .read8 = bcma_host_soc_read8,
2846 .read16 = bcma_host_soc_read16,
2847 .read32 = bcma_host_soc_read32,
2848 --- a/drivers/bcma/main.c
2849 +++ b/drivers/bcma/main.c
2850 @@ -13,6 +13,12 @@
2851 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
2852 MODULE_LICENSE("GPL");
2853
2854 +/* contains the number the next bus should get. */
2855 +static unsigned int bcma_bus_next_num = 0;
2856 +
2857 +/* bcma_buses_mutex locks the bcma_bus_next_num */
2858 +static DEFINE_MUTEX(bcma_buses_mutex);
2859 +
2860 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
2861 static int bcma_device_probe(struct device *dev);
2862 static int bcma_device_remove(struct device *dev);
2863 @@ -55,7 +61,14 @@ static struct bus_type bcma_bus_type = {
2864 .dev_attrs = bcma_device_attrs,
2865 };
2866
2867 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2868 +static u16 bcma_cc_core_id(struct bcma_bus *bus)
2869 +{
2870 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
2871 + return BCMA_CORE_4706_CHIPCOMMON;
2872 + return BCMA_CORE_CHIPCOMMON;
2873 +}
2874 +
2875 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2876 {
2877 struct bcma_device *core;
2878
2879 @@ -65,6 +78,38 @@ static struct bcma_device *bcma_find_cor
2880 }
2881 return NULL;
2882 }
2883 +EXPORT_SYMBOL_GPL(bcma_find_core);
2884 +
2885 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
2886 + u8 unit)
2887 +{
2888 + struct bcma_device *core;
2889 +
2890 + list_for_each_entry(core, &bus->cores, list) {
2891 + if (core->id.id == coreid && core->core_unit == unit)
2892 + return core;
2893 + }
2894 + return NULL;
2895 +}
2896 +
2897 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
2898 + int timeout)
2899 +{
2900 + unsigned long deadline = jiffies + timeout;
2901 + u32 val;
2902 +
2903 + do {
2904 + val = bcma_read32(core, reg);
2905 + if ((val & mask) == value)
2906 + return true;
2907 + cpu_relax();
2908 + udelay(10);
2909 + } while (!time_after_eq(jiffies, deadline));
2910 +
2911 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
2912 +
2913 + return false;
2914 +}
2915
2916 static void bcma_release_core_dev(struct device *dev)
2917 {
2918 @@ -84,16 +129,23 @@ static int bcma_register_cores(struct bc
2919 list_for_each_entry(core, &bus->cores, list) {
2920 /* We support that cores ourself */
2921 switch (core->id.id) {
2922 + case BCMA_CORE_4706_CHIPCOMMON:
2923 case BCMA_CORE_CHIPCOMMON:
2924 case BCMA_CORE_PCI:
2925 case BCMA_CORE_PCIE:
2926 case BCMA_CORE_MIPS_74K:
2927 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
2928 continue;
2929 }
2930
2931 + /* Only first GMAC core on BCM4706 is connected and working */
2932 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
2933 + core->core_unit > 0)
2934 + continue;
2935 +
2936 core->dev.release = bcma_release_core_dev;
2937 core->dev.bus = &bcma_bus_type;
2938 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
2939 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2940
2941 switch (bus->hosttype) {
2942 case BCMA_HOSTTYPE_PCI:
2943 @@ -111,41 +163,75 @@ static int bcma_register_cores(struct bc
2944
2945 err = device_register(&core->dev);
2946 if (err) {
2947 - pr_err("Could not register dev for core 0x%03X\n",
2948 - core->id.id);
2949 + bcma_err(bus,
2950 + "Could not register dev for core 0x%03X\n",
2951 + core->id.id);
2952 continue;
2953 }
2954 core->dev_registered = true;
2955 dev_id++;
2956 }
2957
2958 + err = bcma_gpio_init(&bus->drv_cc);
2959 + if (err == -ENOTSUPP)
2960 + bcma_debug(bus, "GPIO driver not activated\n");
2961 + else if (err)
2962 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
2963 +
2964 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2965 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
2966 + if (err)
2967 + bcma_err(bus, "Error registering watchdog driver\n");
2968 + }
2969 +
2970 return 0;
2971 }
2972
2973 static void bcma_unregister_cores(struct bcma_bus *bus)
2974 {
2975 - struct bcma_device *core;
2976 + struct bcma_device *core, *tmp;
2977
2978 - list_for_each_entry(core, &bus->cores, list) {
2979 + list_for_each_entry_safe(core, tmp, &bus->cores, list) {
2980 + list_del(&core->list);
2981 if (core->dev_registered)
2982 device_unregister(&core->dev);
2983 }
2984 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2985 + platform_device_unregister(bus->drv_cc.watchdog);
2986 }
2987
2988 -int bcma_bus_register(struct bcma_bus *bus)
2989 +int __devinit bcma_bus_register(struct bcma_bus *bus)
2990 {
2991 int err;
2992 struct bcma_device *core;
2993
2994 + mutex_lock(&bcma_buses_mutex);
2995 + bus->num = bcma_bus_next_num++;
2996 + mutex_unlock(&bcma_buses_mutex);
2997 +
2998 /* Scan for devices (cores) */
2999 err = bcma_bus_scan(bus);
3000 if (err) {
3001 - pr_err("Failed to scan: %d\n", err);
3002 + bcma_err(bus, "Failed to scan: %d\n", err);
3003 return -1;
3004 }
3005
3006 + /* Early init CC core */
3007 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3008 + if (core) {
3009 + bus->drv_cc.core = core;
3010 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3011 + }
3012 +
3013 + /* Try to get SPROM */
3014 + err = bcma_sprom_get(bus);
3015 + if (err == -ENOENT) {
3016 + bcma_err(bus, "No SPROM available\n");
3017 + } else if (err)
3018 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
3019 +
3020 /* Init CC core */
3021 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3022 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3023 if (core) {
3024 bus->drv_cc.core = core;
3025 bcma_core_chipcommon_init(&bus->drv_cc);
3026 @@ -159,30 +245,54 @@ int bcma_bus_register(struct bcma_bus *b
3027 }
3028
3029 /* Init PCIE core */
3030 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
3031 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
3032 if (core) {
3033 - bus->drv_pci.core = core;
3034 - bcma_core_pci_init(&bus->drv_pci);
3035 + bus->drv_pci[0].core = core;
3036 + bcma_core_pci_init(&bus->drv_pci[0]);
3037 }
3038
3039 - /* Try to get SPROM */
3040 - err = bcma_sprom_get(bus);
3041 - if (err == -ENOENT) {
3042 - pr_err("No SPROM available\n");
3043 - } else if (err)
3044 - pr_err("Failed to get SPROM: %d\n", err);
3045 + /* Init PCIE core */
3046 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
3047 + if (core) {
3048 + bus->drv_pci[1].core = core;
3049 + bcma_core_pci_init(&bus->drv_pci[1]);
3050 + }
3051 +
3052 + /* Init GBIT MAC COMMON core */
3053 + core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3054 + if (core) {
3055 + bus->drv_gmac_cmn.core = core;
3056 + bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
3057 + }
3058
3059 /* Register found cores */
3060 bcma_register_cores(bus);
3061
3062 - pr_info("Bus registered\n");
3063 + bcma_info(bus, "Bus registered\n");
3064
3065 return 0;
3066 }
3067
3068 void bcma_bus_unregister(struct bcma_bus *bus)
3069 {
3070 + struct bcma_device *cores[3];
3071 + int err;
3072 +
3073 + err = bcma_gpio_unregister(&bus->drv_cc);
3074 + if (err == -EBUSY)
3075 + bcma_err(bus, "Some GPIOs are still in use.\n");
3076 + else if (err)
3077 + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
3078 +
3079 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3080 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
3081 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3082 +
3083 bcma_unregister_cores(bus);
3084 +
3085 + kfree(cores[2]);
3086 + kfree(cores[1]);
3087 + kfree(cores[0]);
3088 }
3089
3090 int __init bcma_bus_early_register(struct bcma_bus *bus,
3091 @@ -196,14 +306,14 @@ int __init bcma_bus_early_register(struc
3092 bcma_init_bus(bus);
3093
3094 match.manuf = BCMA_MANUF_BCM;
3095 - match.id = BCMA_CORE_CHIPCOMMON;
3096 + match.id = bcma_cc_core_id(bus);
3097 match.class = BCMA_CL_SIM;
3098 match.rev = BCMA_ANY_REV;
3099
3100 /* Scan for chip common core */
3101 err = bcma_bus_scan_early(bus, &match, core_cc);
3102 if (err) {
3103 - pr_err("Failed to scan for common core: %d\n", err);
3104 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
3105 return -1;
3106 }
3107
3108 @@ -215,25 +325,25 @@ int __init bcma_bus_early_register(struc
3109 /* Scan for mips core */
3110 err = bcma_bus_scan_early(bus, &match, core_mips);
3111 if (err) {
3112 - pr_err("Failed to scan for mips core: %d\n", err);
3113 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
3114 return -1;
3115 }
3116
3117 - /* Init CC core */
3118 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3119 + /* Early init CC core */
3120 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3121 if (core) {
3122 bus->drv_cc.core = core;
3123 - bcma_core_chipcommon_init(&bus->drv_cc);
3124 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3125 }
3126
3127 - /* Init MIPS core */
3128 + /* Early init MIPS core */
3129 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3130 if (core) {
3131 bus->drv_mips.core = core;
3132 - bcma_core_mips_init(&bus->drv_mips);
3133 + bcma_core_mips_early_init(&bus->drv_mips);
3134 }
3135
3136 - pr_info("Early bus registered\n");
3137 + bcma_info(bus, "Early bus registered\n");
3138
3139 return 0;
3140 }
3141 @@ -259,8 +369,7 @@ int bcma_bus_resume(struct bcma_bus *bus
3142 struct bcma_device *core;
3143
3144 /* Init CC core */
3145 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3146 - if (core) {
3147 + if (bus->drv_cc.core) {
3148 bus->drv_cc.setup_done = false;
3149 bcma_core_chipcommon_init(&bus->drv_cc);
3150 }
3151 --- a/drivers/bcma/scan.c
3152 +++ b/drivers/bcma/scan.c
3153 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
3154 u16 id;
3155 const char *name;
3156 };
3157 -struct bcma_device_id_name bcma_device_names[] = {
3158 +
3159 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
3160 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
3161 + { BCMA_CORE_ARM_1176, "ARM 1176" },
3162 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3163 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
3164 +};
3165 +
3166 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
3167 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
3168 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
3169 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
3170 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
3171 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
3172 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
3173 { BCMA_CORE_INVALID, "Invalid" },
3174 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
3175 { BCMA_CORE_ILINE20, "ILine 20" },
3176 { BCMA_CORE_SRAM, "SRAM" },
3177 { BCMA_CORE_SDRAM, "SDRAM" },
3178 { BCMA_CORE_PCI, "PCI" },
3179 - { BCMA_CORE_MIPS, "MIPS" },
3180 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
3181 { BCMA_CORE_V90, "V90" },
3182 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
3183 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
3184 { BCMA_CORE_PHY_A, "PHY A" },
3185 { BCMA_CORE_PHY_B, "PHY B" },
3186 { BCMA_CORE_PHY_G, "PHY G" },
3187 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3188 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
3189 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
3190 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
3191 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
3192 { BCMA_CORE_PHY_N, "PHY N" },
3193 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
3194 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
3195 - { BCMA_CORE_ARM_1176, "ARM 1176" },
3196 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3197 { BCMA_CORE_PHY_LP, "PHY LP" },
3198 { BCMA_CORE_PMU, "PMU" },
3199 { BCMA_CORE_PHY_SSN, "PHY SSN" },
3200 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
3201 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
3202 { BCMA_CORE_PHY_HT, "PHY HT" },
3203 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3204 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
3205 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
3206 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
3207 @@ -77,18 +84,45 @@ struct bcma_device_id_name bcma_device_n
3208 { BCMA_CORE_I2S, "I2S" },
3209 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
3210 { BCMA_CORE_SHIM, "SHIM" },
3211 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
3212 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
3213 { BCMA_CORE_DEFAULT, "Default" },
3214 };
3215 -const char *bcma_device_name(struct bcma_device_id *id)
3216 +
3217 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
3218 + { BCMA_CORE_MIPS, "MIPS" },
3219 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3220 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3221 +};
3222 +
3223 +static const char *bcma_device_name(const struct bcma_device_id *id)
3224 {
3225 - int i;
3226 + const struct bcma_device_id_name *names;
3227 + int size, i;
3228
3229 - if (id->manuf == BCMA_MANUF_BCM) {
3230 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
3231 - if (bcma_device_names[i].id == id->id)
3232 - return bcma_device_names[i].name;
3233 - }
3234 + /* search manufacturer specific names */
3235 + switch (id->manuf) {
3236 + case BCMA_MANUF_ARM:
3237 + names = bcma_arm_device_names;
3238 + size = ARRAY_SIZE(bcma_arm_device_names);
3239 + break;
3240 + case BCMA_MANUF_BCM:
3241 + names = bcma_bcm_device_names;
3242 + size = ARRAY_SIZE(bcma_bcm_device_names);
3243 + break;
3244 + case BCMA_MANUF_MIPS:
3245 + names = bcma_mips_device_names;
3246 + size = ARRAY_SIZE(bcma_mips_device_names);
3247 + break;
3248 + default:
3249 + return "UNKNOWN";
3250 }
3251 +
3252 + for (i = 0; i < size; i++) {
3253 + if (names[i].id == id->id)
3254 + return names[i].name;
3255 + }
3256 +
3257 return "UNKNOWN";
3258 }
3259
3260 @@ -105,19 +139,19 @@ static void bcma_scan_switch_core(struct
3261 addr);
3262 }
3263
3264 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
3265 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
3266 {
3267 u32 ent = readl(*eromptr);
3268 (*eromptr)++;
3269 return ent;
3270 }
3271
3272 -static void bcma_erom_push_ent(u32 **eromptr)
3273 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
3274 {
3275 (*eromptr)--;
3276 }
3277
3278 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
3279 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
3280 {
3281 u32 ent = bcma_erom_get_ent(bus, eromptr);
3282 if (!(ent & SCAN_ER_VALID))
3283 @@ -127,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
3284 return ent;
3285 }
3286
3287 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
3288 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
3289 {
3290 u32 ent = bcma_erom_get_ent(bus, eromptr);
3291 bcma_erom_push_ent(eromptr);
3292 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
3293 }
3294
3295 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
3296 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
3297 {
3298 u32 ent = bcma_erom_get_ent(bus, eromptr);
3299 bcma_erom_push_ent(eromptr);
3300 @@ -143,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
3301 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
3302 }
3303
3304 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
3305 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
3306 {
3307 u32 ent;
3308 while (1) {
3309 @@ -157,7 +191,7 @@ static void bcma_erom_skip_component(str
3310 bcma_erom_push_ent(eromptr);
3311 }
3312
3313 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
3314 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
3315 {
3316 u32 ent = bcma_erom_get_ent(bus, eromptr);
3317 if (!(ent & SCAN_ER_VALID))
3318 @@ -167,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
3319 return ent;
3320 }
3321
3322 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
3323 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
3324 u32 type, u8 port)
3325 {
3326 u32 addrl, addrh, sizel, sizeh = 0;
3327 @@ -212,6 +246,17 @@ static struct bcma_device *bcma_find_cor
3328 return NULL;
3329 }
3330
3331 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
3332 +{
3333 + struct bcma_device *core;
3334 +
3335 + list_for_each_entry_reverse(core, &bus->cores, list) {
3336 + if (core->id.id == coreid)
3337 + return core;
3338 + }
3339 + return NULL;
3340 +}
3341 +
3342 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
3343 struct bcma_device_id *match, int core_num,
3344 struct bcma_device *core)
3345 @@ -252,11 +297,15 @@ static int bcma_get_next_core(struct bcm
3346
3347 /* check if component is a core at all */
3348 if (wrappers[0] + wrappers[1] == 0) {
3349 - /* we could save addrl of the router
3350 - if (cid == BCMA_CORE_OOB_ROUTER)
3351 - */
3352 - bcma_erom_skip_component(bus, eromptr);
3353 - return -ENXIO;
3354 + /* Some specific cores don't need wrappers */
3355 + switch (core->id.id) {
3356 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
3357 + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
3358 + break;
3359 + default:
3360 + bcma_erom_skip_component(bus, eromptr);
3361 + return -ENXIO;
3362 + }
3363 }
3364
3365 if (bcma_erom_is_bridge(bus, eromptr)) {
3366 @@ -286,6 +335,23 @@ static int bcma_get_next_core(struct bcm
3367 return -EILSEQ;
3368 }
3369
3370 + /* First Slave Address Descriptor should be port 0:
3371 + * the main register space for the core
3372 + */
3373 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
3374 + if (tmp <= 0) {
3375 + /* Try again to see if it is a bridge */
3376 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
3377 + SCAN_ADDR_TYPE_BRIDGE, 0);
3378 + if (tmp <= 0) {
3379 + return -EILSEQ;
3380 + } else {
3381 + bcma_info(bus, "Bridge found\n");
3382 + return -ENXIO;
3383 + }
3384 + }
3385 + core->addr = tmp;
3386 +
3387 /* get & parse slave ports */
3388 for (i = 0; i < ports[1]; i++) {
3389 for (j = 0; ; j++) {
3390 @@ -298,7 +364,7 @@ static int bcma_get_next_core(struct bcm
3391 break;
3392 } else {
3393 if (i == 0 && j == 0)
3394 - core->addr = tmp;
3395 + core->addr1 = tmp;
3396 }
3397 }
3398 }
3399 @@ -353,6 +419,7 @@ static int bcma_get_next_core(struct bcm
3400 void bcma_init_bus(struct bcma_bus *bus)
3401 {
3402 s32 tmp;
3403 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
3404
3405 if (bus->init_done)
3406 return;
3407 @@ -363,9 +430,12 @@ void bcma_init_bus(struct bcma_bus *bus)
3408 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
3409
3410 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
3411 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3412 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3413 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3414 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3415 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3416 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3417 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
3418 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
3419 +
3420 bus->init_done = true;
3421 }
3422
3423 @@ -392,9 +462,12 @@ int bcma_bus_scan(struct bcma_bus *bus)
3424 bcma_scan_switch_core(bus, erombase);
3425
3426 while (eromptr < eromend) {
3427 + struct bcma_device *other_core;
3428 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
3429 - if (!core)
3430 - return -ENOMEM;
3431 + if (!core) {
3432 + err = -ENOMEM;
3433 + goto out;
3434 + }
3435 INIT_LIST_HEAD(&core->list);
3436 core->bus = bus;
3437
3438 @@ -409,25 +482,28 @@ int bcma_bus_scan(struct bcma_bus *bus)
3439 } else if (err == -ESPIPE) {
3440 break;
3441 }
3442 - return err;
3443 + goto out;
3444 }
3445
3446 core->core_index = core_num++;
3447 bus->nr_cores++;
3448 + other_core = bcma_find_core_reverse(bus, core->id.id);
3449 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
3450
3451 - pr_info("Core %d found: %s "
3452 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3453 - core->core_index, bcma_device_name(&core->id),
3454 - core->id.manuf, core->id.id, core->id.rev,
3455 - core->id.class);
3456 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3457 + core->core_index, bcma_device_name(&core->id),
3458 + core->id.manuf, core->id.id, core->id.rev,
3459 + core->id.class);
3460
3461 - list_add(&core->list, &bus->cores);
3462 + list_add_tail(&core->list, &bus->cores);
3463 }
3464
3465 + err = 0;
3466 +out:
3467 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3468 iounmap(eromptr);
3469
3470 - return 0;
3471 + return err;
3472 }
3473
3474 int __init bcma_bus_scan_early(struct bcma_bus *bus,
3475 @@ -467,21 +543,21 @@ int __init bcma_bus_scan_early(struct bc
3476 else if (err == -ESPIPE)
3477 break;
3478 else if (err < 0)
3479 - return err;
3480 + goto out;
3481
3482 core->core_index = core_num++;
3483 bus->nr_cores++;
3484 - pr_info("Core %d found: %s "
3485 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3486 - core->core_index, bcma_device_name(&core->id),
3487 - core->id.manuf, core->id.id, core->id.rev,
3488 - core->id.class);
3489 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3490 + core->core_index, bcma_device_name(&core->id),
3491 + core->id.manuf, core->id.id, core->id.rev,
3492 + core->id.class);
3493
3494 - list_add(&core->list, &bus->cores);
3495 + list_add_tail(&core->list, &bus->cores);
3496 err = 0;
3497 break;
3498 }
3499
3500 +out:
3501 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3502 iounmap(eromptr);
3503
3504 --- a/drivers/bcma/scan.h
3505 +++ b/drivers/bcma/scan.h
3506 @@ -27,7 +27,7 @@
3507 #define SCAN_CIB_NMW 0x0007C000
3508 #define SCAN_CIB_NMW_SHIFT 14
3509 #define SCAN_CIB_NSW 0x00F80000
3510 -#define SCAN_CIB_NSW_SHIFT 17
3511 +#define SCAN_CIB_NSW_SHIFT 19
3512 #define SCAN_CIB_REV 0xFF000000
3513 #define SCAN_CIB_REV_SHIFT 24
3514
3515 --- a/drivers/bcma/sprom.c
3516 +++ b/drivers/bcma/sprom.c
3517 @@ -2,6 +2,8 @@
3518 * Broadcom specific AMBA
3519 * SPROM reading
3520 *
3521 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3522 + *
3523 * Licensed under the GNU/GPL. See COPYING for details.
3524 */
3525
3526 @@ -14,18 +16,68 @@
3527 #include <linux/dma-mapping.h>
3528 #include <linux/slab.h>
3529
3530 -#define SPOFF(offset) ((offset) / sizeof(u16))
3531 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
3532 +
3533 +/**
3534 + * bcma_arch_register_fallback_sprom - Registers a method providing a
3535 + * fallback SPROM if no SPROM is found.
3536 + *
3537 + * @sprom_callback: The callback function.
3538 + *
3539 + * With this function the architecture implementation may register a
3540 + * callback handler which fills the SPROM data structure. The fallback is
3541 + * used for PCI based BCMA devices, where no valid SPROM can be found
3542 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
3543 + * to controll the system bus.
3544 + *
3545 + * This function is useful for weird architectures that have a half-assed
3546 + * BCMA device hardwired to their PCI bus.
3547 + *
3548 + * This function is available for architecture code, only. So it is not
3549 + * exported.
3550 + */
3551 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
3552 + struct ssb_sprom *out))
3553 +{
3554 + if (get_fallback_sprom)
3555 + return -EEXIST;
3556 + get_fallback_sprom = sprom_callback;
3557 +
3558 + return 0;
3559 +}
3560 +
3561 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
3562 + struct ssb_sprom *out)
3563 +{
3564 + int err;
3565 +
3566 + if (!get_fallback_sprom) {
3567 + err = -ENOENT;
3568 + goto fail;
3569 + }
3570 +
3571 + err = get_fallback_sprom(bus, out);
3572 + if (err)
3573 + goto fail;
3574 +
3575 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
3576 + bus->sprom.revision);
3577 + return 0;
3578 +fail:
3579 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
3580 + return err;
3581 +}
3582
3583 /**************************************************
3584 * R/W ops.
3585 **************************************************/
3586
3587 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
3588 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
3589 + size_t words)
3590 {
3591 int i;
3592 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
3593 - sprom[i] = bcma_read16(bus->drv_cc.core,
3594 - offset + (i * 2));
3595 + for (i = 0; i < words; i++)
3596 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
3597 }
3598
3599 /**************************************************
3600 @@ -72,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
3601 return t[crc ^ data];
3602 }
3603
3604 -static u8 bcma_sprom_crc(const u16 *sprom)
3605 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
3606 {
3607 int word;
3608 u8 crc = 0xFF;
3609
3610 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
3611 + for (word = 0; word < words - 1; word++) {
3612 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
3613 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
3614 }
3615 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
3616 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
3617 crc ^= 0xFF;
3618
3619 return crc;
3620 }
3621
3622 -static int bcma_sprom_check_crc(const u16 *sprom)
3623 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
3624 {
3625 u8 crc;
3626 u8 expected_crc;
3627 u16 tmp;
3628
3629 - crc = bcma_sprom_crc(sprom);
3630 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
3631 + crc = bcma_sprom_crc(sprom, words);
3632 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
3633 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
3634 if (crc != expected_crc)
3635 return -EPROTO;
3636 @@ -102,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
3637 return 0;
3638 }
3639
3640 -static int bcma_sprom_valid(const u16 *sprom)
3641 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
3642 + size_t words)
3643 {
3644 u16 revision;
3645 int err;
3646
3647 - err = bcma_sprom_check_crc(sprom);
3648 + err = bcma_sprom_check_crc(sprom, words);
3649 if (err)
3650 return err;
3651
3652 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
3653 - if (revision != 8 && revision != 9) {
3654 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
3655 + if (revision != 8 && revision != 9 && revision != 10) {
3656 pr_err("Unsupported SPROM revision: %d\n", revision);
3657 return -ENOENT;
3658 }
3659
3660 + bus->sprom.revision = revision;
3661 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
3662 +
3663 return 0;
3664 }
3665
3666 @@ -124,124 +180,439 @@ static int bcma_sprom_valid(const u16 *s
3667 * SPROM extraction.
3668 **************************************************/
3669
3670 +#define SPOFF(offset) ((offset) / sizeof(u16))
3671 +
3672 +#define SPEX(_field, _offset, _mask, _shift) \
3673 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
3674 +
3675 +#define SPEX32(_field, _offset, _mask, _shift) \
3676 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
3677 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
3678 +
3679 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
3680 + do { \
3681 + SPEX(_field[0], _offset + 0, _mask, _shift); \
3682 + SPEX(_field[1], _offset + 2, _mask, _shift); \
3683 + SPEX(_field[2], _offset + 4, _mask, _shift); \
3684 + SPEX(_field[3], _offset + 6, _mask, _shift); \
3685 + SPEX(_field[4], _offset + 8, _mask, _shift); \
3686 + SPEX(_field[5], _offset + 10, _mask, _shift); \
3687 + SPEX(_field[6], _offset + 12, _mask, _shift); \
3688 + SPEX(_field[7], _offset + 14, _mask, _shift); \
3689 + } while (0)
3690 +
3691 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
3692 {
3693 - u16 v;
3694 + u16 v, o;
3695 int i;
3696 -
3697 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
3698 - SSB_SPROM_REVISION_REV;
3699 + u16 pwr_info_offset[] = {
3700 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
3701 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
3702 + };
3703 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
3704 + ARRAY_SIZE(bus->sprom.core_pwr_info));
3705
3706 for (i = 0; i < 3; i++) {
3707 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
3708 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
3709 }
3710
3711 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
3712 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
3713 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
3714 +
3715 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
3716 + SSB_SPROM4_TXPID2G0_SHIFT);
3717 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
3718 + SSB_SPROM4_TXPID2G1_SHIFT);
3719 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
3720 + SSB_SPROM4_TXPID2G2_SHIFT);
3721 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
3722 + SSB_SPROM4_TXPID2G3_SHIFT);
3723 +
3724 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
3725 + SSB_SPROM4_TXPID5GL0_SHIFT);
3726 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
3727 + SSB_SPROM4_TXPID5GL1_SHIFT);
3728 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
3729 + SSB_SPROM4_TXPID5GL2_SHIFT);
3730 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
3731 + SSB_SPROM4_TXPID5GL3_SHIFT);
3732 +
3733 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
3734 + SSB_SPROM4_TXPID5G0_SHIFT);
3735 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
3736 + SSB_SPROM4_TXPID5G1_SHIFT);
3737 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
3738 + SSB_SPROM4_TXPID5G2_SHIFT);
3739 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
3740 + SSB_SPROM4_TXPID5G3_SHIFT);
3741 +
3742 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
3743 + SSB_SPROM4_TXPID5GH0_SHIFT);
3744 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
3745 + SSB_SPROM4_TXPID5GH1_SHIFT);
3746 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
3747 + SSB_SPROM4_TXPID5GH2_SHIFT);
3748 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
3749 + SSB_SPROM4_TXPID5GH3_SHIFT);
3750 +
3751 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
3752 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
3753 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
3754 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
3755 +
3756 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
3757 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
3758 +
3759 + /* Extract cores power info info */
3760 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
3761 + o = pwr_info_offset[i];
3762 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3763 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
3764 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3765 + SSB_SPROM8_2G_MAXP, 0);
3766 +
3767 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
3768 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
3769 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
3770 +
3771 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3772 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
3773 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3774 + SSB_SPROM8_5G_MAXP, 0);
3775 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
3776 + SSB_SPROM8_5GH_MAXP, 0);
3777 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
3778 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
3779 +
3780 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
3781 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
3782 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
3783 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
3784 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
3785 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
3786 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
3787 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
3788 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
3789 + }
3790 +
3791 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
3792 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3793 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
3794 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3795 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
3796 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3797 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
3798 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3799 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
3800 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3801 +
3802 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
3803 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3804 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
3805 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3806 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
3807 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3808 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
3809 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3810 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
3811 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3812 +
3813 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
3814 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
3815 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
3816 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
3817 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
3818 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
3819 + SSB_SPROM8_ITSSI_BG_SHIFT);
3820 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
3821 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
3822 + SSB_SPROM8_ITSSI_A_SHIFT);
3823 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
3824 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
3825 + SSB_SPROM8_MAXP_AL_SHIFT);
3826 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
3827 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
3828 + SSB_SPROM8_GPIOA_P1_SHIFT);
3829 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
3830 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
3831 + SSB_SPROM8_GPIOB_P3_SHIFT);
3832 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
3833 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
3834 + SSB_SPROM8_TRI5G_SHIFT);
3835 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
3836 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
3837 + SSB_SPROM8_TRI5GH_SHIFT);
3838 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
3839 + SSB_SPROM8_RXPO2G_SHIFT);
3840 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
3841 + SSB_SPROM8_RXPO5G_SHIFT);
3842 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
3843 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
3844 + SSB_SPROM8_RSSISMC2G_SHIFT);
3845 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
3846 + SSB_SPROM8_RSSISAV2G_SHIFT);
3847 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
3848 + SSB_SPROM8_BXA2G_SHIFT);
3849 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
3850 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
3851 + SSB_SPROM8_RSSISMC5G_SHIFT);
3852 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
3853 + SSB_SPROM8_RSSISAV5G_SHIFT);
3854 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
3855 + SSB_SPROM8_BXA5G_SHIFT);
3856 +
3857 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
3858 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
3859 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
3860 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
3861 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
3862 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
3863 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
3864 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
3865 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
3866 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
3867 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
3868 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
3869 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
3870 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
3871 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
3872 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
3873 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
3874 +
3875 + /* Extract the antenna gain values. */
3876 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
3877 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
3878 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
3879 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
3880 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
3881 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
3882 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
3883 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
3884 +
3885 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
3886 + SSB_SPROM8_LEDDC_ON_SHIFT);
3887 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
3888 + SSB_SPROM8_LEDDC_OFF_SHIFT);
3889 +
3890 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
3891 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
3892 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
3893 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
3894 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
3895 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
3896 +
3897 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
3898 +
3899 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
3900 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
3901 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
3902 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
3903 +
3904 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
3905 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
3906 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
3907 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
3908 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
3909 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
3910 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
3911 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
3912 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
3913 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
3914 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
3915 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
3916 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
3917 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
3918 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
3919 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
3920 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
3921 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
3922 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
3923 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
3924 +
3925 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
3926 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
3927 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
3928 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
3929 +
3930 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
3931 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
3932 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
3933 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
3934 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
3935 + SSB_SPROM8_TEMPDELTA_PHYCAL,
3936 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
3937 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
3938 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
3939 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
3940 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
3941 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
3942 +}
3943 +
3944 +/*
3945 + * Indicates the presence of external SPROM.
3946 + */
3947 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
3948 +{
3949 + u32 chip_status;
3950 + u32 srom_control;
3951 + u32 present_mask;
3952 +
3953 + if (bus->drv_cc.core->id.rev >= 31) {
3954 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3955 + return false;
3956 +
3957 + srom_control = bcma_read32(bus->drv_cc.core,
3958 + BCMA_CC_SROM_CONTROL);
3959 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
3960 + }
3961 +
3962 + /* older chipcommon revisions use chip status register */
3963 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3964 + switch (bus->chipinfo.id) {
3965 + case BCMA_CHIP_ID_BCM4313:
3966 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
3967 + break;
3968 +
3969 + case BCMA_CHIP_ID_BCM4331:
3970 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
3971 + break;
3972
3973 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3974 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
3975 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3976 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
3977 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3978 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
3979 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3980 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
3981 -
3982 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3983 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
3984 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3985 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
3986 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3987 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
3988 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3989 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
3990 -
3991 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3992 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
3993 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3994 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
3995 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3996 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
3997 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3998 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
3999 -
4000 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
4001 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
4002 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
4003 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
4004 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
4005 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
4006 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
4007 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
4008 -
4009 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
4010 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
4011 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
4012 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
4013 -
4014 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
4015 -
4016 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4017 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
4018 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4019 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
4020 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4021 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
4022 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4023 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
4024 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4025 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
4026 -
4027 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4028 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
4029 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4030 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
4031 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4032 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
4033 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4034 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
4035 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4036 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
4037 + default:
4038 + return true;
4039 + }
4040 +
4041 + return chip_status & present_mask;
4042 +}
4043 +
4044 +/*
4045 + * Indicates that on-chip OTP memory is present and enabled.
4046 + */
4047 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
4048 +{
4049 + u32 chip_status;
4050 + u32 otpsize = 0;
4051 + bool present;
4052 +
4053 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
4054 + switch (bus->chipinfo.id) {
4055 + case BCMA_CHIP_ID_BCM4313:
4056 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
4057 + break;
4058 +
4059 + case BCMA_CHIP_ID_BCM4331:
4060 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
4061 + break;
4062 + case BCMA_CHIP_ID_BCM43142:
4063 + case BCMA_CHIP_ID_BCM43224:
4064 + case BCMA_CHIP_ID_BCM43225:
4065 + /* for these chips OTP is always available */
4066 + present = true;
4067 + break;
4068 + case BCMA_CHIP_ID_BCM43227:
4069 + case BCMA_CHIP_ID_BCM43228:
4070 + case BCMA_CHIP_ID_BCM43428:
4071 + present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
4072 + break;
4073 + default:
4074 + present = false;
4075 + break;
4076 + }
4077 +
4078 + if (present) {
4079 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
4080 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
4081 + }
4082 +
4083 + return otpsize != 0;
4084 +}
4085 +
4086 +/*
4087 + * Verify OTP is filled and determine the byte
4088 + * offset where SPROM data is located.
4089 + *
4090 + * On error, returns 0; byte offset otherwise.
4091 + */
4092 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
4093 +{
4094 + struct bcma_device *cc = bus->drv_cc.core;
4095 + u32 offset;
4096 +
4097 + /* verify OTP status */
4098 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
4099 + return 0;
4100 +
4101 + /* obtain bit offset from otplayout register */
4102 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
4103 + return BCMA_CC_SPROM + (offset >> 3);
4104 }
4105
4106 int bcma_sprom_get(struct bcma_bus *bus)
4107 {
4108 - u16 offset;
4109 + u16 offset = BCMA_CC_SPROM;
4110 u16 *sprom;
4111 - int err = 0;
4112 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
4113 + SSB_SPROMSIZE_WORDS_R10, };
4114 + int i, err = 0;
4115
4116 if (!bus->drv_cc.core)
4117 return -EOPNOTSUPP;
4118
4119 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
4120 - return -ENOENT;
4121 + if (!bcma_sprom_ext_available(bus)) {
4122 + bool sprom_onchip;
4123
4124 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
4125 - GFP_KERNEL);
4126 - if (!sprom)
4127 - return -ENOMEM;
4128 + /*
4129 + * External SPROM takes precedence so check
4130 + * on-chip OTP only when no external SPROM
4131 + * is present.
4132 + */
4133 + sprom_onchip = bcma_sprom_onchip_available(bus);
4134 + if (sprom_onchip) {
4135 + /* determine offset */
4136 + offset = bcma_sprom_onchip_offset(bus);
4137 + }
4138 + if (!offset || !sprom_onchip) {
4139 + /*
4140 + * Maybe there is no SPROM on the device?
4141 + * Now we ask the arch code if there is some sprom
4142 + * available for this device in some other storage.
4143 + */
4144 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
4145 + return err;
4146 + }
4147 + }
4148
4149 - if (bus->chipinfo.id == 0x4331)
4150 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
4151 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
4152 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
4153
4154 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
4155 - * According to brcm80211 this applies to cards with PCIe rev >= 6
4156 - * TODO: understand this condition and use it */
4157 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
4158 - BCMA_CC_SPROM_PCIE6;
4159 - bcma_sprom_read(bus, offset, sprom);
4160 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
4161 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
4162 + size_t words = sprom_sizes[i];
4163 +
4164 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
4165 + if (!sprom)
4166 + return -ENOMEM;
4167 +
4168 + bcma_sprom_read(bus, offset, sprom, words);
4169 + err = bcma_sprom_valid(bus, sprom, words);
4170 + if (!err)
4171 + break;
4172
4173 - if (bus->chipinfo.id == 0x4331)
4174 - bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
4175 + kfree(sprom);
4176 + }
4177
4178 - err = bcma_sprom_valid(sprom);
4179 - if (err)
4180 - goto out;
4181 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
4182 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
4183 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
4184
4185 - bcma_sprom_extract_r8(bus, sprom);
4186 + if (err) {
4187 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
4188 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
4189 + } else {
4190 + bcma_sprom_extract_r8(bus, sprom);
4191 + kfree(sprom);
4192 + }
4193
4194 -out:
4195 - kfree(sprom);
4196 return err;
4197 }
4198 --- a/include/linux/bcma/bcma.h
4199 +++ b/include/linux/bcma/bcma.h
4200 @@ -7,9 +7,10 @@
4201 #include <linux/bcma/bcma_driver_chipcommon.h>
4202 #include <linux/bcma/bcma_driver_pci.h>
4203 #include <linux/bcma/bcma_driver_mips.h>
4204 +#include <linux/bcma/bcma_driver_gmac_cmn.h>
4205 #include <linux/ssb/ssb.h> /* SPROM sharing */
4206
4207 -#include "bcma_regs.h"
4208 +#include <linux/bcma/bcma_regs.h>
4209
4210 struct bcma_device;
4211 struct bcma_bus;
4212 @@ -26,6 +27,11 @@ struct bcma_chipinfo {
4213 u8 pkg;
4214 };
4215
4216 +struct bcma_boardinfo {
4217 + u16 vendor;
4218 + u16 type;
4219 +};
4220 +
4221 enum bcma_clkmode {
4222 BCMA_CLKMODE_FAST,
4223 BCMA_CLKMODE_DYNAMIC,
4224 @@ -65,6 +71,13 @@ struct bcma_host_ops {
4225
4226 /* Core-ID values. */
4227 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
4228 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
4229 +#define BCMA_CORE_4706_SOC_RAM 0x50E
4230 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
4231 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
4232 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
4233 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
4234 +#define BCMA_CORE_DDR23_PHY 0x5DD
4235 #define BCMA_CORE_INVALID 0x700
4236 #define BCMA_CORE_CHIPCOMMON 0x800
4237 #define BCMA_CORE_ILINE20 0x801
4238 @@ -121,10 +134,104 @@ struct bcma_host_ops {
4239 #define BCMA_CORE_I2S 0x834
4240 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
4241 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
4242 +#define BCMA_CORE_PHY_AC 0x83B
4243 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
4244 +#define BCMA_CORE_USB30_DEV 0x83D
4245 +#define BCMA_CORE_ARM_CR4 0x83E
4246 #define BCMA_CORE_DEFAULT 0xFFF
4247
4248 #define BCMA_MAX_NR_CORES 16
4249
4250 +/* Chip IDs of PCIe devices */
4251 +#define BCMA_CHIP_ID_BCM4313 0x4313
4252 +#define BCMA_CHIP_ID_BCM43142 43142
4253 +#define BCMA_CHIP_ID_BCM43224 43224
4254 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
4255 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
4256 +#define BCMA_CHIP_ID_BCM43225 43225
4257 +#define BCMA_CHIP_ID_BCM43227 43227
4258 +#define BCMA_CHIP_ID_BCM43228 43228
4259 +#define BCMA_CHIP_ID_BCM43421 43421
4260 +#define BCMA_CHIP_ID_BCM43428 43428
4261 +#define BCMA_CHIP_ID_BCM43431 43431
4262 +#define BCMA_CHIP_ID_BCM43460 43460
4263 +#define BCMA_CHIP_ID_BCM4331 0x4331
4264 +#define BCMA_CHIP_ID_BCM6362 0x6362
4265 +#define BCMA_CHIP_ID_BCM4360 0x4360
4266 +#define BCMA_CHIP_ID_BCM4352 0x4352
4267 +
4268 +/* Chip IDs of SoCs */
4269 +#define BCMA_CHIP_ID_BCM4706 0x5300
4270 +#define BCMA_PKG_ID_BCM4706L 1
4271 +#define BCMA_CHIP_ID_BCM4716 0x4716
4272 +#define BCMA_PKG_ID_BCM4716 8
4273 +#define BCMA_PKG_ID_BCM4717 9
4274 +#define BCMA_PKG_ID_BCM4718 10
4275 +#define BCMA_CHIP_ID_BCM47162 47162
4276 +#define BCMA_CHIP_ID_BCM4748 0x4748
4277 +#define BCMA_CHIP_ID_BCM4749 0x4749
4278 +#define BCMA_CHIP_ID_BCM5356 0x5356
4279 +#define BCMA_CHIP_ID_BCM5357 0x5357
4280 +#define BCMA_PKG_ID_BCM5358 9
4281 +#define BCMA_PKG_ID_BCM47186 10
4282 +#define BCMA_PKG_ID_BCM5357 11
4283 +#define BCMA_CHIP_ID_BCM53572 53572
4284 +#define BCMA_PKG_ID_BCM47188 9
4285 +
4286 +/* Board types (on PCI usually equals to the subsystem dev id) */
4287 +/* BCM4313 */
4288 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
4289 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
4290 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
4291 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
4292 +/* BCM4716 */
4293 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
4294 +/* BCM43224 */
4295 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
4296 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
4297 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
4298 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
4299 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
4300 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
4301 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
4302 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
4303 +/* BCM43228 */
4304 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
4305 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
4306 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
4307 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
4308 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
4309 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
4310 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
4311 +/* BCM4331 */
4312 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
4313 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
4314 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
4315 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
4316 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
4317 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
4318 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
4319 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
4320 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
4321 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
4322 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
4323 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
4324 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
4325 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
4326 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
4327 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
4328 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
4329 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
4330 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
4331 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
4332 +/* BCM53572 */
4333 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
4334 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
4335 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
4336 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
4337 +/* BCM43142 */
4338 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
4339 +
4340 struct bcma_device {
4341 struct bcma_bus *bus;
4342 struct bcma_device_id id;
4343 @@ -136,8 +243,10 @@ struct bcma_device {
4344 bool dev_registered;
4345
4346 u8 core_index;
4347 + u8 core_unit;
4348
4349 u32 addr;
4350 + u32 addr1;
4351 u32 wrap;
4352
4353 void __iomem *io_addr;
4354 @@ -175,6 +284,12 @@ int __bcma_driver_register(struct bcma_d
4355
4356 extern void bcma_driver_unregister(struct bcma_driver *drv);
4357
4358 +/* Set a fallback SPROM.
4359 + * See kdoc at the function definition for complete documentation. */
4360 +extern int bcma_arch_register_fallback_sprom(
4361 + int (*sprom_callback)(struct bcma_bus *bus,
4362 + struct ssb_sprom *out));
4363 +
4364 struct bcma_bus {
4365 /* The MMIO area. */
4366 void __iomem *mmio;
4367 @@ -191,14 +306,18 @@ struct bcma_bus {
4368
4369 struct bcma_chipinfo chipinfo;
4370
4371 + struct bcma_boardinfo boardinfo;
4372 +
4373 struct bcma_device *mapped_core;
4374 struct list_head cores;
4375 u8 nr_cores;
4376 u8 init_done:1;
4377 + u8 num;
4378
4379 struct bcma_drv_cc drv_cc;
4380 - struct bcma_drv_pci drv_pci;
4381 + struct bcma_drv_pci drv_pci[2];
4382 struct bcma_drv_mips drv_mips;
4383 + struct bcma_drv_gmac_cmn drv_gmac_cmn;
4384
4385 /* We decided to share SPROM struct with SSB as long as we do not need
4386 * any hacks for BCMA. This simplifies drivers code. */
4387 @@ -282,6 +401,7 @@ static inline void bcma_maskset16(struct
4388 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
4389 }
4390
4391 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
4392 extern bool bcma_core_is_enabled(struct bcma_device *core);
4393 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
4394 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
4395 @@ -289,6 +409,7 @@ extern void bcma_core_set_clockmode(stru
4396 enum bcma_clkmode clkmode);
4397 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
4398 bool on);
4399 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
4400 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
4401 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
4402 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
4403 --- a/include/linux/bcma/bcma_driver_chipcommon.h
4404 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
4405 @@ -1,6 +1,9 @@
4406 #ifndef LINUX_BCMA_DRIVER_CC_H_
4407 #define LINUX_BCMA_DRIVER_CC_H_
4408
4409 +#include <linux/platform_device.h>
4410 +#include <linux/gpio.h>
4411 +
4412 /** ChipCommon core registers. **/
4413 #define BCMA_CC_ID 0x0000
4414 #define BCMA_CC_ID_ID 0x0000FFFF
4415 @@ -24,7 +27,7 @@
4416 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
4417 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
4418 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
4419 -#define BCMA_CC_FLASHT_NFLASH 0x00000200
4420 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
4421 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
4422 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
4423 #define BCMA_PLLTYPE_NONE 0x00000000
4424 @@ -45,6 +48,7 @@
4425 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
4426 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
4427 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
4428 +#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
4429 #define BCMA_CC_CORECTL 0x0008
4430 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
4431 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
4432 @@ -56,6 +60,9 @@
4433 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
4434 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
4435 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
4436 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
4437 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
4438 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
4439 #define BCMA_CC_OTPC 0x0014 /* OTP control */
4440 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
4441 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
4442 @@ -72,6 +79,8 @@
4443 #define BCMA_CC_OTPP_READ 0x40000000
4444 #define BCMA_CC_OTPP_START 0x80000000
4445 #define BCMA_CC_OTPP_BUSY 0x80000000
4446 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
4447 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
4448 #define BCMA_CC_IRQSTAT 0x0020
4449 #define BCMA_CC_IRQMASK 0x0024
4450 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
4451 @@ -79,6 +88,23 @@
4452 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
4453 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
4454 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
4455 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
4456 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
4457 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
4458 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
4459 +#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
4460 +#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
4461 +#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
4462 +#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
4463 +#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
4464 +#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
4465 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
4466 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
4467 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
4468 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
4469 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
4470 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
4471 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
4472 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
4473 #define BCMA_CC_JCMD_START 0x80000000
4474 #define BCMA_CC_JCMD_BUSY 0x80000000
4475 @@ -108,10 +134,58 @@
4476 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
4477 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
4478 #define BCMA_CC_FLASHCTL 0x0040
4479 +/* Start/busy bit in flashcontrol */
4480 +#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
4481 +#define BCMA_CC_FLASHCTL_ACTION 0x00000700
4482 +#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
4483 #define BCMA_CC_FLASHCTL_START 0x80000000
4484 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
4485 +/* Flashcontrol action + opcodes for ST flashes */
4486 +#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
4487 +#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
4488 +#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
4489 +#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
4490 +#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
4491 +#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
4492 +#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
4493 +#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
4494 +#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
4495 +#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
4496 +#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
4497 +#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
4498 +/* Flashcontrol action + opcodes for Atmel flashes */
4499 +#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
4500 +#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
4501 +#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
4502 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
4503 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
4504 +#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
4505 +#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
4506 +#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
4507 +#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
4508 +#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
4509 +#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
4510 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
4511 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
4512 +#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
4513 +#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
4514 +#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
4515 +#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
4516 +#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
4517 +#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
4518 #define BCMA_CC_FLASHADDR 0x0044
4519 #define BCMA_CC_FLASHDATA 0x0048
4520 +/* Status register bits for ST flashes */
4521 +#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
4522 +#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
4523 +#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
4524 +#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
4525 +#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
4526 +/* Status register bits for Atmel flashes */
4527 +#define BCMA_CC_FLASHDATA_AT_READY 0x80
4528 +#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
4529 +#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
4530 +#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
4531 #define BCMA_CC_BCAST_ADDR 0x0050
4532 #define BCMA_CC_BCAST_DATA 0x0054
4533 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
4534 @@ -181,6 +255,45 @@
4535 #define BCMA_CC_FLASH_CFG 0x0128
4536 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
4537 #define BCMA_CC_FLASH_WAITCNT 0x012C
4538 +#define BCMA_CC_SROM_CONTROL 0x0190
4539 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
4540 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
4541 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
4542 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
4543 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
4544 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
4545 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
4546 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
4547 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
4548 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
4549 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
4550 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
4551 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
4552 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
4553 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
4554 +/* Block 0x140 - 0x190 registers are chipset specific */
4555 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
4556 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
4557 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
4558 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
4559 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
4560 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
4561 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
4562 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
4563 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
4564 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
4565 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
4566 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
4567 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
4568 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
4569 +/* NAND flash registers for BCM4706 (corerev = 31) */
4570 +#define BCMA_CC_NFLASH_CTL 0x01A0
4571 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
4572 +#define BCMA_CC_NFLASH_CONF 0x01A4
4573 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
4574 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
4575 +#define BCMA_CC_NFLASH_DATA 0x01B0
4576 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
4577 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
4578 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
4579 #define BCMA_CC_UART0_DATA 0x0300
4580 @@ -203,6 +316,9 @@
4581 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
4582 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
4583 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
4584 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
4585 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
4586 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
4587 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
4588 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
4589 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
4590 @@ -214,6 +330,8 @@
4591 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
4592 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
4593 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
4594 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
4595 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
4596 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
4597 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
4598 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
4599 @@ -239,8 +357,66 @@
4600 #define BCMA_CC_REGCTL_DATA 0x065C
4601 #define BCMA_CC_PLLCTL_ADDR 0x0660
4602 #define BCMA_CC_PLLCTL_DATA 0x0664
4603 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
4604 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
4605 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
4606 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
4607 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
4608 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
4609 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
4610 +/* NAND flash MLC controller registers (corerev >= 38) */
4611 +#define BCMA_CC_NAND_REVISION 0x0C00
4612 +#define BCMA_CC_NAND_CMD_START 0x0C04
4613 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
4614 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
4615 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
4616 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
4617 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
4618 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
4619 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
4620 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
4621 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
4622 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
4623 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
4624 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
4625 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
4626 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
4627 +#define BCMA_CC_NAND_CONFIG 0x0C48
4628 +#define BCMA_CC_NAND_TIMING_1 0x0C50
4629 +#define BCMA_CC_NAND_TIMING_2 0x0C54
4630 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
4631 +#define BCMA_CC_NAND_DEVID 0x0C60
4632 +#define BCMA_CC_NAND_DEVID_X 0x0C64
4633 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
4634 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
4635 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
4636 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
4637 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
4638 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
4639 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
4640 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
4641 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
4642 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
4643 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
4644 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
4645 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
4646 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
4647 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
4648 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
4649 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
4650 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
4651 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
4652 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
4653 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
4654 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
4655 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
4656 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
4657 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
4658 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
4659 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
4660 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
4661 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
4662 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
4663 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
4664
4665 /* Divider allocation in 4716/47162/5356 */
4666 #define BCMA_CC_PMU5_MAINPLL_CPU 1
4667 @@ -256,6 +432,32 @@
4668
4669 /* 4706 PMU */
4670 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
4671 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
4672 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
4673 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
4674 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
4675 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
4676 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
4677 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
4678 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
4679 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
4680 +
4681 +/* PMU rev 15 */
4682 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
4683 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
4684 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
4685 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
4686 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
4687 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
4688 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
4689 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
4690 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
4691 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
4692 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
4693 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
4694 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
4695 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
4696 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
4697
4698 /* ALP clock on pre-PMU chips */
4699 #define BCMA_CC_PMU_ALP_CLOCK 20000000
4700 @@ -284,6 +486,19 @@
4701 #define BCMA_CC_PPL_PCHI_OFF 5
4702 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
4703
4704 +#define BCMA_CC_PMU_PLL_CTL0 0
4705 +#define BCMA_CC_PMU_PLL_CTL1 1
4706 +#define BCMA_CC_PMU_PLL_CTL2 2
4707 +#define BCMA_CC_PMU_PLL_CTL3 3
4708 +#define BCMA_CC_PMU_PLL_CTL4 4
4709 +#define BCMA_CC_PMU_PLL_CTL5 5
4710 +
4711 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
4712 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
4713 +
4714 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
4715 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
4716 +
4717 /* BCM4331 ChipControl numbers. */
4718 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
4719 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
4720 @@ -297,9 +512,56 @@
4721 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
4722 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
4723 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
4724 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
4725 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
4726 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
4727
4728 +/* 43224 chip-specific ChipControl register bits */
4729 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
4730 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
4731 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
4732 +
4733 +/* 4313 Chip specific ChipControl register bits */
4734 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
4735 +
4736 +/* BCM5357 ChipControl register bits */
4737 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
4738 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
4739 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
4740 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
4741 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
4742 +
4743 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
4744 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
4745 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
4746 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
4747 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
4748 +#define BCMA_RES_4314_CLDO_PU BIT(5)
4749 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
4750 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
4751 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
4752 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
4753 +#define BCMA_RES_4314_OTP_PU BIT(10)
4754 +#define BCMA_RES_4314_XTAL_PU BIT(11)
4755 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
4756 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
4757 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
4758 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
4759 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
4760 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
4761 +#define BCMA_RES_4314_ILP_REQ BIT(18)
4762 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
4763 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
4764 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
4765 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
4766 +#define BCMA_RES_4314_RADIO_PU BIT(23)
4767 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
4768 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
4769 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
4770 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
4771 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
4772 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
4773 +
4774 /* Data for the PMU, if available.
4775 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
4776 */
4777 @@ -330,6 +592,7 @@ struct bcma_drv_cc {
4778 u32 capabilities;
4779 u32 capabilities_ext;
4780 u8 setup_done:1;
4781 + u8 early_setup_done:1;
4782 /* Fast Powerup Delay constant */
4783 u16 fast_pwrup_delay;
4784 struct bcma_chipcommon_pmu pmu;
4785 @@ -339,6 +602,14 @@ struct bcma_drv_cc {
4786 int nr_serial_ports;
4787 struct bcma_serial_port serial_ports[4];
4788 #endif /* CONFIG_BCMA_DRIVER_MIPS */
4789 + u32 ticks_per_ms;
4790 + struct platform_device *watchdog;
4791 +
4792 + /* Lock for GPIO register access. */
4793 + spinlock_t gpio_lock;
4794 +#ifdef CONFIG_BCMA_DRIVER_GPIO
4795 + struct gpio_chip gpio;
4796 +#endif
4797 };
4798
4799 /* Register access */
4800 @@ -355,14 +626,16 @@ struct bcma_drv_cc {
4801 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
4802
4803 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
4804 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
4805
4806 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
4807 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
4808
4809 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
4810
4811 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
4812 - u32 ticks);
4813 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
4814 +
4815 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
4816
4817 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4818
4819 @@ -375,9 +648,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
4820 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
4821 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4822 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
4823 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
4824 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
4825
4826 /* PMU support */
4827 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
4828 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
4829
4830 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
4831 u32 value);
4832 @@ -387,5 +663,8 @@ extern void bcma_chipco_chipctl_maskset(
4833 u32 offset, u32 mask, u32 set);
4834 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
4835 u32 offset, u32 mask, u32 set);
4836 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
4837 +
4838 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
4839
4840 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
4841 --- /dev/null
4842 +++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
4843 @@ -0,0 +1,100 @@
4844 +#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
4845 +#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
4846 +
4847 +#include <linux/types.h>
4848 +
4849 +#define BCMA_GMAC_CMN_STAG0 0x000
4850 +#define BCMA_GMAC_CMN_STAG1 0x004
4851 +#define BCMA_GMAC_CMN_STAG2 0x008
4852 +#define BCMA_GMAC_CMN_STAG3 0x00C
4853 +#define BCMA_GMAC_CMN_PARSER_CTL 0x020
4854 +#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
4855 +#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
4856 +#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
4857 +#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
4858 +#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
4859 +#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
4860 +#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
4861 +#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
4862 +#define BCMA_GMAC_CMN_PA_START 0x40000000
4863 +#define BCMA_GMAC_CMN_PHY_CTL 0x104
4864 +#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
4865 +#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
4866 +#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
4867 +#define BCMA_GMAC_CMN_PC_MTE 0x00800000
4868 +#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
4869 +#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
4870 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
4871 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
4872 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
4873 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
4874 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
4875 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
4876 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
4877 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
4878 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
4879 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
4880 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
4881 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
4882 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
4883 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
4884 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
4885 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
4886 +#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
4887 +#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
4888 +#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
4889 +#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
4890 +#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
4891 +#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
4892 +#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
4893 +#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
4894 +#define BCMA_GMAC_CMN_UDF_0_A8 0x308
4895 +#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
4896 +#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
4897 +#define BCMA_GMAC_CMN_UDF_1_A8 0x318
4898 +#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
4899 +#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
4900 +#define BCMA_GMAC_CMN_UDF_2_A8 0x328
4901 +#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
4902 +#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
4903 +#define BCMA_GMAC_CMN_UDF_0_B8 0x338
4904 +#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
4905 +#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
4906 +#define BCMA_GMAC_CMN_UDF_1_B8 0x348
4907 +#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
4908 +#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
4909 +#define BCMA_GMAC_CMN_UDF_2_B8 0x358
4910 +#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
4911 +#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
4912 +#define BCMA_GMAC_CMN_UDF_0_C8 0x368
4913 +#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
4914 +#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
4915 +#define BCMA_GMAC_CMN_UDF_1_C8 0x378
4916 +#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
4917 +#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
4918 +#define BCMA_GMAC_CMN_UDF_2_C8 0x388
4919 +#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
4920 +#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
4921 +#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
4922 +
4923 +struct bcma_drv_gmac_cmn {
4924 + struct bcma_device *core;
4925 +
4926 + /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
4927 + * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
4928 + struct mutex phy_mutex;
4929 +};
4930 +
4931 +/* Register access */
4932 +#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
4933 +#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
4934 +#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
4935 +#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
4936 +
4937 +#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
4938 +extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
4939 +#else
4940 +static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
4941 +#endif
4942 +
4943 +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
4944 --- a/include/linux/bcma/bcma_driver_mips.h
4945 +++ b/include/linux/bcma/bcma_driver_mips.h
4946 @@ -28,6 +28,7 @@
4947 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
4948 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
4949
4950 +#define BCMA_MIPS_OOBSELINA74 0x004
4951 #define BCMA_MIPS_OOBSELOUTA30 0x100
4952
4953 struct bcma_device;
4954 @@ -35,17 +36,24 @@ struct bcma_device;
4955 struct bcma_drv_mips {
4956 struct bcma_device *core;
4957 u8 setup_done:1;
4958 - unsigned int assigned_irqs;
4959 + u8 early_setup_done:1;
4960 };
4961
4962 #ifdef CONFIG_BCMA_DRIVER_MIPS
4963 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
4964 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
4965 +
4966 +extern unsigned int bcma_core_irq(struct bcma_device *core);
4967 #else
4968 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
4969 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
4970 +
4971 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
4972 +{
4973 + return 0;
4974 +}
4975 #endif
4976
4977 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
4978
4979 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
4980 -
4981 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
4982 --- a/include/linux/bcma/bcma_driver_pci.h
4983 +++ b/include/linux/bcma/bcma_driver_pci.h
4984 @@ -53,11 +53,47 @@ struct pci_dev;
4985 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
4986 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
4987 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
4988 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
4989 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
4990 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
4991 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
4992 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
4993 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
4994 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
4995 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
4996 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
4997 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
4998 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
4999 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
5000 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
5001 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
5002 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
5003 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
5004 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
5005 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
5006 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
5007 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
5008 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
5009 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
5010 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
5011 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
5012 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
5013 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
5014 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
5015 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
5016 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
5017 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
5018 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
5019 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
5020 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
5021 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
5022 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
5023 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
5024 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
5025 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
5026 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
5027 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
5028 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
5029
5030 /* SBtoPCIx */
5031 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
5032 @@ -72,20 +108,120 @@ struct pci_dev;
5033 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
5034 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
5035
5036 +/* PCIE protocol PHY diagnostic registers */
5037 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
5038 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
5039 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
5040 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
5041 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
5042 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
5043 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
5044 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
5045 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
5046 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
5047 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
5048 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
5049 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
5050 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
5051 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
5052 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
5053 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
5054 +
5055 +/* PCIE protocol DLLP diagnostic registers */
5056 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
5057 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
5058 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
5059 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
5060 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
5061 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
5062 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
5063 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
5064 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
5065 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
5066 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
5067 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
5068 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
5069 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
5070 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
5071 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
5072 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
5073 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
5074 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
5075 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
5076 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
5077 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
5078 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
5079 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
5080 +
5081 +/* SERDES RX registers */
5082 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
5083 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
5084 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
5085 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
5086 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
5087 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
5088 +
5089 +/* SERDES PLL registers */
5090 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
5091 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
5092 +
5093 /* PCIcore specific boardflags */
5094 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
5095
5096 +/* PCIE Config space accessing MACROS */
5097 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
5098 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
5099 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
5100 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
5101 +
5102 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
5103 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
5104 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
5105 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
5106 +
5107 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
5108 +
5109 +/* PCIE Root Capability Register bits (Host mode only) */
5110 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
5111 +
5112 +struct bcma_drv_pci;
5113 +
5114 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
5115 +struct bcma_drv_pci_host {
5116 + struct bcma_drv_pci *pdev;
5117 +
5118 + u32 host_cfg_addr;
5119 + spinlock_t cfgspace_lock;
5120 +
5121 + struct pci_controller pci_controller;
5122 + struct pci_ops pci_ops;
5123 + struct resource mem_resource;
5124 + struct resource io_resource;
5125 +};
5126 +#endif
5127 +
5128 struct bcma_drv_pci {
5129 struct bcma_device *core;
5130 u8 setup_done:1;
5131 + u8 hostmode:1;
5132 +
5133 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
5134 + struct bcma_drv_pci_host *host_controller;
5135 +#endif
5136 };
5137
5138 /* Register access */
5139 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
5140 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
5141 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
5142 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
5143
5144 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
5145 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
5146 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
5147 struct bcma_device *core, bool enable);
5148 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
5149 +
5150 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
5151 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
5152
5153 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
5154 --- a/include/linux/bcma/bcma_regs.h
5155 +++ b/include/linux/bcma/bcma_regs.h
5156 @@ -11,11 +11,13 @@
5157 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
5158 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
5159 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
5160 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
5161 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
5162 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
5163 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
5164 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
5165 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
5166 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
5167 /* Is there any BCM4328 on BCMA bus? */
5168 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
5169 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
5170 @@ -35,6 +37,7 @@
5171 #define BCMA_IOST_BIST_DONE 0x8000
5172 #define BCMA_RESET_CTL 0x0800
5173 #define BCMA_RESET_CTL_RESET 0x0001
5174 +#define BCMA_RESET_ST 0x0804
5175
5176 /* BCMA PCI config space registers. */
5177 #define BCMA_PCI_PMCSR 0x44
5178 @@ -56,4 +59,31 @@
5179 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5180 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5181
5182 +/* SiliconBackplane Address Map.
5183 + * All regions may not exist on all chips.
5184 + */
5185 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
5186 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
5187 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
5188 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
5189 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
5190 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
5191 +
5192 +
5193 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
5194 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
5195 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
5196 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
5197 + * (2 ZettaBytes), low 32 bits
5198 + */
5199 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
5200 + * (2 ZettaBytes), high 32 bits
5201 + */
5202 +
5203 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
5204 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
5205 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
5206 + * (2 ZettaBytes), high 32 bits
5207 + */
5208 +
5209 #endif /* LINUX_BCMA_REGS_H_ */
5210 --- a/drivers/net/wireless/b43/main.c
5211 +++ b/drivers/net/wireless/b43/main.c
5212 @@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct
5213 switch (dev->dev->bus_type) {
5214 #ifdef CONFIG_B43_BCMA
5215 case B43_BUS_BCMA:
5216 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
5217 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
5218 dev->dev->bdev, true);
5219 break;
5220 #endif
5221 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
5222 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
5223 @@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st
5224
5225 /* fixup necessary chip/core configurations */
5226 if (!sii->pch) {
5227 - sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
5228 + sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core);
5229 if (sii->pch == NULL)
5230 return false;
5231 }
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