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kernel: update linux 3.8 to 3.8.9
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.8 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/bcma_private.h
13 +++ b/drivers/bcma/bcma_private.h
14 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
15 int bcma_bus_suspend(struct bcma_bus *bus);
16 int bcma_bus_resume(struct bcma_bus *bus);
17 #endif
18 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
19 + u8 unit);
20
21 /* scan.c */
22 int bcma_bus_scan(struct bcma_bus *bus);
23 @@ -45,6 +47,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
24 /* driver_chipcommon.c */
25 #ifdef CONFIG_BCMA_DRIVER_MIPS
26 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
27 +extern struct platform_device bcma_pflash_dev;
28 #endif /* CONFIG_BCMA_DRIVER_MIPS */
29
30 /* driver_chipcommon_pmu.c */
31 --- a/drivers/bcma/driver_chipcommon.c
32 +++ b/drivers/bcma/driver_chipcommon.c
33 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
34 return value;
35 }
36
37 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
38 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
39 {
40 if (cc->capabilities & BCMA_CC_CAP_PMU)
41 return bcma_pmu_get_alp_clock(cc);
42
43 return 20000000;
44 }
45 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
46
47 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
48 {
49 @@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
50
51 return res;
52 }
53 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
54
55 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
56 {
57 @@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
58
59 return res;
60 }
61 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
62
63 /*
64 * If the bit is set to 0, chipcommon controlls this GPIO,
65 @@ -329,7 +332,7 @@ void bcma_chipco_serial_init(struct bcma
66 return;
67 }
68
69 - irq = bcma_core_mips_irq(cc->core);
70 + irq = bcma_core_irq(cc->core);
71
72 /* Determine the registers of the UARTs */
73 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
74 --- a/drivers/bcma/driver_chipcommon_nflash.c
75 +++ b/drivers/bcma/driver_chipcommon_nflash.c
76 @@ -5,11 +5,11 @@
77 * Licensed under the GNU/GPL. See COPYING for details.
78 */
79
80 +#include "bcma_private.h"
81 +
82 #include <linux/platform_device.h>
83 #include <linux/bcma/bcma.h>
84
85 -#include "bcma_private.h"
86 -
87 struct platform_device bcma_nflash_dev = {
88 .name = "bcma_nflash",
89 .num_resources = 0,
90 --- a/drivers/bcma/driver_chipcommon_sflash.c
91 +++ b/drivers/bcma/driver_chipcommon_sflash.c
92 @@ -5,11 +5,11 @@
93 * Licensed under the GNU/GPL. See COPYING for details.
94 */
95
96 +#include "bcma_private.h"
97 +
98 #include <linux/platform_device.h>
99 #include <linux/bcma/bcma.h>
100
101 -#include "bcma_private.h"
102 -
103 static struct resource bcma_sflash_resource = {
104 .name = "bcma_sflash",
105 .start = BCMA_SOC_FLASH2,
106 --- a/drivers/bcma/driver_gpio.c
107 +++ b/drivers/bcma/driver_gpio.c
108 @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
109 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
110 }
111
112 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
113 +{
114 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
115 +
116 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
117 + return bcma_core_irq(cc->core);
118 + else
119 + return -EINVAL;
120 +}
121 +
122 int bcma_gpio_init(struct bcma_drv_cc *cc)
123 {
124 struct gpio_chip *chip = &cc->gpio;
125 @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
126 chip->set = bcma_gpio_set_value;
127 chip->direction_input = bcma_gpio_direction_input;
128 chip->direction_output = bcma_gpio_direction_output;
129 + chip->to_irq = bcma_gpio_to_irq;
130 chip->ngpio = 16;
131 /* There is just one SoC in one device and its GPIO addresses should be
132 * deterministic to address them more easily. The other buses could get
133 --- a/drivers/bcma/driver_mips.c
134 +++ b/drivers/bcma/driver_mips.c
135 @@ -14,11 +14,33 @@
136
137 #include <linux/bcma/bcma.h>
138
139 +#include <linux/mtd/physmap.h>
140 +#include <linux/platform_device.h>
141 #include <linux/serial.h>
142 #include <linux/serial_core.h>
143 #include <linux/serial_reg.h>
144 #include <linux/time.h>
145
146 +static const char *part_probes[] = { "bcm47xxpart", NULL };
147 +
148 +static struct physmap_flash_data bcma_pflash_data = {
149 + .part_probe_types = part_probes,
150 +};
151 +
152 +static struct resource bcma_pflash_resource = {
153 + .name = "bcma_pflash",
154 + .flags = IORESOURCE_MEM,
155 +};
156 +
157 +struct platform_device bcma_pflash_dev = {
158 + .name = "physmap-flash",
159 + .dev = {
160 + .platform_data = &bcma_pflash_data,
161 + },
162 + .resource = &bcma_pflash_resource,
163 + .num_resources = 1,
164 +};
165 +
166 /* The 47162a0 hangs when reading MIPS DMP registers registers */
167 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
168 {
169 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
170 return dev->core_index;
171 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
172
173 - return flag & 0x1F;
174 + if (flag)
175 + return flag & 0x1F;
176 + else
177 + return 0x3f;
178 }
179
180 /* Get the MIPS IRQ assignment for a specified device.
181 * If unassigned, 0 is returned.
182 + * If disabled, 5 is returned.
183 + * If not supported, 6 is returned.
184 */
185 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
186 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
187 {
188 struct bcma_device *mdev = dev->bus->drv_mips.core;
189 u32 irqflag;
190 unsigned int irq;
191
192 irqflag = bcma_core_mips_irqflag(dev);
193 + if (irqflag == 0x3f)
194 + return 6;
195
196 - for (irq = 1; irq <= 4; irq++)
197 + for (irq = 0; irq <= 4; irq++)
198 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
199 (1 << irqflag))
200 return irq;
201
202 - return 0;
203 + return 5;
204 }
205 -EXPORT_SYMBOL(bcma_core_mips_irq);
206 +
207 +unsigned int bcma_core_irq(struct bcma_device *dev)
208 +{
209 + unsigned int mips_irq = bcma_core_mips_irq(dev);
210 + return mips_irq <= 4 ? mips_irq + 2 : 0;
211 +}
212 +EXPORT_SYMBOL(bcma_core_irq);
213
214 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
215 {
216 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
217 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
218 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
219 ~(1 << irqflag));
220 - else
221 + else if (oldirq != 5)
222 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
223
224 /* assign the new one */
225 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
226 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
227 (1 << irqflag));
228 } else {
229 - u32 oldirqflag = bcma_read32(mdev,
230 - BCMA_MIPS_MIPS74K_INTMASK(irq));
231 - if (oldirqflag) {
232 + u32 irqinitmask = bcma_read32(mdev,
233 + BCMA_MIPS_MIPS74K_INTMASK(irq));
234 + if (irqinitmask) {
235 struct bcma_device *core;
236
237 /* backplane irq line is in use, find out who uses
238 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
239 */
240 list_for_each_entry(core, &bus->cores, list) {
241 if ((1 << bcma_core_mips_irqflag(core)) ==
242 - oldirqflag) {
243 + irqinitmask) {
244 bcma_core_mips_set_irq(core, 0);
245 break;
246 }
247 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
248 1 << irqflag);
249 }
250
251 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
252 - dev->id.id, oldirq + 2, irq + 2);
253 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
254 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
255 +}
256 +
257 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
258 + u16 coreid, u8 unit)
259 +{
260 + struct bcma_device *core;
261 +
262 + core = bcma_find_core_unit(bus, coreid, unit);
263 + if (!core) {
264 + bcma_warn(bus,
265 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
266 + coreid, unit);
267 + return;
268 + }
269 +
270 + bcma_core_mips_set_irq(core, irq);
271 }
272
273 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
274 {
275 int i;
276 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
277 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
278 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
279 for (i = 0; i <= 6; i++)
280 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
281 printk("\n");
282 @@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
283 {
284 struct bcma_bus *bus = mcore->core->bus;
285 struct bcma_drv_cc *cc = &bus->drv_cc;
286 + struct bcma_pflash *pflash = &cc->pflash;
287
288 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
289 case BCMA_CC_FLASHT_STSER:
290 @@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
291 break;
292 case BCMA_CC_FLASHT_PARA:
293 bcma_debug(bus, "Found parallel flash\n");
294 - cc->pflash.present = true;
295 - cc->pflash.window = BCMA_SOC_FLASH2;
296 - cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
297 + pflash->present = true;
298 + pflash->window = BCMA_SOC_FLASH2;
299 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
300
301 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
302 BCMA_CC_FLASH_CFG_DS) == 0)
303 - cc->pflash.buswidth = 1;
304 + pflash->buswidth = 1;
305 else
306 - cc->pflash.buswidth = 2;
307 + pflash->buswidth = 2;
308 +
309 + bcma_pflash_data.width = pflash->buswidth;
310 + bcma_pflash_resource.start = pflash->window;
311 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
312 +
313 break;
314 default:
315 bcma_err(bus, "Flash type not supported\n");
316 @@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
317 mcore->early_setup_done = true;
318 }
319
320 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
321 +{
322 + struct bcma_device *cpu, *pcie, *i2s;
323 +
324 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
325 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
326 + */
327 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
328 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
329 + return;
330 +
331 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
332 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
333 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
334 + if (cpu && pcie && i2s &&
335 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
336 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
337 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
338 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
339 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
340 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
341 + bcma_debug(bus,
342 + "Moved i2s interrupt to oob line 7 instead of 8\n");
343 + }
344 +}
345 +
346 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
347 {
348 struct bcma_bus *bus;
349 @@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
350 if (mcore->setup_done)
351 return;
352
353 - bcma_info(bus, "Initializing MIPS core...\n");
354 + bcma_debug(bus, "Initializing MIPS core...\n");
355
356 bcma_core_mips_early_init(mcore);
357
358 - mcore->assigned_irqs = 1;
359 + bcma_fix_i2s_irqflag(bus);
360
361 - /* Assign IRQs to all cores on the bus */
362 - list_for_each_entry(core, &bus->cores, list) {
363 - int mips_irq;
364 - if (core->irq)
365 - continue;
366 -
367 - mips_irq = bcma_core_mips_irq(core);
368 - if (mips_irq > 4)
369 - core->irq = 0;
370 - else
371 - core->irq = mips_irq + 2;
372 - if (core->irq > 5)
373 - continue;
374 - switch (core->id.id) {
375 - case BCMA_CORE_PCI:
376 - case BCMA_CORE_PCIE:
377 - case BCMA_CORE_ETHERNET:
378 - case BCMA_CORE_ETHERNET_GBIT:
379 - case BCMA_CORE_MAC_GBIT:
380 - case BCMA_CORE_80211:
381 - case BCMA_CORE_USB20_HOST:
382 - /* These devices get their own IRQ line if available,
383 - * the rest goes on IRQ0
384 - */
385 - if (mcore->assigned_irqs <= 4)
386 - bcma_core_mips_set_irq(core,
387 - mcore->assigned_irqs++);
388 - break;
389 + switch (bus->chipinfo.id) {
390 + case BCMA_CHIP_ID_BCM4716:
391 + case BCMA_CHIP_ID_BCM4748:
392 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
393 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
394 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
395 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
396 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
397 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
398 + break;
399 + case BCMA_CHIP_ID_BCM5356:
400 + case BCMA_CHIP_ID_BCM47162:
401 + case BCMA_CHIP_ID_BCM53572:
402 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
403 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
404 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
405 + break;
406 + case BCMA_CHIP_ID_BCM5357:
407 + case BCMA_CHIP_ID_BCM4749:
408 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
409 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
410 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
411 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
412 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
413 + break;
414 + case BCMA_CHIP_ID_BCM4706:
415 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
416 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
417 + 0);
418 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
419 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
420 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
421 + 0);
422 + break;
423 + default:
424 + list_for_each_entry(core, &bus->cores, list) {
425 + core->irq = bcma_core_irq(core);
426 }
427 + bcma_err(bus,
428 + "Unknown device (0x%x) found, can not configure IRQs\n",
429 + bus->chipinfo.id);
430 }
431 - bcma_info(bus, "IRQ reconfiguration done\n");
432 + bcma_debug(bus, "IRQ reconfiguration done\n");
433 bcma_core_mips_dump_irq(bus);
434
435 mcore->setup_done = true;
436 --- a/drivers/bcma/driver_pci_host.c
437 +++ b/drivers/bcma/driver_pci_host.c
438 @@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
439 if (dev == 0) {
440 /* we support only two functions on device 0 */
441 if (func > 1)
442 - return -EINVAL;
443 + goto out;
444
445 /* accesses to config registers with offsets >= 256
446 * requires indirect access.
447 */
448 if (off >= PCI_CONFIG_SPACE_SIZE) {
449 addr = (func << 12);
450 - addr |= (off & 0x0FFF);
451 + addr |= (off & 0x0FFC);
452 val = bcma_pcie_read_config(pc, addr);
453 } else {
454 addr = BCMA_CORE_PCI_PCICFG0;
455 addr |= (func << 8);
456 - addr |= (off & 0xfc);
457 + addr |= (off & 0xFC);
458 val = pcicore_read32(pc, addr);
459 }
460 } else {
461 @@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
462 goto out;
463
464 if (mips_busprobe32(val, mmio)) {
465 - val = 0xffffffff;
466 + val = 0xFFFFFFFF;
467 goto unmap;
468 }
469 -
470 - val = readl(mmio);
471 }
472 val >>= (8 * (off & 3));
473
474 @@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
475 const void *buf, int len)
476 {
477 int err = -EINVAL;
478 - u32 addr = 0, val = 0;
479 + u32 addr, val;
480 void __iomem *mmio = 0;
481 u16 chipid = pc->core->bus->chipinfo.id;
482
483 @@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
484 if (unlikely(len != 1 && len != 2 && len != 4))
485 goto out;
486 if (dev == 0) {
487 + /* we support only two functions on device 0 */
488 + if (func > 1)
489 + goto out;
490 +
491 /* accesses to config registers with offsets >= 256
492 * requires indirect access.
493 */
494 - if (off < PCI_CONFIG_SPACE_SIZE) {
495 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
496 + if (off >= PCI_CONFIG_SPACE_SIZE) {
497 + addr = (func << 12);
498 + addr |= (off & 0x0FFC);
499 + val = bcma_pcie_read_config(pc, addr);
500 + } else {
501 + addr = BCMA_CORE_PCI_PCICFG0;
502 addr |= (func << 8);
503 - addr |= (off & 0xfc);
504 - mmio = ioremap_nocache(addr, sizeof(val));
505 - if (!mmio)
506 - goto out;
507 + addr |= (off & 0xFC);
508 + val = pcicore_read32(pc, addr);
509 }
510 } else {
511 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
512 @@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
513 goto out;
514
515 if (mips_busprobe32(val, mmio)) {
516 - val = 0xffffffff;
517 + val = 0xFFFFFFFF;
518 goto unmap;
519 }
520 }
521
522 switch (len) {
523 case 1:
524 - val = readl(mmio);
525 val &= ~(0xFF << (8 * (off & 3)));
526 val |= *((const u8 *)buf) << (8 * (off & 3));
527 break;
528 case 2:
529 - val = readl(mmio);
530 val &= ~(0xFFFF << (8 * (off & 3)));
531 val |= *((const u16 *)buf) << (8 * (off & 3));
532 break;
533 @@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
534 val = *((const u32 *)buf);
535 break;
536 }
537 - if (dev == 0 && !addr) {
538 + if (dev == 0) {
539 /* accesses to config registers with offsets >= 256
540 * requires indirect access.
541 */
542 - addr = (func << 12);
543 - addr |= (off & 0x0FFF);
544 - bcma_pcie_write_config(pc, addr, val);
545 + if (off >= PCI_CONFIG_SPACE_SIZE)
546 + bcma_pcie_write_config(pc, addr, val);
547 + else
548 + pcicore_write32(pc, addr, val);
549 } else {
550 writel(val, mmio);
551
552 @@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
553 /* check for Header type 0 */
554 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
555 sizeof(u8));
556 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
557 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
558 return cap_ptr;
559
560 /* check if the capability pointer field exists */
561 @@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct
562 /* Reset RC */
563 usleep_range(3000, 5000);
564 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
565 - usleep_range(1000, 2000);
566 + msleep(50);
567 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
568 BCMA_CORE_PCI_CTL_RST_OE);
569
570 @@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct
571
572 bcma_core_pci_enable_crs(pc);
573
574 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
575 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
576 + u16 val16;
577 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
578 + &val16, sizeof(val16));
579 + val16 |= (2 << 5); /* Max payload size of 512 */
580 + val16 |= (2 << 12); /* MRRS 512 */
581 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
582 + &val16, sizeof(val16));
583 + }
584 +
585 /* Enable PCI bridge BAR0 memory & master access */
586 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
587 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
588 @@ -576,7 +590,7 @@ int bcma_core_pci_plat_dev_init(struct p
589 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
590
591 /* Fix up interrupt lines */
592 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
593 + dev->irq = bcma_core_irq(pc_host->pdev->core);
594 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
595
596 return 0;
597 @@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const
598
599 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
600 pci_ops);
601 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
602 + return bcma_core_irq(pc_host->pdev->core);
603 }
604 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
605 --- a/drivers/bcma/main.c
606 +++ b/drivers/bcma/main.c
607 @@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
608 }
609 EXPORT_SYMBOL_GPL(bcma_find_core);
610
611 -static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
612 - u8 unit)
613 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
614 + u8 unit)
615 {
616 struct bcma_device *core;
617
618 @@ -149,6 +149,14 @@ static int bcma_register_cores(struct bc
619 dev_id++;
620 }
621
622 +#ifdef CONFIG_BCMA_DRIVER_MIPS
623 + if (bus->drv_cc.pflash.present) {
624 + err = platform_device_register(&bcma_pflash_dev);
625 + if (err)
626 + bcma_err(bus, "Error registering parallel flash\n");
627 + }
628 +#endif
629 +
630 #ifdef CONFIG_BCMA_SFLASH
631 if (bus->drv_cc.sflash.present) {
632 err = platform_device_register(&bcma_sflash_dev);
633 --- a/include/linux/bcma/bcma_driver_chipcommon.h
634 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
635 @@ -27,7 +27,7 @@
636 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
637 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
638 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
639 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
640 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
641 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
642 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
643 #define BCMA_PLLTYPE_NONE 0x00000000
644 @@ -104,6 +104,7 @@
645 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
646 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
647 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
648 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
649 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
650 #define BCMA_CC_JCMD_START 0x80000000
651 #define BCMA_CC_JCMD_BUSY 0x80000000
652 @@ -606,6 +607,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
653
654 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
655
656 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
657 +
658 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
659
660 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
661 --- a/include/linux/bcma/bcma_driver_mips.h
662 +++ b/include/linux/bcma/bcma_driver_mips.h
663 @@ -28,6 +28,7 @@
664 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
665 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
666
667 +#define BCMA_MIPS_OOBSELINA74 0x004
668 #define BCMA_MIPS_OOBSELOUTA30 0x100
669
670 struct bcma_device;
671 @@ -36,19 +37,23 @@ struct bcma_drv_mips {
672 struct bcma_device *core;
673 u8 setup_done:1;
674 u8 early_setup_done:1;
675 - unsigned int assigned_irqs;
676 };
677
678 #ifdef CONFIG_BCMA_DRIVER_MIPS
679 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
680 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
681 +
682 +extern unsigned int bcma_core_irq(struct bcma_device *core);
683 #else
684 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
685 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
686 +
687 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
688 +{
689 + return 0;
690 +}
691 #endif
692
693 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
694
695 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
696 -
697 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
698 --- a/include/linux/bcma/bcma_driver_pci.h
699 +++ b/include/linux/bcma/bcma_driver_pci.h
700 @@ -179,6 +179,8 @@ struct pci_dev;
701 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
702 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
703
704 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
705 +
706 /* PCIE Root Capability Register bits (Host mode only) */
707 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
708
709 --- a/drivers/bcma/driver_chipcommon_pmu.c
710 +++ b/drivers/bcma/driver_chipcommon_pmu.c
711 @@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
712 struct bcma_bus *bus = cc->core->bus;
713
714 switch (bus->chipinfo.id) {
715 + case BCMA_CHIP_ID_BCM4313:
716 + case BCMA_CHIP_ID_BCM43224:
717 + case BCMA_CHIP_ID_BCM43225:
718 + case BCMA_CHIP_ID_BCM43227:
719 + case BCMA_CHIP_ID_BCM43228:
720 + case BCMA_CHIP_ID_BCM4331:
721 + case BCMA_CHIP_ID_BCM43421:
722 + case BCMA_CHIP_ID_BCM43428:
723 + case BCMA_CHIP_ID_BCM43431:
724 case BCMA_CHIP_ID_BCM4716:
725 - case BCMA_CHIP_ID_BCM4748:
726 case BCMA_CHIP_ID_BCM47162:
727 - case BCMA_CHIP_ID_BCM4313:
728 - case BCMA_CHIP_ID_BCM5357:
729 + case BCMA_CHIP_ID_BCM4748:
730 case BCMA_CHIP_ID_BCM4749:
731 + case BCMA_CHIP_ID_BCM5357:
732 case BCMA_CHIP_ID_BCM53572:
733 + case BCMA_CHIP_ID_BCM6362:
734 /* always 20Mhz */
735 return 20000 * 1000;
736 - case BCMA_CHIP_ID_BCM5356:
737 case BCMA_CHIP_ID_BCM4706:
738 + case BCMA_CHIP_ID_BCM5356:
739 /* always 25Mhz */
740 return 25000 * 1000;
741 + case BCMA_CHIP_ID_BCM43460:
742 + case BCMA_CHIP_ID_BCM4352:
743 + case BCMA_CHIP_ID_BCM4360:
744 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
745 + return 40000 * 1000;
746 + else
747 + return 20000 * 1000;
748 default:
749 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
750 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
751 @@ -372,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
752 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
753 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
754
755 - tmp = 1 << 10;
756 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
757 break;
758
759 case BCMA_CHIP_ID_BCM4331:
760 @@ -393,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
761 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
762 0x03000a08);
763 }
764 - tmp = 1 << 10;
765 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
766 break;
767
768 case BCMA_CHIP_ID_BCM43224:
769 @@ -426,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
770 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
771 0x88888815);
772 }
773 - tmp = 1 << 10;
774 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
775 break;
776
777 case BCMA_CHIP_ID_BCM4716:
778 @@ -460,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
779 0x88888815);
780 }
781
782 - tmp = 3 << 9;
783 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
784 break;
785
786 case BCMA_CHIP_ID_BCM43227:
787 @@ -496,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
788 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
789 0x88888815);
790 }
791 - tmp = 1 << 10;
792 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
793 break;
794 default:
795 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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