kernel: bcma: update to wireless-testing master-2013-10-01
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.8 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
15 config BCMA_HOST_PCI
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
18 + default y
19
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
23 PCI core hostmode operation (external PCI bus).
24
25 config BCMA_HOST_SOC
26 - bool
27 - depends on BCMA_DRIVER_MIPS
28 + bool "Support for BCMA in a SoC"
29 + depends on BCMA
30 + help
31 + Host interface for a Broadcom AIX bus directly mapped into
32 + the memory. This only works with the Broadcom SoCs from the
33 + BCM47XX line.
34 +
35 + If unsure, say N
36
37 config BCMA_DRIVER_MIPS
38 bool "BCMA Broadcom MIPS core driver"
39 --- a/drivers/bcma/bcma_private.h
40 +++ b/drivers/bcma/bcma_private.h
41 @@ -22,6 +22,8 @@
42 struct bcma_bus;
43
44 /* main.c */
45 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
46 + int timeout);
47 int bcma_bus_register(struct bcma_bus *bus);
48 void bcma_bus_unregister(struct bcma_bus *bus);
49 int __init bcma_bus_early_register(struct bcma_bus *bus,
50 @@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
51 int bcma_bus_suspend(struct bcma_bus *bus);
52 int bcma_bus_resume(struct bcma_bus *bus);
53 #endif
54 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
55 + u8 unit);
56
57 /* scan.c */
58 int bcma_bus_scan(struct bcma_bus *bus);
59 @@ -45,6 +49,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
60 /* driver_chipcommon.c */
61 #ifdef CONFIG_BCMA_DRIVER_MIPS
62 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
63 +extern struct platform_device bcma_pflash_dev;
64 #endif /* CONFIG_BCMA_DRIVER_MIPS */
65
66 /* driver_chipcommon_pmu.c */
67 --- a/drivers/bcma/core.c
68 +++ b/drivers/bcma/core.c
69 @@ -9,6 +9,25 @@
70 #include <linux/export.h>
71 #include <linux/bcma/bcma.h>
72
73 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
74 + u32 value, int timeout)
75 +{
76 + unsigned long deadline = jiffies + timeout;
77 + u32 val;
78 +
79 + do {
80 + val = bcma_aread32(core, reg);
81 + if ((val & mask) == value)
82 + return true;
83 + cpu_relax();
84 + udelay(10);
85 + } while (!time_after_eq(jiffies, deadline));
86 +
87 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
88 +
89 + return false;
90 +}
91 +
92 bool bcma_core_is_enabled(struct bcma_device *core)
93 {
94 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
95 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
96 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
97 return;
98
99 - bcma_awrite32(core, BCMA_IOCTL, flags);
100 - bcma_aread32(core, BCMA_IOCTL);
101 - udelay(10);
102 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
103
104 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
105 bcma_aread32(core, BCMA_RESET_CTL);
106 udelay(1);
107 +
108 + bcma_awrite32(core, BCMA_IOCTL, flags);
109 + bcma_aread32(core, BCMA_IOCTL);
110 + udelay(10);
111 }
112 EXPORT_SYMBOL_GPL(bcma_core_disable);
113
114 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
115 bcma_aread32(core, BCMA_IOCTL);
116
117 bcma_awrite32(core, BCMA_RESET_CTL, 0);
118 + bcma_aread32(core, BCMA_RESET_CTL);
119 udelay(1);
120
121 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
122 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
123 if (i)
124 bcma_err(core->bus, "PLL enable timeout\n");
125 } else {
126 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
127 + /*
128 + * Mask the PLL but don't wait for it to be disabled. PLL may be
129 + * shared between cores and will be still up if there is another
130 + * core using it.
131 + */
132 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
133 + bcma_read32(core, BCMA_CLKCTLST);
134 }
135 }
136 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
137 --- a/drivers/bcma/driver_chipcommon.c
138 +++ b/drivers/bcma/driver_chipcommon.c
139 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
140 return value;
141 }
142
143 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
144 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
145 {
146 if (cc->capabilities & BCMA_CC_CAP_PMU)
147 return bcma_pmu_get_alp_clock(cc);
148
149 return 20000000;
150 }
151 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
152
153 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
154 {
155 @@ -139,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
156 bcma_core_chipcommon_early_init(cc);
157
158 if (cc->core->id.rev >= 20) {
159 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
160 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
161 + u32 pullup = 0, pulldown = 0;
162 +
163 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
164 + pullup = 0x402e0;
165 + pulldown = 0x20500;
166 + }
167 +
168 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
169 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
170 }
171
172 if (cc->capabilities & BCMA_CC_CAP_PMU)
173 @@ -213,6 +221,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
174
175 return res;
176 }
177 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
178
179 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
180 {
181 @@ -225,6 +234,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
182
183 return res;
184 }
185 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
186
187 /*
188 * If the bit is set to 0, chipcommon controlls this GPIO,
189 @@ -329,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
190 return;
191 }
192
193 - irq = bcma_core_mips_irq(cc->core);
194 + irq = bcma_core_irq(cc->core);
195
196 /* Determine the registers of the UARTs */
197 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
198 --- a/drivers/bcma/driver_chipcommon_nflash.c
199 +++ b/drivers/bcma/driver_chipcommon_nflash.c
200 @@ -5,11 +5,11 @@
201 * Licensed under the GNU/GPL. See COPYING for details.
202 */
203
204 +#include "bcma_private.h"
205 +
206 #include <linux/platform_device.h>
207 #include <linux/bcma/bcma.h>
208
209 -#include "bcma_private.h"
210 -
211 struct platform_device bcma_nflash_dev = {
212 .name = "bcma_nflash",
213 .num_resources = 0,
214 --- a/drivers/bcma/driver_chipcommon_pmu.c
215 +++ b/drivers/bcma/driver_chipcommon_pmu.c
216 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
217 }
218 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
219
220 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
221 +{
222 + u32 ilp_ctl, alp_hz;
223 +
224 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
225 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
226 + return 0;
227 +
228 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
229 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
230 + usleep_range(1000, 2000);
231 +
232 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
233 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
234 +
235 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
236 +
237 + alp_hz = ilp_ctl * 32768 / 4;
238 + return (alp_hz + 50000) / 100000 * 100;
239 +}
240 +
241 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
242 +{
243 + struct bcma_bus *bus = cc->core->bus;
244 + u32 freq_tgt_target = 0, freq_tgt_current;
245 + u32 pll0, mask;
246 +
247 + switch (bus->chipinfo.id) {
248 + case BCMA_CHIP_ID_BCM43142:
249 + /* pmu2_xtaltab0_adfll_485 */
250 + switch (xtalfreq) {
251 + case 12000:
252 + freq_tgt_target = 0x50D52;
253 + break;
254 + case 20000:
255 + freq_tgt_target = 0x307FE;
256 + break;
257 + case 26000:
258 + freq_tgt_target = 0x254EA;
259 + break;
260 + case 37400:
261 + freq_tgt_target = 0x19EF8;
262 + break;
263 + case 52000:
264 + freq_tgt_target = 0x12A75;
265 + break;
266 + }
267 + break;
268 + }
269 +
270 + if (!freq_tgt_target) {
271 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
272 + xtalfreq);
273 + return;
274 + }
275 +
276 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
277 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
278 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
279 +
280 + if (freq_tgt_current == freq_tgt_target) {
281 + bcma_debug(bus, "Target TGT frequency already set\n");
282 + return;
283 + }
284 +
285 + /* Turn off PLL */
286 + switch (bus->chipinfo.id) {
287 + case BCMA_CHIP_ID_BCM43142:
288 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
289 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
290 +
291 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
292 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
293 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
294 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
295 + break;
296 + }
297 +
298 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
299 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
300 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
301 +
302 + /* Flush */
303 + if (cc->pmu.rev >= 2)
304 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
305 +
306 + /* TODO: Do we need to update OTP? */
307 +}
308 +
309 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
310 +{
311 + struct bcma_bus *bus = cc->core->bus;
312 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
313 +
314 + switch (bus->chipinfo.id) {
315 + case BCMA_CHIP_ID_BCM43142:
316 + if (xtalfreq == 0)
317 + xtalfreq = 20000;
318 + bcma_pmu2_pll_init0(cc, xtalfreq);
319 + break;
320 + }
321 +}
322 +
323 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
324 {
325 struct bcma_bus *bus = cc->core->bus;
326 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
327 min_msk = 0x200D;
328 max_msk = 0xFFFF;
329 break;
330 + case BCMA_CHIP_ID_BCM43142:
331 + min_msk = BCMA_RES_4314_LPLDO_PU |
332 + BCMA_RES_4314_PMU_SLEEP_DIS |
333 + BCMA_RES_4314_PMU_BG_PU |
334 + BCMA_RES_4314_CBUCK_LPOM_PU |
335 + BCMA_RES_4314_CBUCK_PFM_PU |
336 + BCMA_RES_4314_CLDO_PU |
337 + BCMA_RES_4314_LPLDO2_LVM |
338 + BCMA_RES_4314_WL_PMU_PU |
339 + BCMA_RES_4314_LDO3P3_PU |
340 + BCMA_RES_4314_OTP_PU |
341 + BCMA_RES_4314_WL_PWRSW_PU |
342 + BCMA_RES_4314_LQ_AVAIL |
343 + BCMA_RES_4314_LOGIC_RET |
344 + BCMA_RES_4314_MEM_SLEEP |
345 + BCMA_RES_4314_MACPHY_RET |
346 + BCMA_RES_4314_WL_CORE_READY;
347 + max_msk = 0x3FFFFFFF;
348 + break;
349 default:
350 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
351 bus->chipinfo.id);
352 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
353 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
354 BCMA_CC_PMU_CTL_NOILPONW);
355
356 + bcma_pmu_pll_init(cc);
357 bcma_pmu_resources_init(cc);
358 bcma_pmu_workarounds(cc);
359 }
360 @@ -174,19 +297,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
361 struct bcma_bus *bus = cc->core->bus;
362
363 switch (bus->chipinfo.id) {
364 + case BCMA_CHIP_ID_BCM4313:
365 + case BCMA_CHIP_ID_BCM43224:
366 + case BCMA_CHIP_ID_BCM43225:
367 + case BCMA_CHIP_ID_BCM43227:
368 + case BCMA_CHIP_ID_BCM43228:
369 + case BCMA_CHIP_ID_BCM4331:
370 + case BCMA_CHIP_ID_BCM43421:
371 + case BCMA_CHIP_ID_BCM43428:
372 + case BCMA_CHIP_ID_BCM43431:
373 case BCMA_CHIP_ID_BCM4716:
374 - case BCMA_CHIP_ID_BCM4748:
375 case BCMA_CHIP_ID_BCM47162:
376 - case BCMA_CHIP_ID_BCM4313:
377 - case BCMA_CHIP_ID_BCM5357:
378 + case BCMA_CHIP_ID_BCM4748:
379 case BCMA_CHIP_ID_BCM4749:
380 + case BCMA_CHIP_ID_BCM5357:
381 case BCMA_CHIP_ID_BCM53572:
382 + case BCMA_CHIP_ID_BCM6362:
383 /* always 20Mhz */
384 return 20000 * 1000;
385 - case BCMA_CHIP_ID_BCM5356:
386 case BCMA_CHIP_ID_BCM4706:
387 + case BCMA_CHIP_ID_BCM5356:
388 /* always 25Mhz */
389 return 25000 * 1000;
390 + case BCMA_CHIP_ID_BCM43460:
391 + case BCMA_CHIP_ID_BCM4352:
392 + case BCMA_CHIP_ID_BCM4360:
393 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
394 + return 40000 * 1000;
395 + else
396 + return 20000 * 1000;
397 default:
398 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
399 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
400 @@ -264,7 +403,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st
401 }
402
403 /* query bus clock frequency for PMU-enabled chipcommon */
404 -static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
405 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
406 {
407 struct bcma_bus *bus = cc->core->bus;
408
409 @@ -293,6 +432,7 @@ static u32 bcma_pmu_get_bus_clock(struct
410 }
411 return BCMA_CC_PMU_HT_CLOCK;
412 }
413 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
414
415 /* query cpu clock frequency for PMU-enabled chipcommon */
416 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
417 @@ -372,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
418 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
419 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
420
421 - tmp = 1 << 10;
422 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
423 break;
424
425 case BCMA_CHIP_ID_BCM4331:
426 @@ -393,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
427 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
428 0x03000a08);
429 }
430 - tmp = 1 << 10;
431 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
432 break;
433
434 case BCMA_CHIP_ID_BCM43224:
435 @@ -426,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
436 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
437 0x88888815);
438 }
439 - tmp = 1 << 10;
440 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
441 break;
442
443 case BCMA_CHIP_ID_BCM4716:
444 @@ -460,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
445 0x88888815);
446 }
447
448 - tmp = 3 << 9;
449 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
450 break;
451
452 case BCMA_CHIP_ID_BCM43227:
453 @@ -496,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
454 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
455 0x88888815);
456 }
457 - tmp = 1 << 10;
458 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
459 break;
460 default:
461 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
462 --- a/drivers/bcma/driver_chipcommon_sflash.c
463 +++ b/drivers/bcma/driver_chipcommon_sflash.c
464 @@ -5,11 +5,11 @@
465 * Licensed under the GNU/GPL. See COPYING for details.
466 */
467
468 +#include "bcma_private.h"
469 +
470 #include <linux/platform_device.h>
471 #include <linux/bcma/bcma.h>
472
473 -#include "bcma_private.h"
474 -
475 static struct resource bcma_sflash_resource = {
476 .name = "bcma_sflash",
477 .start = BCMA_SOC_FLASH2,
478 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
479 u16 numblocks;
480 };
481
482 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
483 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
484 { "M25P20", 0x11, 0x10000, 4, },
485 { "M25P40", 0x12, 0x10000, 8, },
486
487 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
488 { 0 },
489 };
490
491 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
492 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
493 { "SST25WF512", 1, 0x1000, 16, },
494 { "SST25VF512", 0x48, 0x1000, 16, },
495 { "SST25WF010", 2, 0x1000, 32, },
496 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
497 { 0 },
498 };
499
500 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
501 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
502 { "AT45DB011", 0xc, 256, 512, },
503 { "AT45DB021", 0x14, 256, 1024, },
504 { "AT45DB041", 0x1c, 256, 2048, },
505 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
506 {
507 struct bcma_bus *bus = cc->core->bus;
508 struct bcma_sflash *sflash = &cc->sflash;
509 - struct bcma_sflash_tbl_e *e;
510 + const struct bcma_sflash_tbl_e *e;
511 u32 id, id2;
512
513 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
514 --- a/drivers/bcma/driver_gpio.c
515 +++ b/drivers/bcma/driver_gpio.c
516 @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
517 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
518 }
519
520 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
521 +{
522 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
523 +
524 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
525 + return bcma_core_irq(cc->core);
526 + else
527 + return -EINVAL;
528 +}
529 +
530 int bcma_gpio_init(struct bcma_drv_cc *cc)
531 {
532 struct gpio_chip *chip = &cc->gpio;
533 @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
534 chip->set = bcma_gpio_set_value;
535 chip->direction_input = bcma_gpio_direction_input;
536 chip->direction_output = bcma_gpio_direction_output;
537 + chip->to_irq = bcma_gpio_to_irq;
538 chip->ngpio = 16;
539 /* There is just one SoC in one device and its GPIO addresses should be
540 * deterministic to address them more easily. The other buses could get
541 --- a/drivers/bcma/driver_mips.c
542 +++ b/drivers/bcma/driver_mips.c
543 @@ -14,11 +14,33 @@
544
545 #include <linux/bcma/bcma.h>
546
547 +#include <linux/mtd/physmap.h>
548 +#include <linux/platform_device.h>
549 #include <linux/serial.h>
550 #include <linux/serial_core.h>
551 #include <linux/serial_reg.h>
552 #include <linux/time.h>
553
554 +static const char *part_probes[] = { "bcm47xxpart", NULL };
555 +
556 +static struct physmap_flash_data bcma_pflash_data = {
557 + .part_probe_types = part_probes,
558 +};
559 +
560 +static struct resource bcma_pflash_resource = {
561 + .name = "bcma_pflash",
562 + .flags = IORESOURCE_MEM,
563 +};
564 +
565 +struct platform_device bcma_pflash_dev = {
566 + .name = "physmap-flash",
567 + .dev = {
568 + .platform_data = &bcma_pflash_data,
569 + },
570 + .resource = &bcma_pflash_resource,
571 + .num_resources = 1,
572 +};
573 +
574 /* The 47162a0 hangs when reading MIPS DMP registers registers */
575 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
576 {
577 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
578 return dev->core_index;
579 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
580
581 - return flag & 0x1F;
582 + if (flag)
583 + return flag & 0x1F;
584 + else
585 + return 0x3f;
586 }
587
588 /* Get the MIPS IRQ assignment for a specified device.
589 * If unassigned, 0 is returned.
590 + * If disabled, 5 is returned.
591 + * If not supported, 6 is returned.
592 */
593 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
594 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
595 {
596 struct bcma_device *mdev = dev->bus->drv_mips.core;
597 u32 irqflag;
598 unsigned int irq;
599
600 irqflag = bcma_core_mips_irqflag(dev);
601 + if (irqflag == 0x3f)
602 + return 6;
603
604 - for (irq = 1; irq <= 4; irq++)
605 + for (irq = 0; irq <= 4; irq++)
606 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
607 (1 << irqflag))
608 return irq;
609
610 - return 0;
611 + return 5;
612 }
613 -EXPORT_SYMBOL(bcma_core_mips_irq);
614 +
615 +unsigned int bcma_core_irq(struct bcma_device *dev)
616 +{
617 + unsigned int mips_irq = bcma_core_mips_irq(dev);
618 + return mips_irq <= 4 ? mips_irq + 2 : 0;
619 +}
620 +EXPORT_SYMBOL(bcma_core_irq);
621
622 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
623 {
624 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
625 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
626 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
627 ~(1 << irqflag));
628 - else
629 + else if (oldirq != 5)
630 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
631
632 /* assign the new one */
633 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
634 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
635 (1 << irqflag));
636 } else {
637 - u32 oldirqflag = bcma_read32(mdev,
638 - BCMA_MIPS_MIPS74K_INTMASK(irq));
639 - if (oldirqflag) {
640 + u32 irqinitmask = bcma_read32(mdev,
641 + BCMA_MIPS_MIPS74K_INTMASK(irq));
642 + if (irqinitmask) {
643 struct bcma_device *core;
644
645 /* backplane irq line is in use, find out who uses
646 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
647 */
648 list_for_each_entry(core, &bus->cores, list) {
649 if ((1 << bcma_core_mips_irqflag(core)) ==
650 - oldirqflag) {
651 + irqinitmask) {
652 bcma_core_mips_set_irq(core, 0);
653 break;
654 }
655 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
656 1 << irqflag);
657 }
658
659 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
660 - dev->id.id, oldirq + 2, irq + 2);
661 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
662 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
663 +}
664 +
665 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
666 + u16 coreid, u8 unit)
667 +{
668 + struct bcma_device *core;
669 +
670 + core = bcma_find_core_unit(bus, coreid, unit);
671 + if (!core) {
672 + bcma_warn(bus,
673 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
674 + coreid, unit);
675 + return;
676 + }
677 +
678 + bcma_core_mips_set_irq(core, irq);
679 }
680
681 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
682 {
683 int i;
684 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
685 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
686 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
687 for (i = 0; i <= 6; i++)
688 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
689 printk("\n");
690 @@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
691 {
692 struct bcma_bus *bus = mcore->core->bus;
693 struct bcma_drv_cc *cc = &bus->drv_cc;
694 + struct bcma_pflash *pflash = &cc->pflash;
695
696 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
697 case BCMA_CC_FLASHT_STSER:
698 @@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
699 break;
700 case BCMA_CC_FLASHT_PARA:
701 bcma_debug(bus, "Found parallel flash\n");
702 - cc->pflash.present = true;
703 - cc->pflash.window = BCMA_SOC_FLASH2;
704 - cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
705 + pflash->present = true;
706 + pflash->window = BCMA_SOC_FLASH2;
707 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
708
709 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
710 BCMA_CC_FLASH_CFG_DS) == 0)
711 - cc->pflash.buswidth = 1;
712 + pflash->buswidth = 1;
713 else
714 - cc->pflash.buswidth = 2;
715 + pflash->buswidth = 2;
716 +
717 + bcma_pflash_data.width = pflash->buswidth;
718 + bcma_pflash_resource.start = pflash->window;
719 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
720 +
721 break;
722 default:
723 bcma_err(bus, "Flash type not supported\n");
724 @@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
725 mcore->early_setup_done = true;
726 }
727
728 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
729 +{
730 + struct bcma_device *cpu, *pcie, *i2s;
731 +
732 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
733 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
734 + */
735 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
736 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
737 + return;
738 +
739 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
740 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
741 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
742 + if (cpu && pcie && i2s &&
743 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
744 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
745 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
746 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
747 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
748 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
749 + bcma_debug(bus,
750 + "Moved i2s interrupt to oob line 7 instead of 8\n");
751 + }
752 +}
753 +
754 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
755 {
756 struct bcma_bus *bus;
757 @@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
758 if (mcore->setup_done)
759 return;
760
761 - bcma_info(bus, "Initializing MIPS core...\n");
762 + bcma_debug(bus, "Initializing MIPS core...\n");
763
764 bcma_core_mips_early_init(mcore);
765
766 - mcore->assigned_irqs = 1;
767 + bcma_fix_i2s_irqflag(bus);
768
769 - /* Assign IRQs to all cores on the bus */
770 - list_for_each_entry(core, &bus->cores, list) {
771 - int mips_irq;
772 - if (core->irq)
773 - continue;
774 -
775 - mips_irq = bcma_core_mips_irq(core);
776 - if (mips_irq > 4)
777 - core->irq = 0;
778 - else
779 - core->irq = mips_irq + 2;
780 - if (core->irq > 5)
781 - continue;
782 - switch (core->id.id) {
783 - case BCMA_CORE_PCI:
784 - case BCMA_CORE_PCIE:
785 - case BCMA_CORE_ETHERNET:
786 - case BCMA_CORE_ETHERNET_GBIT:
787 - case BCMA_CORE_MAC_GBIT:
788 - case BCMA_CORE_80211:
789 - case BCMA_CORE_USB20_HOST:
790 - /* These devices get their own IRQ line if available,
791 - * the rest goes on IRQ0
792 - */
793 - if (mcore->assigned_irqs <= 4)
794 - bcma_core_mips_set_irq(core,
795 - mcore->assigned_irqs++);
796 - break;
797 + switch (bus->chipinfo.id) {
798 + case BCMA_CHIP_ID_BCM4716:
799 + case BCMA_CHIP_ID_BCM4748:
800 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
801 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
802 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
803 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
804 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
805 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
806 + break;
807 + case BCMA_CHIP_ID_BCM5356:
808 + case BCMA_CHIP_ID_BCM47162:
809 + case BCMA_CHIP_ID_BCM53572:
810 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
811 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
812 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
813 + break;
814 + case BCMA_CHIP_ID_BCM5357:
815 + case BCMA_CHIP_ID_BCM4749:
816 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
817 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
818 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
819 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
820 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
821 + break;
822 + case BCMA_CHIP_ID_BCM4706:
823 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
824 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
825 + 0);
826 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
827 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
828 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
829 + 0);
830 + break;
831 + default:
832 + list_for_each_entry(core, &bus->cores, list) {
833 + core->irq = bcma_core_irq(core);
834 }
835 + bcma_err(bus,
836 + "Unknown device (0x%x) found, can not configure IRQs\n",
837 + bus->chipinfo.id);
838 }
839 - bcma_info(bus, "IRQ reconfiguration done\n");
840 + bcma_debug(bus, "IRQ reconfiguration done\n");
841 bcma_core_mips_dump_irq(bus);
842
843 mcore->setup_done = true;
844 --- a/drivers/bcma/driver_pci_host.c
845 +++ b/drivers/bcma/driver_pci_host.c
846 @@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
847 if (dev == 0) {
848 /* we support only two functions on device 0 */
849 if (func > 1)
850 - return -EINVAL;
851 + goto out;
852
853 /* accesses to config registers with offsets >= 256
854 * requires indirect access.
855 */
856 if (off >= PCI_CONFIG_SPACE_SIZE) {
857 addr = (func << 12);
858 - addr |= (off & 0x0FFF);
859 + addr |= (off & 0x0FFC);
860 val = bcma_pcie_read_config(pc, addr);
861 } else {
862 addr = BCMA_CORE_PCI_PCICFG0;
863 addr |= (func << 8);
864 - addr |= (off & 0xfc);
865 + addr |= (off & 0xFC);
866 val = pcicore_read32(pc, addr);
867 }
868 } else {
869 @@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
870 goto out;
871
872 if (mips_busprobe32(val, mmio)) {
873 - val = 0xffffffff;
874 + val = 0xFFFFFFFF;
875 goto unmap;
876 }
877 -
878 - val = readl(mmio);
879 }
880 val >>= (8 * (off & 3));
881
882 @@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
883 const void *buf, int len)
884 {
885 int err = -EINVAL;
886 - u32 addr = 0, val = 0;
887 + u32 addr, val;
888 void __iomem *mmio = 0;
889 u16 chipid = pc->core->bus->chipinfo.id;
890
891 @@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
892 if (unlikely(len != 1 && len != 2 && len != 4))
893 goto out;
894 if (dev == 0) {
895 + /* we support only two functions on device 0 */
896 + if (func > 1)
897 + goto out;
898 +
899 /* accesses to config registers with offsets >= 256
900 * requires indirect access.
901 */
902 - if (off < PCI_CONFIG_SPACE_SIZE) {
903 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
904 + if (off >= PCI_CONFIG_SPACE_SIZE) {
905 + addr = (func << 12);
906 + addr |= (off & 0x0FFC);
907 + val = bcma_pcie_read_config(pc, addr);
908 + } else {
909 + addr = BCMA_CORE_PCI_PCICFG0;
910 addr |= (func << 8);
911 - addr |= (off & 0xfc);
912 - mmio = ioremap_nocache(addr, sizeof(val));
913 - if (!mmio)
914 - goto out;
915 + addr |= (off & 0xFC);
916 + val = pcicore_read32(pc, addr);
917 }
918 } else {
919 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
920 @@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
921 goto out;
922
923 if (mips_busprobe32(val, mmio)) {
924 - val = 0xffffffff;
925 + val = 0xFFFFFFFF;
926 goto unmap;
927 }
928 }
929
930 switch (len) {
931 case 1:
932 - val = readl(mmio);
933 val &= ~(0xFF << (8 * (off & 3)));
934 val |= *((const u8 *)buf) << (8 * (off & 3));
935 break;
936 case 2:
937 - val = readl(mmio);
938 val &= ~(0xFFFF << (8 * (off & 3)));
939 val |= *((const u16 *)buf) << (8 * (off & 3));
940 break;
941 @@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
942 val = *((const u32 *)buf);
943 break;
944 }
945 - if (dev == 0 && !addr) {
946 + if (dev == 0) {
947 /* accesses to config registers with offsets >= 256
948 * requires indirect access.
949 */
950 - addr = (func << 12);
951 - addr |= (off & 0x0FFF);
952 - bcma_pcie_write_config(pc, addr, val);
953 + if (off >= PCI_CONFIG_SPACE_SIZE)
954 + bcma_pcie_write_config(pc, addr, val);
955 + else
956 + pcicore_write32(pc, addr, val);
957 } else {
958 writel(val, mmio);
959
960 @@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
961 /* check for Header type 0 */
962 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
963 sizeof(u8));
964 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
965 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
966 return cap_ptr;
967
968 /* check if the capability pointer field exists */
969 @@ -401,6 +404,8 @@ void bcma_core_pci_hostmode_init(struct
970 return;
971 }
972
973 + spin_lock_init(&pc_host->cfgspace_lock);
974 +
975 pc->host_controller = pc_host;
976 pc_host->pci_controller.io_resource = &pc_host->io_resource;
977 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
978 @@ -426,7 +431,7 @@ void bcma_core_pci_hostmode_init(struct
979 /* Reset RC */
980 usleep_range(3000, 5000);
981 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
982 - usleep_range(1000, 2000);
983 + msleep(50);
984 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
985 BCMA_CORE_PCI_CTL_RST_OE);
986
987 @@ -488,6 +493,17 @@ void bcma_core_pci_hostmode_init(struct
988
989 bcma_core_pci_enable_crs(pc);
990
991 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
992 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
993 + u16 val16;
994 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
995 + &val16, sizeof(val16));
996 + val16 |= (2 << 5); /* Max payload size of 512 */
997 + val16 |= (2 << 12); /* MRRS 512 */
998 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
999 + &val16, sizeof(val16));
1000 + }
1001 +
1002 /* Enable PCI bridge BAR0 memory & master access */
1003 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1004 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1005 @@ -565,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
1006 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1007 {
1008 struct bcma_drv_pci_host *pc_host;
1009 + int readrq;
1010
1011 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1012 /* This is not a device on the PCI-core bridge. */
1013 @@ -576,9 +593,14 @@ int bcma_core_pci_plat_dev_init(struct p
1014 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1015
1016 /* Fix up interrupt lines */
1017 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1018 + dev->irq = bcma_core_irq(pc_host->pdev->core);
1019 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1020
1021 + readrq = pcie_get_readrq(dev);
1022 + if (readrq > 128) {
1023 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
1024 + pcie_set_readrq(dev, 128);
1025 + }
1026 return 0;
1027 }
1028 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1029 @@ -595,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const
1030
1031 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1032 pci_ops);
1033 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1034 + return bcma_core_irq(pc_host->pdev->core);
1035 }
1036 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1037 --- a/drivers/bcma/host_pci.c
1038 +++ b/drivers/bcma/host_pci.c
1039 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1040 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1043 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1045 { 0, },
1046 };
1047 --- a/drivers/bcma/main.c
1048 +++ b/drivers/bcma/main.c
1049 @@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
1050 }
1051 EXPORT_SYMBOL_GPL(bcma_find_core);
1052
1053 -static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1054 - u8 unit)
1055 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1056 + u8 unit)
1057 {
1058 struct bcma_device *core;
1059
1060 @@ -93,6 +93,25 @@ static struct bcma_device *bcma_find_cor
1061 return NULL;
1062 }
1063
1064 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1065 + int timeout)
1066 +{
1067 + unsigned long deadline = jiffies + timeout;
1068 + u32 val;
1069 +
1070 + do {
1071 + val = bcma_read32(core, reg);
1072 + if ((val & mask) == value)
1073 + return true;
1074 + cpu_relax();
1075 + udelay(10);
1076 + } while (!time_after_eq(jiffies, deadline));
1077 +
1078 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
1079 +
1080 + return false;
1081 +}
1082 +
1083 static void bcma_release_core_dev(struct device *dev)
1084 {
1085 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1086 @@ -120,6 +139,11 @@ static int bcma_register_cores(struct bc
1087 continue;
1088 }
1089
1090 + /* Only first GMAC core on BCM4706 is connected and working */
1091 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1092 + core->core_unit > 0)
1093 + continue;
1094 +
1095 core->dev.release = bcma_release_core_dev;
1096 core->dev.bus = &bcma_bus_type;
1097 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1098 @@ -149,6 +173,14 @@ static int bcma_register_cores(struct bc
1099 dev_id++;
1100 }
1101
1102 +#ifdef CONFIG_BCMA_DRIVER_MIPS
1103 + if (bus->drv_cc.pflash.present) {
1104 + err = platform_device_register(&bcma_pflash_dev);
1105 + if (err)
1106 + bcma_err(bus, "Error registering parallel flash\n");
1107 + }
1108 +#endif
1109 +
1110 #ifdef CONFIG_BCMA_SFLASH
1111 if (bus->drv_cc.sflash.present) {
1112 err = platform_device_register(&bcma_sflash_dev);
1113 @@ -205,7 +237,7 @@ int bcma_bus_register(struct bcma_bus *b
1114 err = bcma_bus_scan(bus);
1115 if (err) {
1116 bcma_err(bus, "Failed to scan: %d\n", err);
1117 - return -1;
1118 + return err;
1119 }
1120
1121 /* Early init CC core */
1122 --- a/drivers/bcma/scan.c
1123 +++ b/drivers/bcma/scan.c
1124 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
1125 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1126 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1127 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1128 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
1129 + { BCMA_CORE_DMA, "DMA" },
1130 + { BCMA_CORE_SDIO3, "SDIO3" },
1131 + { BCMA_CORE_USB20, "USB 2.0" },
1132 + { BCMA_CORE_USB30, "USB 3.0" },
1133 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
1134 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
1135 + { BCMA_CORE_ROM, "ROM" },
1136 + { BCMA_CORE_NAND, "NAND flash controller" },
1137 + { BCMA_CORE_QSPI, "SPI flash controller" },
1138 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
1139 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1140 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1141 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1142 { BCMA_CORE_INVALID, "Invalid" },
1143 @@ -84,6 +96,8 @@ static const struct bcma_device_id_name
1144 { BCMA_CORE_I2S, "I2S" },
1145 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
1146 { BCMA_CORE_SHIM, "SHIM" },
1147 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
1148 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
1149 { BCMA_CORE_DEFAULT, "Default" },
1150 };
1151
1152 @@ -137,19 +151,19 @@ static void bcma_scan_switch_core(struct
1153 addr);
1154 }
1155
1156 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
1157 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
1158 {
1159 u32 ent = readl(*eromptr);
1160 (*eromptr)++;
1161 return ent;
1162 }
1163
1164 -static void bcma_erom_push_ent(u32 **eromptr)
1165 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
1166 {
1167 (*eromptr)--;
1168 }
1169
1170 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
1171 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
1172 {
1173 u32 ent = bcma_erom_get_ent(bus, eromptr);
1174 if (!(ent & SCAN_ER_VALID))
1175 @@ -159,14 +173,14 @@ static s32 bcma_erom_get_ci(struct bcma_
1176 return ent;
1177 }
1178
1179 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
1180 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
1181 {
1182 u32 ent = bcma_erom_get_ent(bus, eromptr);
1183 bcma_erom_push_ent(eromptr);
1184 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
1185 }
1186
1187 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
1188 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
1189 {
1190 u32 ent = bcma_erom_get_ent(bus, eromptr);
1191 bcma_erom_push_ent(eromptr);
1192 @@ -175,7 +189,7 @@ static bool bcma_erom_is_bridge(struct b
1193 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
1194 }
1195
1196 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
1197 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
1198 {
1199 u32 ent;
1200 while (1) {
1201 @@ -189,7 +203,7 @@ static void bcma_erom_skip_component(str
1202 bcma_erom_push_ent(eromptr);
1203 }
1204
1205 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
1206 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
1207 {
1208 u32 ent = bcma_erom_get_ent(bus, eromptr);
1209 if (!(ent & SCAN_ER_VALID))
1210 @@ -199,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1211 return ent;
1212 }
1213
1214 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
1215 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1216 u32 type, u8 port)
1217 {
1218 u32 addrl, addrh, sizel, sizeh = 0;
1219 @@ -211,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1220 ((ent & SCAN_ADDR_TYPE) != type) ||
1221 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1222 bcma_erom_push_ent(eromptr);
1223 - return -EINVAL;
1224 + return (u32)-EINVAL;
1225 }
1226
1227 addrl = ent & SCAN_ADDR_ADDR;
1228 @@ -255,11 +269,13 @@ static struct bcma_device *bcma_find_cor
1229 return NULL;
1230 }
1231
1232 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1233 +
1234 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1235 struct bcma_device_id *match, int core_num,
1236 struct bcma_device *core)
1237 {
1238 - s32 tmp;
1239 + u32 tmp;
1240 u8 i, j;
1241 s32 cia, cib;
1242 u8 ports[2], wrappers[2];
1243 @@ -337,11 +353,11 @@ static int bcma_get_next_core(struct bcm
1244 * the main register space for the core
1245 */
1246 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1247 - if (tmp <= 0) {
1248 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1249 /* Try again to see if it is a bridge */
1250 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1251 SCAN_ADDR_TYPE_BRIDGE, 0);
1252 - if (tmp <= 0) {
1253 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1254 return -EILSEQ;
1255 } else {
1256 bcma_info(bus, "Bridge found\n");
1257 @@ -355,7 +371,7 @@ static int bcma_get_next_core(struct bcm
1258 for (j = 0; ; j++) {
1259 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1260 SCAN_ADDR_TYPE_SLAVE, i);
1261 - if (tmp < 0) {
1262 + if (IS_ERR_VALUE_U32(tmp)) {
1263 /* no more entries for port _i_ */
1264 /* pr_debug("erom: slave port %d "
1265 * "has %d descriptors\n", i, j); */
1266 @@ -372,7 +388,7 @@ static int bcma_get_next_core(struct bcm
1267 for (j = 0; ; j++) {
1268 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1269 SCAN_ADDR_TYPE_MWRAP, i);
1270 - if (tmp < 0) {
1271 + if (IS_ERR_VALUE_U32(tmp)) {
1272 /* no more entries for port _i_ */
1273 /* pr_debug("erom: master wrapper %d "
1274 * "has %d descriptors\n", i, j); */
1275 @@ -390,7 +406,7 @@ static int bcma_get_next_core(struct bcm
1276 for (j = 0; ; j++) {
1277 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1278 SCAN_ADDR_TYPE_SWRAP, i + hack);
1279 - if (tmp < 0) {
1280 + if (IS_ERR_VALUE_U32(tmp)) {
1281 /* no more entries for port _i_ */
1282 /* pr_debug("erom: master wrapper %d "
1283 * has %d descriptors\n", i, j); */
1284 --- a/drivers/bcma/sprom.c
1285 +++ b/drivers/bcma/sprom.c
1286 @@ -72,12 +72,12 @@ fail:
1287 * R/W ops.
1288 **************************************************/
1289
1290 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1291 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1292 + size_t words)
1293 {
1294 int i;
1295 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1296 - sprom[i] = bcma_read16(bus->drv_cc.core,
1297 - offset + (i * 2));
1298 + for (i = 0; i < words; i++)
1299 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1300 }
1301
1302 /**************************************************
1303 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1304 return t[crc ^ data];
1305 }
1306
1307 -static u8 bcma_sprom_crc(const u16 *sprom)
1308 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1309 {
1310 int word;
1311 u8 crc = 0xFF;
1312
1313 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1314 + for (word = 0; word < words - 1; word++) {
1315 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1316 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1317 }
1318 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1319 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1320 crc ^= 0xFF;
1321
1322 return crc;
1323 }
1324
1325 -static int bcma_sprom_check_crc(const u16 *sprom)
1326 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1327 {
1328 u8 crc;
1329 u8 expected_crc;
1330 u16 tmp;
1331
1332 - crc = bcma_sprom_crc(sprom);
1333 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1334 + crc = bcma_sprom_crc(sprom, words);
1335 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1336 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1337 if (crc != expected_crc)
1338 return -EPROTO;
1339 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1340 return 0;
1341 }
1342
1343 -static int bcma_sprom_valid(const u16 *sprom)
1344 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1345 + size_t words)
1346 {
1347 u16 revision;
1348 int err;
1349
1350 - err = bcma_sprom_check_crc(sprom);
1351 + err = bcma_sprom_check_crc(sprom, words);
1352 if (err)
1353 return err;
1354
1355 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1356 - if (revision != 8 && revision != 9) {
1357 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1358 + if (revision != 8 && revision != 9 && revision != 10) {
1359 pr_err("Unsupported SPROM revision: %d\n", revision);
1360 return -ENOENT;
1361 }
1362
1363 + bus->sprom.revision = revision;
1364 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1365 +
1366 return 0;
1367 }
1368
1369 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
1370 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1371 ARRAY_SIZE(bus->sprom.core_pwr_info));
1372
1373 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1374 - SSB_SPROM_REVISION_REV;
1375 -
1376 for (i = 0; i < 3; i++) {
1377 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1378 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1379 }
1380
1381 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
1382 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
1383
1384 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
1385 SSB_SPROM4_TXPID2G0_SHIFT);
1386 @@ -501,7 +503,7 @@ static bool bcma_sprom_onchip_available(
1387 case BCMA_CHIP_ID_BCM4331:
1388 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1389 break;
1390 -
1391 + case BCMA_CHIP_ID_BCM43142:
1392 case BCMA_CHIP_ID_BCM43224:
1393 case BCMA_CHIP_ID_BCM43225:
1394 /* for these chips OTP is always available */
1395 @@ -549,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1396 {
1397 u16 offset = BCMA_CC_SPROM;
1398 u16 *sprom;
1399 - int err = 0;
1400 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1401 + SSB_SPROMSIZE_WORDS_R10, };
1402 + int i, err = 0;
1403
1404 if (!bus->drv_cc.core)
1405 return -EOPNOTSUPP;
1406 @@ -578,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1407 }
1408 }
1409
1410 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1411 - GFP_KERNEL);
1412 - if (!sprom)
1413 - return -ENOMEM;
1414 -
1415 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1416 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1417 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1418
1419 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1420 - bcma_sprom_read(bus, offset, sprom);
1421 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1422 + size_t words = sprom_sizes[i];
1423 +
1424 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1425 + if (!sprom)
1426 + return -ENOMEM;
1427 +
1428 + bcma_sprom_read(bus, offset, sprom, words);
1429 + err = bcma_sprom_valid(bus, sprom, words);
1430 + if (!err)
1431 + break;
1432 +
1433 + kfree(sprom);
1434 + }
1435
1436 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1437 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1438 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1439
1440 - err = bcma_sprom_valid(sprom);
1441 if (err) {
1442 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1443 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1444 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1445 - goto out;
1446 + } else {
1447 + bcma_sprom_extract_r8(bus, sprom);
1448 + kfree(sprom);
1449 }
1450
1451 - bcma_sprom_extract_r8(bus, sprom);
1452 -
1453 -out:
1454 - kfree(sprom);
1455 return err;
1456 }
1457 --- a/include/linux/bcma/bcma.h
1458 +++ b/include/linux/bcma/bcma.h
1459 @@ -72,7 +72,19 @@ struct bcma_host_ops {
1460 /* Core-ID values. */
1461 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1462 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1463 +#define BCMA_CORE_PCIEG2 0x501
1464 +#define BCMA_CORE_DMA 0x502
1465 +#define BCMA_CORE_SDIO3 0x503
1466 +#define BCMA_CORE_USB20 0x504
1467 +#define BCMA_CORE_USB30 0x505
1468 +#define BCMA_CORE_A9JTAG 0x506
1469 +#define BCMA_CORE_DDR23 0x507
1470 +#define BCMA_CORE_ROM 0x508
1471 +#define BCMA_CORE_NAND 0x509
1472 +#define BCMA_CORE_QSPI 0x50A
1473 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
1474 #define BCMA_CORE_4706_SOC_RAM 0x50E
1475 +#define BCMA_CORE_ARMCA9 0x510
1476 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1477 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1478 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1479 @@ -134,12 +146,17 @@ struct bcma_host_ops {
1480 #define BCMA_CORE_I2S 0x834
1481 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
1482 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
1483 +#define BCMA_CORE_PHY_AC 0x83B
1484 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
1485 +#define BCMA_CORE_USB30_DEV 0x83D
1486 +#define BCMA_CORE_ARM_CR4 0x83E
1487 #define BCMA_CORE_DEFAULT 0xFFF
1488
1489 #define BCMA_MAX_NR_CORES 16
1490
1491 /* Chip IDs of PCIe devices */
1492 #define BCMA_CHIP_ID_BCM4313 0x4313
1493 +#define BCMA_CHIP_ID_BCM43142 43142
1494 #define BCMA_CHIP_ID_BCM43224 43224
1495 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1496 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1497 @@ -172,6 +189,65 @@ struct bcma_host_ops {
1498 #define BCMA_PKG_ID_BCM5357 11
1499 #define BCMA_CHIP_ID_BCM53572 53572
1500 #define BCMA_PKG_ID_BCM47188 9
1501 +#define BCMA_CHIP_ID_BCM4707 53010
1502 +#define BCMA_PKG_ID_BCM4707 1
1503 +#define BCMA_PKG_ID_BCM4708 2
1504 +#define BCMA_PKG_ID_BCM4709 0
1505 +#define BCMA_CHIP_ID_BCM53018 53018
1506 +
1507 +/* Board types (on PCI usually equals to the subsystem dev id) */
1508 +/* BCM4313 */
1509 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
1510 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
1511 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
1512 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
1513 +/* BCM4716 */
1514 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
1515 +/* BCM43224 */
1516 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
1517 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
1518 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
1519 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
1520 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
1521 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
1522 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
1523 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
1524 +/* BCM43228 */
1525 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
1526 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
1527 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
1528 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
1529 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
1530 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
1531 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
1532 +/* BCM4331 */
1533 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
1534 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
1535 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
1536 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
1537 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
1538 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
1539 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
1540 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
1541 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
1542 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
1543 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
1544 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
1545 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
1546 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
1547 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
1548 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
1549 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
1550 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
1551 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
1552 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
1553 +/* BCM53572 */
1554 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
1555 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
1556 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
1557 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
1558 +/* BCM43142 */
1559 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
1560
1561 struct bcma_device {
1562 struct bcma_bus *bus;
1563 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1564 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1565 @@ -27,7 +27,7 @@
1566 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
1567 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
1568 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
1569 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
1570 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
1571 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
1572 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
1573 #define BCMA_PLLTYPE_NONE 0x00000000
1574 @@ -104,6 +104,7 @@
1575 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1576 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1577 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1578 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
1579 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1580 #define BCMA_CC_JCMD_START 0x80000000
1581 #define BCMA_CC_JCMD_BUSY 0x80000000
1582 @@ -315,6 +316,9 @@
1583 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
1584 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1585 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
1586 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
1587 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
1588 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
1589 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
1590 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1591 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1592 @@ -326,6 +330,8 @@
1593 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1594 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1595 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1596 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1597 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1598 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1599 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1600 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1601 @@ -351,6 +357,11 @@
1602 #define BCMA_CC_REGCTL_DATA 0x065C
1603 #define BCMA_CC_PLLCTL_ADDR 0x0660
1604 #define BCMA_CC_PLLCTL_DATA 0x0664
1605 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1606 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1607 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1608 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1609 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1610 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1611 /* NAND flash MLC controller registers (corerev >= 38) */
1612 #define BCMA_CC_NAND_REVISION 0x0C00
1613 @@ -431,6 +442,23 @@
1614 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1615 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1616
1617 +/* PMU rev 15 */
1618 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1619 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1620 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1621 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1622 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1623 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1624 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1625 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1626 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1627 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1628 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1629 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1630 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1631 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1632 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1633 +
1634 /* ALP clock on pre-PMU chips */
1635 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1636 /* HT clock for systems with PMU-enabled chipcommon */
1637 @@ -503,6 +531,37 @@
1638 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1639 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1640
1641 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1642 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1643 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1644 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1645 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1646 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1647 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1648 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1649 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1650 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1651 +#define BCMA_RES_4314_OTP_PU BIT(10)
1652 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1653 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1654 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1655 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1656 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1657 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1658 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1659 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1660 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1661 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1662 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1663 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1664 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1665 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1666 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1667 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1668 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1669 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1670 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1671 +
1672 /* Data for the PMU, if available.
1673 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1674 */
1675 @@ -528,6 +587,7 @@ struct bcma_sflash {
1676 u32 size;
1677
1678 struct mtd_info *mtd;
1679 + void *priv;
1680 };
1681 #endif
1682
1683 @@ -606,6 +666,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
1684
1685 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1686
1687 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1688 +
1689 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1690
1691 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
1692 @@ -634,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
1693 u32 offset, u32 mask, u32 set);
1694 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
1695
1696 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1697 +
1698 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1699 --- a/include/linux/bcma/bcma_driver_mips.h
1700 +++ b/include/linux/bcma/bcma_driver_mips.h
1701 @@ -28,6 +28,7 @@
1702 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
1703 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
1704
1705 +#define BCMA_MIPS_OOBSELINA74 0x004
1706 #define BCMA_MIPS_OOBSELOUTA30 0x100
1707
1708 struct bcma_device;
1709 @@ -36,19 +37,23 @@ struct bcma_drv_mips {
1710 struct bcma_device *core;
1711 u8 setup_done:1;
1712 u8 early_setup_done:1;
1713 - unsigned int assigned_irqs;
1714 };
1715
1716 #ifdef CONFIG_BCMA_DRIVER_MIPS
1717 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1718 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1719 +
1720 +extern unsigned int bcma_core_irq(struct bcma_device *core);
1721 #else
1722 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1723 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1724 +
1725 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
1726 +{
1727 + return 0;
1728 +}
1729 #endif
1730
1731 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1732
1733 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
1734 -
1735 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
1736 --- a/include/linux/bcma/bcma_driver_pci.h
1737 +++ b/include/linux/bcma/bcma_driver_pci.h
1738 @@ -179,10 +179,33 @@ struct pci_dev;
1739 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
1740 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
1741
1742 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1743 +
1744 +#define BCMA_CORE_PCI_
1745 +
1746 +/* MDIO devices (SERDES modules) */
1747 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1748 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1749 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1750 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1751 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1752 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1753 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1754 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1755 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1756 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1757 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1758 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1759 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1760 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1761 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1762 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1763 +
1764 /* PCIE Root Capability Register bits (Host mode only) */
1765 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1766
1767 struct bcma_drv_pci;
1768 +struct bcma_bus;
1769
1770 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1771 struct bcma_drv_pci_host {
1772 @@ -217,7 +240,9 @@ struct bcma_drv_pci {
1773 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1774 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1775 struct bcma_device *core, bool enable);
1776 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1777 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1778 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1779 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1780
1781 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1782 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1783 --- a/include/linux/bcma/bcma_regs.h
1784 +++ b/include/linux/bcma/bcma_regs.h
1785 @@ -37,6 +37,7 @@
1786 #define BCMA_IOST_BIST_DONE 0x8000
1787 #define BCMA_RESET_CTL 0x0800
1788 #define BCMA_RESET_CTL_RESET 0x0001
1789 +#define BCMA_RESET_ST 0x0804
1790
1791 /* BCMA PCI config space registers. */
1792 #define BCMA_PCI_PMCSR 0x44
1793 --- a/drivers/bcma/driver_pci.c
1794 +++ b/drivers/bcma/driver_pci.c
1795 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
1796 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1797 }
1798
1799 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1800 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
1801 {
1802 u32 v;
1803 int i;
1804 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
1805 }
1806 }
1807
1808 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1809 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
1810 {
1811 int max_retries = 10;
1812 u16 ret = 0;
1813 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1814 return ret;
1815 }
1816
1817 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1818 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
1819 u8 address, u16 data)
1820 {
1821 int max_retries = 10;
1822 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
1823 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1824 }
1825
1826 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
1827 + u8 address, u16 data)
1828 +{
1829 + bcma_pcie_mdio_write(pc, device, address, data);
1830 + return bcma_pcie_mdio_read(pc, device, address);
1831 +}
1832 +
1833 /**************************************************
1834 * Workarounds.
1835 **************************************************/
1836 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
1837 bcma_core_pci_clientmode_init(pc);
1838 }
1839
1840 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
1841 +{
1842 + struct bcma_drv_pci *pc;
1843 + u16 data;
1844 +
1845 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1846 + return;
1847 +
1848 + pc = &bus->drv_pci[0];
1849 +
1850 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
1851 + data = up ? 0x74 : 0x7C;
1852 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1853 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
1854 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1855 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1856 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
1857 + data = up ? 0x75 : 0x7D;
1858 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1859 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
1860 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1861 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1862 + }
1863 +}
1864 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
1865 +
1866 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1867 bool enable)
1868 {
1869 @@ -262,7 +295,7 @@ out:
1870 }
1871 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1872
1873 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1874 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1875 {
1876 u32 w;
1877
1878 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
1879 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1880 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1881 }
1882 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1883 +
1884 +void bcma_core_pci_up(struct bcma_bus *bus)
1885 +{
1886 + struct bcma_drv_pci *pc;
1887 +
1888 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1889 + return;
1890 +
1891 + pc = &bus->drv_pci[0];
1892 +
1893 + bcma_core_pci_extend_L1timer(pc, true);
1894 +}
1895 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
1896 +
1897 +void bcma_core_pci_down(struct bcma_bus *bus)
1898 +{
1899 + struct bcma_drv_pci *pc;
1900 +
1901 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1902 + return;
1903 +
1904 + pc = &bus->drv_pci[0];
1905 +
1906 + bcma_core_pci_extend_L1timer(pc, false);
1907 +}
1908 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
1909 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1910 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1911 @@ -685,27 +685,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1912 return mode == BCMA_CLKMODE_FAST;
1913 }
1914
1915 -void ai_pci_up(struct si_pub *sih)
1916 -{
1917 - struct si_info *sii;
1918 -
1919 - sii = container_of(sih, struct si_info, pub);
1920 -
1921 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1922 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1923 -}
1924 -
1925 -/* Unconfigure and/or apply various WARs when going down */
1926 -void ai_pci_down(struct si_pub *sih)
1927 -{
1928 - struct si_info *sii;
1929 -
1930 - sii = container_of(sih, struct si_info, pub);
1931 -
1932 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1933 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1934 -}
1935 -
1936 /* Enable BT-COEX & Ex-PA for 4313 */
1937 void ai_epa_4313war(struct si_pub *sih)
1938 {
1939 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1940 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1941 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
1942 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
1943 extern bool ai_deviceremoved(struct si_pub *sih);
1944
1945 -extern void ai_pci_down(struct si_pub *sih);
1946 -extern void ai_pci_up(struct si_pub *sih);
1947 -
1948 /* Enable Ex-PA for 4313 */
1949 extern void ai_epa_4313war(struct si_pub *sih);
1950
1951 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1952 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1953 @@ -4648,7 +4648,7 @@ static int brcms_b_attach(struct brcms_c
1954 brcms_c_coredisable(wlc_hw);
1955
1956 /* Match driver "down" state */
1957 - ai_pci_down(wlc_hw->sih);
1958 + bcma_core_pci_down(wlc_hw->d11core->bus);
1959
1960 /* turn off pll and xtal to match driver "down" state */
1961 brcms_b_xtal(wlc_hw, OFF);
1962 @@ -4991,12 +4991,12 @@ static int brcms_b_up_prep(struct brcms_
1963 */
1964 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1965 /* put SB PCI in down state again */
1966 - ai_pci_down(wlc_hw->sih);
1967 + bcma_core_pci_down(wlc_hw->d11core->bus);
1968 brcms_b_xtal(wlc_hw, OFF);
1969 return -ENOMEDIUM;
1970 }
1971
1972 - ai_pci_up(wlc_hw->sih);
1973 + bcma_core_pci_up(wlc_hw->d11core->bus);
1974
1975 /* reset the d11 core */
1976 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1977 @@ -5193,7 +5193,7 @@ static int brcms_b_down_finish(struct br
1978
1979 /* turn off primary xtal and pll */
1980 if (!wlc_hw->noreset) {
1981 - ai_pci_down(wlc_hw->sih);
1982 + bcma_core_pci_down(wlc_hw->d11core->bus);
1983 brcms_b_xtal(wlc_hw, OFF);
1984 }
1985 }