kernel: bcma: update to wireless-testing master-2013-10-01
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.9 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 --- a/drivers/bcma/bcma_private.h
29 +++ b/drivers/bcma/bcma_private.h
30 @@ -22,6 +22,8 @@
31 struct bcma_bus;
32
33 /* main.c */
34 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
35 + int timeout);
36 int bcma_bus_register(struct bcma_bus *bus);
37 void bcma_bus_unregister(struct bcma_bus *bus);
38 int __init bcma_bus_early_register(struct bcma_bus *bus,
39 --- a/drivers/bcma/core.c
40 +++ b/drivers/bcma/core.c
41 @@ -9,6 +9,25 @@
42 #include <linux/export.h>
43 #include <linux/bcma/bcma.h>
44
45 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
46 + u32 value, int timeout)
47 +{
48 + unsigned long deadline = jiffies + timeout;
49 + u32 val;
50 +
51 + do {
52 + val = bcma_aread32(core, reg);
53 + if ((val & mask) == value)
54 + return true;
55 + cpu_relax();
56 + udelay(10);
57 + } while (!time_after_eq(jiffies, deadline));
58 +
59 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
60 +
61 + return false;
62 +}
63 +
64 bool bcma_core_is_enabled(struct bcma_device *core)
65 {
66 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
67 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
68 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
69 return;
70
71 - bcma_awrite32(core, BCMA_IOCTL, flags);
72 - bcma_aread32(core, BCMA_IOCTL);
73 - udelay(10);
74 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
75
76 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
77 bcma_aread32(core, BCMA_RESET_CTL);
78 udelay(1);
79 +
80 + bcma_awrite32(core, BCMA_IOCTL, flags);
81 + bcma_aread32(core, BCMA_IOCTL);
82 + udelay(10);
83 }
84 EXPORT_SYMBOL_GPL(bcma_core_disable);
85
86 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
87 bcma_aread32(core, BCMA_IOCTL);
88
89 bcma_awrite32(core, BCMA_RESET_CTL, 0);
90 + bcma_aread32(core, BCMA_RESET_CTL);
91 udelay(1);
92
93 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
94 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
95 if (i)
96 bcma_err(core->bus, "PLL enable timeout\n");
97 } else {
98 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
99 + /*
100 + * Mask the PLL but don't wait for it to be disabled. PLL may be
101 + * shared between cores and will be still up if there is another
102 + * core using it.
103 + */
104 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
105 + bcma_read32(core, BCMA_CLKCTLST);
106 }
107 }
108 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
109 --- a/drivers/bcma/driver_chipcommon.c
110 +++ b/drivers/bcma/driver_chipcommon.c
111 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
112 return value;
113 }
114
115 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
116 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
117 {
118 if (cc->capabilities & BCMA_CC_CAP_PMU)
119 return bcma_pmu_get_alp_clock(cc);
120
121 return 20000000;
122 }
123 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
124
125 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
126 {
127 @@ -139,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
128 bcma_core_chipcommon_early_init(cc);
129
130 if (cc->core->id.rev >= 20) {
131 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
132 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
133 + u32 pullup = 0, pulldown = 0;
134 +
135 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
136 + pullup = 0x402e0;
137 + pulldown = 0x20500;
138 + }
139 +
140 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
141 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
142 }
143
144 if (cc->capabilities & BCMA_CC_CAP_PMU)
145 @@ -213,6 +221,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
146
147 return res;
148 }
149 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
150
151 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
152 {
153 @@ -225,6 +234,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
154
155 return res;
156 }
157 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
158
159 /*
160 * If the bit is set to 0, chipcommon controlls this GPIO,
161 --- a/drivers/bcma/driver_chipcommon_pmu.c
162 +++ b/drivers/bcma/driver_chipcommon_pmu.c
163 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
164 }
165 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
166
167 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
168 +{
169 + u32 ilp_ctl, alp_hz;
170 +
171 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
172 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
173 + return 0;
174 +
175 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
176 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
177 + usleep_range(1000, 2000);
178 +
179 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
180 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
181 +
182 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
183 +
184 + alp_hz = ilp_ctl * 32768 / 4;
185 + return (alp_hz + 50000) / 100000 * 100;
186 +}
187 +
188 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
189 +{
190 + struct bcma_bus *bus = cc->core->bus;
191 + u32 freq_tgt_target = 0, freq_tgt_current;
192 + u32 pll0, mask;
193 +
194 + switch (bus->chipinfo.id) {
195 + case BCMA_CHIP_ID_BCM43142:
196 + /* pmu2_xtaltab0_adfll_485 */
197 + switch (xtalfreq) {
198 + case 12000:
199 + freq_tgt_target = 0x50D52;
200 + break;
201 + case 20000:
202 + freq_tgt_target = 0x307FE;
203 + break;
204 + case 26000:
205 + freq_tgt_target = 0x254EA;
206 + break;
207 + case 37400:
208 + freq_tgt_target = 0x19EF8;
209 + break;
210 + case 52000:
211 + freq_tgt_target = 0x12A75;
212 + break;
213 + }
214 + break;
215 + }
216 +
217 + if (!freq_tgt_target) {
218 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
219 + xtalfreq);
220 + return;
221 + }
222 +
223 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
224 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
225 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
226 +
227 + if (freq_tgt_current == freq_tgt_target) {
228 + bcma_debug(bus, "Target TGT frequency already set\n");
229 + return;
230 + }
231 +
232 + /* Turn off PLL */
233 + switch (bus->chipinfo.id) {
234 + case BCMA_CHIP_ID_BCM43142:
235 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
236 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
237 +
238 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
239 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
240 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
241 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
242 + break;
243 + }
244 +
245 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
246 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
247 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
248 +
249 + /* Flush */
250 + if (cc->pmu.rev >= 2)
251 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
252 +
253 + /* TODO: Do we need to update OTP? */
254 +}
255 +
256 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
257 +{
258 + struct bcma_bus *bus = cc->core->bus;
259 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
260 +
261 + switch (bus->chipinfo.id) {
262 + case BCMA_CHIP_ID_BCM43142:
263 + if (xtalfreq == 0)
264 + xtalfreq = 20000;
265 + bcma_pmu2_pll_init0(cc, xtalfreq);
266 + break;
267 + }
268 +}
269 +
270 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
271 {
272 struct bcma_bus *bus = cc->core->bus;
273 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
274 min_msk = 0x200D;
275 max_msk = 0xFFFF;
276 break;
277 + case BCMA_CHIP_ID_BCM43142:
278 + min_msk = BCMA_RES_4314_LPLDO_PU |
279 + BCMA_RES_4314_PMU_SLEEP_DIS |
280 + BCMA_RES_4314_PMU_BG_PU |
281 + BCMA_RES_4314_CBUCK_LPOM_PU |
282 + BCMA_RES_4314_CBUCK_PFM_PU |
283 + BCMA_RES_4314_CLDO_PU |
284 + BCMA_RES_4314_LPLDO2_LVM |
285 + BCMA_RES_4314_WL_PMU_PU |
286 + BCMA_RES_4314_LDO3P3_PU |
287 + BCMA_RES_4314_OTP_PU |
288 + BCMA_RES_4314_WL_PWRSW_PU |
289 + BCMA_RES_4314_LQ_AVAIL |
290 + BCMA_RES_4314_LOGIC_RET |
291 + BCMA_RES_4314_MEM_SLEEP |
292 + BCMA_RES_4314_MACPHY_RET |
293 + BCMA_RES_4314_WL_CORE_READY;
294 + max_msk = 0x3FFFFFFF;
295 + break;
296 default:
297 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
298 bus->chipinfo.id);
299 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
300 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
301 BCMA_CC_PMU_CTL_NOILPONW);
302
303 + bcma_pmu_pll_init(cc);
304 bcma_pmu_resources_init(cc);
305 bcma_pmu_workarounds(cc);
306 }
307 @@ -174,19 +297,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
308 struct bcma_bus *bus = cc->core->bus;
309
310 switch (bus->chipinfo.id) {
311 + case BCMA_CHIP_ID_BCM4313:
312 + case BCMA_CHIP_ID_BCM43224:
313 + case BCMA_CHIP_ID_BCM43225:
314 + case BCMA_CHIP_ID_BCM43227:
315 + case BCMA_CHIP_ID_BCM43228:
316 + case BCMA_CHIP_ID_BCM4331:
317 + case BCMA_CHIP_ID_BCM43421:
318 + case BCMA_CHIP_ID_BCM43428:
319 + case BCMA_CHIP_ID_BCM43431:
320 case BCMA_CHIP_ID_BCM4716:
321 - case BCMA_CHIP_ID_BCM4748:
322 case BCMA_CHIP_ID_BCM47162:
323 - case BCMA_CHIP_ID_BCM4313:
324 - case BCMA_CHIP_ID_BCM5357:
325 + case BCMA_CHIP_ID_BCM4748:
326 case BCMA_CHIP_ID_BCM4749:
327 + case BCMA_CHIP_ID_BCM5357:
328 case BCMA_CHIP_ID_BCM53572:
329 + case BCMA_CHIP_ID_BCM6362:
330 /* always 20Mhz */
331 return 20000 * 1000;
332 - case BCMA_CHIP_ID_BCM5356:
333 case BCMA_CHIP_ID_BCM4706:
334 + case BCMA_CHIP_ID_BCM5356:
335 /* always 25Mhz */
336 return 25000 * 1000;
337 + case BCMA_CHIP_ID_BCM43460:
338 + case BCMA_CHIP_ID_BCM4352:
339 + case BCMA_CHIP_ID_BCM4360:
340 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
341 + return 40000 * 1000;
342 + else
343 + return 20000 * 1000;
344 default:
345 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
346 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
347 @@ -373,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
348 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
349 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
350
351 - tmp = 1 << 10;
352 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
353 break;
354
355 case BCMA_CHIP_ID_BCM4331:
356 @@ -394,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
357 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
358 0x03000a08);
359 }
360 - tmp = 1 << 10;
361 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
362 break;
363
364 case BCMA_CHIP_ID_BCM43224:
365 @@ -427,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
366 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
367 0x88888815);
368 }
369 - tmp = 1 << 10;
370 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
371 break;
372
373 case BCMA_CHIP_ID_BCM4716:
374 @@ -461,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
375 0x88888815);
376 }
377
378 - tmp = 3 << 9;
379 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
380 break;
381
382 case BCMA_CHIP_ID_BCM43227:
383 @@ -497,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
384 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
385 0x88888815);
386 }
387 - tmp = 1 << 10;
388 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
389 break;
390 default:
391 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
392 --- a/drivers/bcma/driver_chipcommon_sflash.c
393 +++ b/drivers/bcma/driver_chipcommon_sflash.c
394 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
395 u16 numblocks;
396 };
397
398 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
399 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
400 { "M25P20", 0x11, 0x10000, 4, },
401 { "M25P40", 0x12, 0x10000, 8, },
402
403 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
404 { 0 },
405 };
406
407 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
408 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
409 { "SST25WF512", 1, 0x1000, 16, },
410 { "SST25VF512", 0x48, 0x1000, 16, },
411 { "SST25WF010", 2, 0x1000, 32, },
412 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
413 { 0 },
414 };
415
416 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
417 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
418 { "AT45DB011", 0xc, 256, 512, },
419 { "AT45DB021", 0x14, 256, 1024, },
420 { "AT45DB041", 0x1c, 256, 2048, },
421 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
422 {
423 struct bcma_bus *bus = cc->core->bus;
424 struct bcma_sflash *sflash = &cc->sflash;
425 - struct bcma_sflash_tbl_e *e;
426 + const struct bcma_sflash_tbl_e *e;
427 u32 id, id2;
428
429 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
430 --- a/drivers/bcma/host_pci.c
431 +++ b/drivers/bcma/host_pci.c
432 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
433 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
434 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
435 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
436 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
437 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
438 { 0, },
439 };
440 --- a/drivers/bcma/main.c
441 +++ b/drivers/bcma/main.c
442 @@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(
443 return NULL;
444 }
445
446 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
447 + int timeout)
448 +{
449 + unsigned long deadline = jiffies + timeout;
450 + u32 val;
451 +
452 + do {
453 + val = bcma_read32(core, reg);
454 + if ((val & mask) == value)
455 + return true;
456 + cpu_relax();
457 + udelay(10);
458 + } while (!time_after_eq(jiffies, deadline));
459 +
460 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
461 +
462 + return false;
463 +}
464 +
465 static void bcma_release_core_dev(struct device *dev)
466 {
467 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
468 @@ -120,6 +139,11 @@ static int bcma_register_cores(struct bc
469 continue;
470 }
471
472 + /* Only first GMAC core on BCM4706 is connected and working */
473 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
474 + core->core_unit > 0)
475 + continue;
476 +
477 core->dev.release = bcma_release_core_dev;
478 core->dev.bus = &bcma_bus_type;
479 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
480 @@ -213,7 +237,7 @@ int bcma_bus_register(struct bcma_bus *b
481 err = bcma_bus_scan(bus);
482 if (err) {
483 bcma_err(bus, "Failed to scan: %d\n", err);
484 - return -1;
485 + return err;
486 }
487
488 /* Early init CC core */
489 --- a/drivers/bcma/scan.c
490 +++ b/drivers/bcma/scan.c
491 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
492 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
493 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
494 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
495 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
496 + { BCMA_CORE_DMA, "DMA" },
497 + { BCMA_CORE_SDIO3, "SDIO3" },
498 + { BCMA_CORE_USB20, "USB 2.0" },
499 + { BCMA_CORE_USB30, "USB 3.0" },
500 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
501 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
502 + { BCMA_CORE_ROM, "ROM" },
503 + { BCMA_CORE_NAND, "NAND flash controller" },
504 + { BCMA_CORE_QSPI, "SPI flash controller" },
505 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
506 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
507 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
508 { BCMA_CORE_ALTA, "ALTA (I2S)" },
509 { BCMA_CORE_INVALID, "Invalid" },
510 @@ -84,6 +96,8 @@ static const struct bcma_device_id_name
511 { BCMA_CORE_I2S, "I2S" },
512 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
513 { BCMA_CORE_SHIM, "SHIM" },
514 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
515 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
516 { BCMA_CORE_DEFAULT, "Default" },
517 };
518
519 @@ -137,19 +151,19 @@ static void bcma_scan_switch_core(struct
520 addr);
521 }
522
523 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
524 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
525 {
526 u32 ent = readl(*eromptr);
527 (*eromptr)++;
528 return ent;
529 }
530
531 -static void bcma_erom_push_ent(u32 **eromptr)
532 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
533 {
534 (*eromptr)--;
535 }
536
537 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
538 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
539 {
540 u32 ent = bcma_erom_get_ent(bus, eromptr);
541 if (!(ent & SCAN_ER_VALID))
542 @@ -159,14 +173,14 @@ static s32 bcma_erom_get_ci(struct bcma_
543 return ent;
544 }
545
546 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
547 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
548 {
549 u32 ent = bcma_erom_get_ent(bus, eromptr);
550 bcma_erom_push_ent(eromptr);
551 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
552 }
553
554 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
555 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
556 {
557 u32 ent = bcma_erom_get_ent(bus, eromptr);
558 bcma_erom_push_ent(eromptr);
559 @@ -175,7 +189,7 @@ static bool bcma_erom_is_bridge(struct b
560 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
561 }
562
563 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
564 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
565 {
566 u32 ent;
567 while (1) {
568 @@ -189,7 +203,7 @@ static void bcma_erom_skip_component(str
569 bcma_erom_push_ent(eromptr);
570 }
571
572 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
573 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
574 {
575 u32 ent = bcma_erom_get_ent(bus, eromptr);
576 if (!(ent & SCAN_ER_VALID))
577 @@ -199,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
578 return ent;
579 }
580
581 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
582 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
583 u32 type, u8 port)
584 {
585 u32 addrl, addrh, sizel, sizeh = 0;
586 @@ -211,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
587 ((ent & SCAN_ADDR_TYPE) != type) ||
588 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
589 bcma_erom_push_ent(eromptr);
590 - return -EINVAL;
591 + return (u32)-EINVAL;
592 }
593
594 addrl = ent & SCAN_ADDR_ADDR;
595 @@ -255,11 +269,13 @@ static struct bcma_device *bcma_find_cor
596 return NULL;
597 }
598
599 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
600 +
601 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
602 struct bcma_device_id *match, int core_num,
603 struct bcma_device *core)
604 {
605 - s32 tmp;
606 + u32 tmp;
607 u8 i, j;
608 s32 cia, cib;
609 u8 ports[2], wrappers[2];
610 @@ -337,11 +353,11 @@ static int bcma_get_next_core(struct bcm
611 * the main register space for the core
612 */
613 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
614 - if (tmp <= 0) {
615 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
616 /* Try again to see if it is a bridge */
617 tmp = bcma_erom_get_addr_desc(bus, eromptr,
618 SCAN_ADDR_TYPE_BRIDGE, 0);
619 - if (tmp <= 0) {
620 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
621 return -EILSEQ;
622 } else {
623 bcma_info(bus, "Bridge found\n");
624 @@ -355,7 +371,7 @@ static int bcma_get_next_core(struct bcm
625 for (j = 0; ; j++) {
626 tmp = bcma_erom_get_addr_desc(bus, eromptr,
627 SCAN_ADDR_TYPE_SLAVE, i);
628 - if (tmp < 0) {
629 + if (IS_ERR_VALUE_U32(tmp)) {
630 /* no more entries for port _i_ */
631 /* pr_debug("erom: slave port %d "
632 * "has %d descriptors\n", i, j); */
633 @@ -372,7 +388,7 @@ static int bcma_get_next_core(struct bcm
634 for (j = 0; ; j++) {
635 tmp = bcma_erom_get_addr_desc(bus, eromptr,
636 SCAN_ADDR_TYPE_MWRAP, i);
637 - if (tmp < 0) {
638 + if (IS_ERR_VALUE_U32(tmp)) {
639 /* no more entries for port _i_ */
640 /* pr_debug("erom: master wrapper %d "
641 * "has %d descriptors\n", i, j); */
642 @@ -390,7 +406,7 @@ static int bcma_get_next_core(struct bcm
643 for (j = 0; ; j++) {
644 tmp = bcma_erom_get_addr_desc(bus, eromptr,
645 SCAN_ADDR_TYPE_SWRAP, i + hack);
646 - if (tmp < 0) {
647 + if (IS_ERR_VALUE_U32(tmp)) {
648 /* no more entries for port _i_ */
649 /* pr_debug("erom: master wrapper %d "
650 * has %d descriptors\n", i, j); */
651 --- a/drivers/bcma/sprom.c
652 +++ b/drivers/bcma/sprom.c
653 @@ -72,12 +72,12 @@ fail:
654 * R/W ops.
655 **************************************************/
656
657 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
658 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
659 + size_t words)
660 {
661 int i;
662 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
663 - sprom[i] = bcma_read16(bus->drv_cc.core,
664 - offset + (i * 2));
665 + for (i = 0; i < words; i++)
666 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
667 }
668
669 /**************************************************
670 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
671 return t[crc ^ data];
672 }
673
674 -static u8 bcma_sprom_crc(const u16 *sprom)
675 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
676 {
677 int word;
678 u8 crc = 0xFF;
679
680 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
681 + for (word = 0; word < words - 1; word++) {
682 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
683 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
684 }
685 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
686 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
687 crc ^= 0xFF;
688
689 return crc;
690 }
691
692 -static int bcma_sprom_check_crc(const u16 *sprom)
693 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
694 {
695 u8 crc;
696 u8 expected_crc;
697 u16 tmp;
698
699 - crc = bcma_sprom_crc(sprom);
700 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
701 + crc = bcma_sprom_crc(sprom, words);
702 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
703 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
704 if (crc != expected_crc)
705 return -EPROTO;
706 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
707 return 0;
708 }
709
710 -static int bcma_sprom_valid(const u16 *sprom)
711 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
712 + size_t words)
713 {
714 u16 revision;
715 int err;
716
717 - err = bcma_sprom_check_crc(sprom);
718 + err = bcma_sprom_check_crc(sprom, words);
719 if (err)
720 return err;
721
722 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
723 - if (revision != 8 && revision != 9) {
724 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
725 + if (revision != 8 && revision != 9 && revision != 10) {
726 pr_err("Unsupported SPROM revision: %d\n", revision);
727 return -ENOENT;
728 }
729
730 + bus->sprom.revision = revision;
731 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
732 +
733 return 0;
734 }
735
736 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
737 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
738 ARRAY_SIZE(bus->sprom.core_pwr_info));
739
740 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
741 - SSB_SPROM_REVISION_REV;
742 -
743 for (i = 0; i < 3; i++) {
744 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
745 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
746 }
747
748 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
749 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
750
751 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
752 SSB_SPROM4_TXPID2G0_SHIFT);
753 @@ -501,7 +503,7 @@ static bool bcma_sprom_onchip_available(
754 case BCMA_CHIP_ID_BCM4331:
755 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
756 break;
757 -
758 + case BCMA_CHIP_ID_BCM43142:
759 case BCMA_CHIP_ID_BCM43224:
760 case BCMA_CHIP_ID_BCM43225:
761 /* for these chips OTP is always available */
762 @@ -549,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
763 {
764 u16 offset = BCMA_CC_SPROM;
765 u16 *sprom;
766 - int err = 0;
767 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
768 + SSB_SPROMSIZE_WORDS_R10, };
769 + int i, err = 0;
770
771 if (!bus->drv_cc.core)
772 return -EOPNOTSUPP;
773 @@ -578,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
774 }
775 }
776
777 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
778 - GFP_KERNEL);
779 - if (!sprom)
780 - return -ENOMEM;
781 -
782 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
783 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
784 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
785
786 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
787 - bcma_sprom_read(bus, offset, sprom);
788 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
789 + size_t words = sprom_sizes[i];
790 +
791 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
792 + if (!sprom)
793 + return -ENOMEM;
794 +
795 + bcma_sprom_read(bus, offset, sprom, words);
796 + err = bcma_sprom_valid(bus, sprom, words);
797 + if (!err)
798 + break;
799 +
800 + kfree(sprom);
801 + }
802
803 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
804 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
805 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
806
807 - err = bcma_sprom_valid(sprom);
808 if (err) {
809 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
810 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
811 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
812 - goto out;
813 + } else {
814 + bcma_sprom_extract_r8(bus, sprom);
815 + kfree(sprom);
816 }
817
818 - bcma_sprom_extract_r8(bus, sprom);
819 -
820 -out:
821 - kfree(sprom);
822 return err;
823 }
824 --- a/include/linux/bcma/bcma.h
825 +++ b/include/linux/bcma/bcma.h
826 @@ -72,7 +72,19 @@ struct bcma_host_ops {
827 /* Core-ID values. */
828 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
829 #define BCMA_CORE_4706_CHIPCOMMON 0x500
830 +#define BCMA_CORE_PCIEG2 0x501
831 +#define BCMA_CORE_DMA 0x502
832 +#define BCMA_CORE_SDIO3 0x503
833 +#define BCMA_CORE_USB20 0x504
834 +#define BCMA_CORE_USB30 0x505
835 +#define BCMA_CORE_A9JTAG 0x506
836 +#define BCMA_CORE_DDR23 0x507
837 +#define BCMA_CORE_ROM 0x508
838 +#define BCMA_CORE_NAND 0x509
839 +#define BCMA_CORE_QSPI 0x50A
840 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
841 #define BCMA_CORE_4706_SOC_RAM 0x50E
842 +#define BCMA_CORE_ARMCA9 0x510
843 #define BCMA_CORE_4706_MAC_GBIT 0x52D
844 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
845 #define BCMA_CORE_ALTA 0x534 /* I2S core */
846 @@ -134,12 +146,17 @@ struct bcma_host_ops {
847 #define BCMA_CORE_I2S 0x834
848 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
849 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
850 +#define BCMA_CORE_PHY_AC 0x83B
851 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
852 +#define BCMA_CORE_USB30_DEV 0x83D
853 +#define BCMA_CORE_ARM_CR4 0x83E
854 #define BCMA_CORE_DEFAULT 0xFFF
855
856 #define BCMA_MAX_NR_CORES 16
857
858 /* Chip IDs of PCIe devices */
859 #define BCMA_CHIP_ID_BCM4313 0x4313
860 +#define BCMA_CHIP_ID_BCM43142 43142
861 #define BCMA_CHIP_ID_BCM43224 43224
862 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
863 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
864 @@ -172,6 +189,65 @@ struct bcma_host_ops {
865 #define BCMA_PKG_ID_BCM5357 11
866 #define BCMA_CHIP_ID_BCM53572 53572
867 #define BCMA_PKG_ID_BCM47188 9
868 +#define BCMA_CHIP_ID_BCM4707 53010
869 +#define BCMA_PKG_ID_BCM4707 1
870 +#define BCMA_PKG_ID_BCM4708 2
871 +#define BCMA_PKG_ID_BCM4709 0
872 +#define BCMA_CHIP_ID_BCM53018 53018
873 +
874 +/* Board types (on PCI usually equals to the subsystem dev id) */
875 +/* BCM4313 */
876 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
877 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
878 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
879 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
880 +/* BCM4716 */
881 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
882 +/* BCM43224 */
883 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
884 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
885 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
886 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
887 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
888 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
889 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
890 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
891 +/* BCM43228 */
892 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
893 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
894 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
895 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
896 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
897 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
898 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
899 +/* BCM4331 */
900 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
901 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
902 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
903 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
904 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
905 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
906 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
907 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
908 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
909 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
910 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
911 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
912 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
913 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
914 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
915 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
916 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
917 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
918 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
919 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
920 +/* BCM53572 */
921 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
922 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
923 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
924 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
925 +/* BCM43142 */
926 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
927
928 struct bcma_device {
929 struct bcma_bus *bus;
930 --- a/include/linux/bcma/bcma_driver_chipcommon.h
931 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
932 @@ -104,6 +104,7 @@
933 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
934 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
935 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
936 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
937 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
938 #define BCMA_CC_JCMD_START 0x80000000
939 #define BCMA_CC_JCMD_BUSY 0x80000000
940 @@ -315,6 +316,9 @@
941 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
942 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
943 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
944 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
945 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
946 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
947 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
948 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
949 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
950 @@ -326,6 +330,8 @@
951 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
952 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
953 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
954 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
955 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
956 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
957 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
958 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
959 @@ -351,6 +357,11 @@
960 #define BCMA_CC_REGCTL_DATA 0x065C
961 #define BCMA_CC_PLLCTL_ADDR 0x0660
962 #define BCMA_CC_PLLCTL_DATA 0x0664
963 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
964 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
965 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
966 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
967 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
968 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
969 /* NAND flash MLC controller registers (corerev >= 38) */
970 #define BCMA_CC_NAND_REVISION 0x0C00
971 @@ -431,6 +442,23 @@
972 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
973 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
974
975 +/* PMU rev 15 */
976 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
977 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
978 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
979 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
980 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
981 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
982 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
983 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
984 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
985 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
986 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
987 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
988 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
989 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
990 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
991 +
992 /* ALP clock on pre-PMU chips */
993 #define BCMA_CC_PMU_ALP_CLOCK 20000000
994 /* HT clock for systems with PMU-enabled chipcommon */
995 @@ -503,6 +531,37 @@
996 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
997 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
998
999 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1000 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1001 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1002 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1003 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1004 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1005 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1006 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1007 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1008 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1009 +#define BCMA_RES_4314_OTP_PU BIT(10)
1010 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1011 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1012 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1013 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1014 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1015 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1016 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1017 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1018 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1019 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1020 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1021 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1022 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1023 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1024 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1025 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1026 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1027 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1028 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1029 +
1030 /* Data for the PMU, if available.
1031 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1032 */
1033 @@ -607,6 +666,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
1034
1035 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1036
1037 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1038 +
1039 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1040
1041 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
1042 --- a/include/linux/bcma/bcma_regs.h
1043 +++ b/include/linux/bcma/bcma_regs.h
1044 @@ -37,6 +37,7 @@
1045 #define BCMA_IOST_BIST_DONE 0x8000
1046 #define BCMA_RESET_CTL 0x0800
1047 #define BCMA_RESET_CTL_RESET 0x0001
1048 +#define BCMA_RESET_ST 0x0804
1049
1050 /* BCMA PCI config space registers. */
1051 #define BCMA_PCI_PMCSR 0x44
1052 --- a/drivers/bcma/driver_pci.c
1053 +++ b/drivers/bcma/driver_pci.c
1054 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
1055 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1056 }
1057
1058 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1059 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
1060 {
1061 u32 v;
1062 int i;
1063 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
1064 }
1065 }
1066
1067 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1068 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
1069 {
1070 int max_retries = 10;
1071 u16 ret = 0;
1072 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1073 return ret;
1074 }
1075
1076 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1077 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
1078 u8 address, u16 data)
1079 {
1080 int max_retries = 10;
1081 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
1082 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1083 }
1084
1085 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
1086 + u8 address, u16 data)
1087 +{
1088 + bcma_pcie_mdio_write(pc, device, address, data);
1089 + return bcma_pcie_mdio_read(pc, device, address);
1090 +}
1091 +
1092 /**************************************************
1093 * Workarounds.
1094 **************************************************/
1095 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
1096 bcma_core_pci_clientmode_init(pc);
1097 }
1098
1099 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
1100 +{
1101 + struct bcma_drv_pci *pc;
1102 + u16 data;
1103 +
1104 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1105 + return;
1106 +
1107 + pc = &bus->drv_pci[0];
1108 +
1109 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
1110 + data = up ? 0x74 : 0x7C;
1111 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1112 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
1113 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1114 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1115 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
1116 + data = up ? 0x75 : 0x7D;
1117 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1118 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
1119 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1120 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1121 + }
1122 +}
1123 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
1124 +
1125 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1126 bool enable)
1127 {
1128 @@ -262,7 +295,7 @@ out:
1129 }
1130 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1131
1132 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1133 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1134 {
1135 u32 w;
1136
1137 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
1138 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1139 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1140 }
1141 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1142 +
1143 +void bcma_core_pci_up(struct bcma_bus *bus)
1144 +{
1145 + struct bcma_drv_pci *pc;
1146 +
1147 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1148 + return;
1149 +
1150 + pc = &bus->drv_pci[0];
1151 +
1152 + bcma_core_pci_extend_L1timer(pc, true);
1153 +}
1154 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
1155 +
1156 +void bcma_core_pci_down(struct bcma_bus *bus)
1157 +{
1158 + struct bcma_drv_pci *pc;
1159 +
1160 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1161 + return;
1162 +
1163 + pc = &bus->drv_pci[0];
1164 +
1165 + bcma_core_pci_extend_L1timer(pc, false);
1166 +}
1167 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
1168 --- a/drivers/bcma/driver_pci_host.c
1169 +++ b/drivers/bcma/driver_pci_host.c
1170 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
1171 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1172 {
1173 struct bcma_drv_pci_host *pc_host;
1174 + int readrq;
1175
1176 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1177 /* This is not a device on the PCI-core bridge. */
1178 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
1179 dev->irq = bcma_core_irq(pc_host->pdev->core);
1180 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1181
1182 + readrq = pcie_get_readrq(dev);
1183 + if (readrq > 128) {
1184 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
1185 + pcie_set_readrq(dev, 128);
1186 + }
1187 return 0;
1188 }
1189 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1190 --- a/include/linux/bcma/bcma_driver_pci.h
1191 +++ b/include/linux/bcma/bcma_driver_pci.h
1192 @@ -181,10 +181,31 @@ struct pci_dev;
1193
1194 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1195
1196 +#define BCMA_CORE_PCI_
1197 +
1198 +/* MDIO devices (SERDES modules) */
1199 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1200 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1201 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1202 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1203 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1204 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1205 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1206 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1207 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1208 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1209 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1210 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1211 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1212 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1213 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1214 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1215 +
1216 /* PCIE Root Capability Register bits (Host mode only) */
1217 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1218
1219 struct bcma_drv_pci;
1220 +struct bcma_bus;
1221
1222 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1223 struct bcma_drv_pci_host {
1224 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1225 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1226 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1227 struct bcma_device *core, bool enable);
1228 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1229 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1230 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1231 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1232
1233 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1234 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1235 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1236 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1237 @@ -685,27 +685,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1238 return mode == BCMA_CLKMODE_FAST;
1239 }
1240
1241 -void ai_pci_up(struct si_pub *sih)
1242 -{
1243 - struct si_info *sii;
1244 -
1245 - sii = container_of(sih, struct si_info, pub);
1246 -
1247 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1248 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1249 -}
1250 -
1251 -/* Unconfigure and/or apply various WARs when going down */
1252 -void ai_pci_down(struct si_pub *sih)
1253 -{
1254 - struct si_info *sii;
1255 -
1256 - sii = container_of(sih, struct si_info, pub);
1257 -
1258 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1259 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1260 -}
1261 -
1262 /* Enable BT-COEX & Ex-PA for 4313 */
1263 void ai_epa_4313war(struct si_pub *sih)
1264 {
1265 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1266 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1267 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
1268 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
1269 extern bool ai_deviceremoved(struct si_pub *sih);
1270
1271 -extern void ai_pci_down(struct si_pub *sih);
1272 -extern void ai_pci_up(struct si_pub *sih);
1273 -
1274 /* Enable Ex-PA for 4313 */
1275 extern void ai_epa_4313war(struct si_pub *sih);
1276
1277 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1278 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1279 @@ -4644,7 +4644,7 @@ static int brcms_b_attach(struct brcms_c
1280 brcms_c_coredisable(wlc_hw);
1281
1282 /* Match driver "down" state */
1283 - ai_pci_down(wlc_hw->sih);
1284 + bcma_core_pci_down(wlc_hw->d11core->bus);
1285
1286 /* turn off pll and xtal to match driver "down" state */
1287 brcms_b_xtal(wlc_hw, OFF);
1288 @@ -4987,12 +4987,12 @@ static int brcms_b_up_prep(struct brcms_
1289 */
1290 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1291 /* put SB PCI in down state again */
1292 - ai_pci_down(wlc_hw->sih);
1293 + bcma_core_pci_down(wlc_hw->d11core->bus);
1294 brcms_b_xtal(wlc_hw, OFF);
1295 return -ENOMEDIUM;
1296 }
1297
1298 - ai_pci_up(wlc_hw->sih);
1299 + bcma_core_pci_up(wlc_hw->d11core->bus);
1300
1301 /* reset the d11 core */
1302 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1303 @@ -5189,7 +5189,7 @@ static int brcms_b_down_finish(struct br
1304
1305 /* turn off primary xtal and pll */
1306 if (!wlc_hw->noreset) {
1307 - ai_pci_down(wlc_hw->sih);
1308 + bcma_core_pci_down(wlc_hw->d11core->bus);
1309 brcms_b_xtal(wlc_hw, OFF);
1310 }
1311 }