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c5bfb9f152f7c7395506497e23ceed9235bb822b
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-4.3 / 022-bcma-from-4.6.patch
1 --- a/drivers/bcma/driver_chipcommon.c
2 +++ b/drivers/bcma/driver_chipcommon.c
3 @@ -15,6 +15,8 @@
4 #include <linux/platform_device.h>
5 #include <linux/bcma/bcma.h>
6
7 +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
8 +
9 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
10 u32 mask, u32 value)
11 {
12 @@ -115,6 +117,8 @@ int bcma_chipco_watchdog_register(struct
13
14 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
15 {
16 + struct bcma_bus *bus = cc->core->bus;
17 +
18 if (cc->early_setup_done)
19 return;
20
21 @@ -129,6 +133,9 @@ void bcma_core_chipcommon_early_init(str
22 if (cc->capabilities & BCMA_CC_CAP_PMU)
23 bcma_pmu_early_init(cc);
24
25 + if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
26 + bcma_chipco_serial_init(cc);
27 +
28 cc->early_setup_done = true;
29 }
30
31 @@ -185,11 +192,12 @@ u32 bcma_chipco_watchdog_timer_set(struc
32 ticks = 2;
33 else if (ticks > maxt)
34 ticks = maxt;
35 - bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
36 + bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
37 } else {
38 struct bcma_bus *bus = cc->core->bus;
39
40 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
41 + bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
42 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
43 bcma_core_set_clockmode(cc->core,
44 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
45 @@ -314,9 +322,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm
46 return res;
47 }
48
49 -#ifdef CONFIG_BCMA_DRIVER_MIPS
50 -void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
51 +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
52 {
53 +#if IS_BUILTIN(CONFIG_BCM47XX)
54 unsigned int irq;
55 u32 baud_base;
56 u32 i;
57 @@ -358,5 +366,5 @@ void bcma_chipco_serial_init(struct bcma
58 ports[i].baud_base = baud_base;
59 ports[i].reg_shift = 0;
60 }
61 +#endif /* CONFIG_BCM47XX */
62 }
63 -#endif /* CONFIG_BCMA_DRIVER_MIPS */
64 --- a/drivers/bcma/driver_chipcommon_pmu.c
65 +++ b/drivers/bcma/driver_chipcommon_pmu.c
66 @@ -15,44 +15,44 @@
67
68 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
69 {
70 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
71 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
72 - return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
73 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
74 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
75 + return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
76 }
77 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
78
79 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
80 {
81 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
82 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
83 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
84 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
85 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
86 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
87 }
88 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
89
90 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
91 u32 set)
92 {
93 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
94 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
95 - bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
96 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
97 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
98 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
99 }
100 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
101
102 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
103 u32 offset, u32 mask, u32 set)
104 {
105 - bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
106 - bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
107 - bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
108 + bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
109 + bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
110 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
111 }
112 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
113
114 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
115 u32 set)
116 {
117 - bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
118 - bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
119 - bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
120 + bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
121 + bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
122 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
123 }
124 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
125
126 @@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
127 {
128 u32 ilp_ctl, alp_hz;
129
130 - if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
131 + if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
132 BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
133 return 0;
134
135 - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
136 - BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
137 + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
138 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
139 usleep_range(1000, 2000);
140
141 - ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
142 + ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
143 ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
144
145 - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
146 + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
147
148 alp_hz = ilp_ctl * 32768 / 4;
149 return (alp_hz + 50000) / 100000 * 100;
150 @@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
151 mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
152 BCMA_RES_4314_MACPHY_CLK_AVAIL);
153
154 - bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
155 - bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
156 + bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
157 + bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
158 bcma_wait_value(cc->core, BCMA_CLKCTLST,
159 BCMA_CLKCTLST_HAVEHT, 0, 20000);
160 break;
161 @@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
162
163 /* Flush */
164 if (cc->pmu.rev >= 2)
165 - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
166 + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
167
168 /* TODO: Do we need to update OTP? */
169 }
170 @@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
171
172 /* Set the resource masks. */
173 if (min_msk)
174 - bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
175 + bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
176 if (max_msk)
177 - bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
178 + bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
179
180 /*
181 * Add some delay; allow resources to come up and settle.
182 @@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
183
184 void bcma_pmu_early_init(struct bcma_drv_cc *cc)
185 {
186 + struct bcma_bus *bus = cc->core->bus;
187 u32 pmucap;
188
189 - pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
190 + if (cc->core->id.rev >= 35 &&
191 + cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
192 + cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
193 + if (!cc->pmu.core)
194 + bcma_warn(bus, "Couldn't find expected PMU core");
195 + }
196 + if (!cc->pmu.core)
197 + cc->pmu.core = cc->core;
198 +
199 + pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
200 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
201
202 - bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
203 - cc->pmu.rev, pmucap);
204 + bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
205 + pmucap);
206 }
207
208 void bcma_pmu_init(struct bcma_drv_cc *cc)
209 {
210 if (cc->pmu.rev == 1)
211 - bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
212 - ~BCMA_CC_PMU_CTL_NOILPONW);
213 + bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
214 + ~BCMA_CC_PMU_CTL_NOILPONW);
215 else
216 - bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
217 - BCMA_CC_PMU_CTL_NOILPONW);
218 + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
219 + BCMA_CC_PMU_CTL_NOILPONW);
220
221 bcma_pmu_pll_init(cc);
222 bcma_pmu_resources_init(cc);
223 @@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
224 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
225 u32 value)
226 {
227 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
228 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
229 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
230 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
231 }
232
233 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
234 @@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
235 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
236
237 /* RMW only the P1 divider */
238 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
239 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
240 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
241 - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
242 + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
243 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
244 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
245 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
246 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
247
248 /* RMW only the int feedback divider */
249 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
250 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
251 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
252 - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
253 + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
254 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
255 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
256 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
257 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
258
259 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
260 break;
261 @@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
262 break;
263 }
264
265 - tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
266 - bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
267 + tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
268 + bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
269 }
270 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
271 --- a/drivers/bcma/driver_chipcommon_sflash.c
272 +++ b/drivers/bcma/driver_chipcommon_sflash.c
273 @@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
274 { "M25P32", 0x15, 0x10000, 64, },
275 { "M25P64", 0x16, 0x10000, 128, },
276 { "M25FL128", 0x17, 0x10000, 256, },
277 + { "MX25L25635F", 0x18, 0x10000, 512, },
278 { NULL },
279 };
280
281 --- a/drivers/bcma/scan.c
282 +++ b/drivers/bcma/scan.c
283 @@ -98,6 +98,9 @@ static const struct bcma_device_id_name
284 { BCMA_CORE_SHIM, "SHIM" },
285 { BCMA_CORE_PCIE2, "PCIe Gen2" },
286 { BCMA_CORE_ARM_CR4, "ARM CR4" },
287 + { BCMA_CORE_GCI, "GCI" },
288 + { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
289 + { BCMA_CORE_ARM_CA7, "ARM CA7" },
290 { BCMA_CORE_DEFAULT, "Default" },
291 };
292
293 @@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
294 switch (core->id.id) {
295 case BCMA_CORE_4706_MAC_GBIT_COMMON:
296 case BCMA_CORE_NS_CHIPCOMMON_B:
297 + case BCMA_CORE_PMU:
298 + case BCMA_CORE_GCI:
299 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
300 break;
301 default:
302 --- a/drivers/net/wireless/b43/main.c
303 +++ b/drivers/net/wireless/b43/main.c
304 @@ -1216,10 +1216,10 @@ void b43_wireless_core_phy_pll_reset(str
305 case B43_BUS_BCMA:
306 bcma_cc = &dev->dev->bdev->bus->drv_cc;
307
308 - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
309 - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
310 - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
311 - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
312 + bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
313 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
314 + bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
315 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
316 break;
317 #endif
318 #ifdef CONFIG_B43_SSB
319 --- a/include/linux/bcma/bcma.h
320 +++ b/include/linux/bcma/bcma.h
321 @@ -151,6 +151,8 @@ struct bcma_host_ops {
322 #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
323 #define BCMA_CORE_USB30_DEV 0x83D
324 #define BCMA_CORE_ARM_CR4 0x83E
325 +#define BCMA_CORE_GCI 0x840
326 +#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
327 #define BCMA_CORE_ARM_CA7 0x847
328 #define BCMA_CORE_SYS_MEM 0x849
329 #define BCMA_CORE_DEFAULT 0xFFF
330 @@ -199,6 +201,7 @@ struct bcma_host_ops {
331 #define BCMA_PKG_ID_BCM4707 1
332 #define BCMA_PKG_ID_BCM4708 2
333 #define BCMA_PKG_ID_BCM4709 0
334 +#define BCMA_CHIP_ID_BCM47094 53030
335 #define BCMA_CHIP_ID_BCM53018 53018
336
337 /* Board types (on PCI usually equals to the subsystem dev id) */
338 --- a/include/linux/bcma/bcma_driver_chipcommon.h
339 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
340 @@ -217,6 +217,11 @@
341 #define BCMA_CC_CLKDIV_JTAG_SHIFT 8
342 #define BCMA_CC_CLKDIV_UART 0x000000FF
343 #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
344 +#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
345 +#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
346 +#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
347 +#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
348 +#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
349 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
350 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
351 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
352 @@ -351,12 +356,12 @@
353 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
354 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
355 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
356 -#define BCMA_CC_CHIPCTL_ADDR 0x0650
357 -#define BCMA_CC_CHIPCTL_DATA 0x0654
358 -#define BCMA_CC_REGCTL_ADDR 0x0658
359 -#define BCMA_CC_REGCTL_DATA 0x065C
360 -#define BCMA_CC_PLLCTL_ADDR 0x0660
361 -#define BCMA_CC_PLLCTL_DATA 0x0664
362 +#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
363 +#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
364 +#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
365 +#define BCMA_CC_PMU_REGCTL_DATA 0x065C
366 +#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
367 +#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
368 #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
369 #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
370 #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
371 @@ -566,6 +571,7 @@
372 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
373 */
374 struct bcma_chipcommon_pmu {
375 + struct bcma_device *core; /* Can be separated core or just ChipCommon one */
376 u8 rev; /* PMU revision */
377 u32 crystalfreq; /* The active crystal frequency (in kHz) */
378 };
379 @@ -662,6 +668,19 @@ struct bcma_drv_cc_b {
380 #define bcma_cc_maskset32(cc, offset, mask, set) \
381 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
382
383 +/* PMU registers access */
384 +#define bcma_pmu_read32(cc, offset) \
385 + bcma_read32((cc)->pmu.core, offset)
386 +#define bcma_pmu_write32(cc, offset, val) \
387 + bcma_write32((cc)->pmu.core, offset, val)
388 +
389 +#define bcma_pmu_mask32(cc, offset, mask) \
390 + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
391 +#define bcma_pmu_set32(cc, offset, set) \
392 + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
393 +#define bcma_pmu_maskset32(cc, offset, mask, set) \
394 + bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
395 +
396 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
397
398 extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
399 --- a/drivers/bcma/bcma_private.h
400 +++ b/drivers/bcma/bcma_private.h
401 @@ -48,7 +48,6 @@ void bcma_core_chipcommon_early_init(str
402 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
403 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
404 #ifdef CONFIG_BCMA_DRIVER_MIPS
405 -void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
406 extern struct platform_device bcma_pflash_dev;
407 #endif /* CONFIG_BCMA_DRIVER_MIPS */
408
409 --- a/drivers/bcma/driver_gpio.c
410 +++ b/drivers/bcma/driver_gpio.c
411 @@ -197,6 +197,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
412 case BCMA_CHIP_ID_BCM4707:
413 case BCMA_CHIP_ID_BCM5357:
414 case BCMA_CHIP_ID_BCM53572:
415 + case BCMA_CHIP_ID_BCM47094:
416 chip->ngpio = 32;
417 break;
418 default:
419 --- a/drivers/bcma/driver_mips.c
420 +++ b/drivers/bcma/driver_mips.c
421 @@ -337,12 +337,9 @@ static void bcma_core_mips_flash_detect(
422
423 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
424 {
425 - struct bcma_bus *bus = mcore->core->bus;
426 -
427 if (mcore->early_setup_done)
428 return;
429
430 - bcma_chipco_serial_init(&bus->drv_cc);
431 bcma_core_mips_flash_detect(mcore);
432
433 mcore->early_setup_done = true;
434 --- a/drivers/bcma/host_pci.c
435 +++ b/drivers/bcma/host_pci.c
436 @@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p
437 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
438 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
439 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
440 - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
441 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
442 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
443 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
444 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
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