[ifxmips] Danube: Fix irq ack
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files-2.6.33 / arch / mips / ifxmips / danube / irq.c
1 #include <linux/init.h>
2 #include <linux/sched.h>
3 #include <linux/slab.h>
4 #include <linux/interrupt.h>
5 #include <linux/kernel_stat.h>
6 #include <linux/module.h>
7
8 #include <asm/bootinfo.h>
9 #include <asm/irq.h>
10 #include <asm/irq_cpu.h>
11
12 #include <ifxmips.h>
13 #include <ifxmips_irq.h>
14
15 void
16 ifxmips_disable_irq(unsigned int irq_nr)
17 {
18 int i;
19 u32 *ier = IFXMIPS_ICU_IM0_IER;
20
21 irq_nr -= INT_NUM_IRQ0;
22 for (i = 0; i <= 4; i++)
23 {
24 if (irq_nr < INT_NUM_IM_OFFSET)
25 {
26 ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
27 return;
28 }
29 ier += IFXMIPS_ICU_OFFSET;
30 irq_nr -= INT_NUM_IM_OFFSET;
31 }
32 }
33 EXPORT_SYMBOL(ifxmips_disable_irq);
34
35 void
36 ifxmips_mask_and_ack_irq(unsigned int irq_nr)
37 {
38 int i;
39 u32 *ier = IFXMIPS_ICU_IM0_IER;
40 u32 *isr = IFXMIPS_ICU_IM0_ISR;
41
42 irq_nr -= INT_NUM_IRQ0;
43 for (i = 0; i <= 4; i++)
44 {
45 if (irq_nr < INT_NUM_IM_OFFSET)
46 {
47 ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
48 ifxmips_w32((1 << irq_nr), isr);
49 return;
50 }
51 ier += IFXMIPS_ICU_OFFSET;
52 isr += IFXMIPS_ICU_OFFSET;
53 irq_nr -= INT_NUM_IM_OFFSET;
54 }
55 }
56 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
57
58 static void
59 ifxmips_ack_irq(unsigned int irq_nr)
60 {
61 int i;
62 u32 *isr = IFXMIPS_ICU_IM0_ISR;
63
64 irq_nr -= INT_NUM_IRQ0;
65 for (i = 0; i <= 4; i++)
66 {
67 if (irq_nr < INT_NUM_IM_OFFSET)
68 {
69 ifxmips_w32((1 << irq_nr), isr);
70 return;
71 }
72 isr += IFXMIPS_ICU_OFFSET;
73 irq_nr -= INT_NUM_IM_OFFSET;
74 }
75 }
76
77
78 void
79 ifxmips_enable_irq(unsigned int irq_nr)
80 {
81 int i;
82 u32 *ier = IFXMIPS_ICU_IM0_IER;
83
84 irq_nr -= INT_NUM_IRQ0;
85 for (i = 0; i <= 4; i++)
86 {
87 if (irq_nr < INT_NUM_IM_OFFSET)
88 {
89 ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
90 return;
91 }
92 ier += IFXMIPS_ICU_OFFSET;
93 irq_nr -= INT_NUM_IM_OFFSET;
94 }
95 }
96 EXPORT_SYMBOL(ifxmips_enable_irq);
97
98 static unsigned int
99 ifxmips_startup_irq(unsigned int irq)
100 {
101 ifxmips_enable_irq(irq);
102 return 0;
103 }
104
105 static void
106 ifxmips_end_irq(unsigned int irq)
107 {
108 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
109 ifxmips_enable_irq(irq);
110 }
111
112 static struct irq_chip
113 ifxmips_irq_type = {
114 "ifxmips",
115 .startup = ifxmips_startup_irq,
116 .enable = ifxmips_enable_irq,
117 .disable = ifxmips_disable_irq,
118 .unmask = ifxmips_enable_irq,
119 .ack = ifxmips_ack_irq,
120 .mask = ifxmips_disable_irq,
121 .mask_ack = ifxmips_mask_and_ack_irq,
122 .end = ifxmips_end_irq,
123 };
124
125 /* silicon bug causes only the msb set to 1 to be valid. all
126 other bits might be bogus */
127 static inline int
128 ls1bit32(unsigned long x)
129 {
130 __asm__ (
131 ".set push \n"
132 ".set mips32 \n"
133 "clz %0, %1 \n"
134 ".set pop \n"
135 : "=r" (x)
136 : "r" (x));
137 return 31 - x;
138 }
139
140 static void
141 ifxmips_hw_irqdispatch(int module)
142 {
143 u32 irq;
144
145 irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
146 if (irq == 0)
147 return;
148
149 /* we need to do this due to a silicon bug */
150 irq = ls1bit32(irq);
151 do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
152
153 if ((irq == 22) && (module == 0))
154 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
155 IFXMIPS_EBU_PCC_ISTAT);
156 }
157
158 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
159 #define DEFINE_HWx_IRQDISPATCH(x) \
160 static void ifxmips_hw ## x ## _irqdispatch(void)\
161 {\
162 ifxmips_hw_irqdispatch(x); \
163 }
164 static void ifxmips_hw5_irqdispatch(void)
165 {
166 do_IRQ(MIPS_CPU_TIMER_IRQ);
167 }
168 DEFINE_HWx_IRQDISPATCH(0)
169 DEFINE_HWx_IRQDISPATCH(1)
170 DEFINE_HWx_IRQDISPATCH(2)
171 DEFINE_HWx_IRQDISPATCH(3)
172 DEFINE_HWx_IRQDISPATCH(4)
173 /*DEFINE_HWx_IRQDISPATCH(5)*/
174 #endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
175
176 asmlinkage void
177 plat_irq_dispatch(void)
178 {
179 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
180 unsigned int i;
181
182 if (pending & CAUSEF_IP7)
183 {
184 do_IRQ(MIPS_CPU_TIMER_IRQ);
185 goto out;
186 } else {
187 for (i = 0; i < 5; i++)
188 {
189 if (pending & (CAUSEF_IP2 << i))
190 {
191 ifxmips_hw_irqdispatch(i);
192 goto out;
193 }
194 }
195 }
196 printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
197
198 out:
199 return;
200 }
201
202 static struct irqaction
203 cascade = {
204 .handler = no_action,
205 .flags = IRQF_DISABLED,
206 .name = "cascade",
207 };
208
209 void __init
210 arch_init_irq(void)
211 {
212 int i;
213
214 for (i = 0; i < 5; i++)
215 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
216
217 mips_cpu_irq_init();
218
219 for (i = 2; i <= 6; i++)
220 setup_irq(i, &cascade);
221
222 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
223 if (cpu_has_vint) {
224 printk(KERN_INFO "Setting up vectored interrupts\n");
225 set_vi_handler(2, ifxmips_hw0_irqdispatch);
226 set_vi_handler(3, ifxmips_hw1_irqdispatch);
227 set_vi_handler(4, ifxmips_hw2_irqdispatch);
228 set_vi_handler(5, ifxmips_hw3_irqdispatch);
229 set_vi_handler(6, ifxmips_hw4_irqdispatch);
230 set_vi_handler(7, ifxmips_hw5_irqdispatch);
231 }
232 #endif
233
234 for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
235 set_irq_chip_and_handler(i, &ifxmips_irq_type,
236 handle_level_irq);
237
238 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
239 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
240 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
241 #else
242 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
243 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
244 #endif
245 }
246
247 void __cpuinit
248 arch_fixup_c0_irqs(void)
249 {
250 /* FIXME: check for CPUID and only do fix for specific chips/versions */
251 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
252 cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
253 }