target/linux/ifxmips/files/arch/mips/ifxmips/cgu.c

   1 /*
   2  *   arch/mips/ifxmips/cgu.c
   3  *
   4  *   This program is free software; you can redistribute it and/or modify
   5  *   it under the terms of the GNU General Public License as published by
   6  *   the Free Software Foundation; either version 2 of the License, or
   7  *   (at your option) any later version.
   8  *
   9  *   This program is distributed in the hope that it will be useful,
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *   GNU General Public License for more details.
  13  *
  14  *   You should have received a copy of the GNU General Public License
  15  *   along with this program; if not, write to the Free Software
  16  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  17  *
  18  *   Copyright (C) 2007 Xu Liang, infineon
  19  *
  20  *   Rewrite of Infineon IFXMips code
  21  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  22  *
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/version.h>
  28 #include <linux/types.h>
  29 #include <linux/fs.h>
  30 #include <linux/miscdevice.h>
  31 #include <linux/init.h>
  32 #include <asm/uaccess.h>
  33 #include <asm/unistd.h>
  34 #include <asm/irq.h>
  35 #include <asm/div64.h>
  36 #include <linux/errno.h>
  37 #include <asm/ifxmips/ifxmips.h>
  38
  39 #define FIX_FOR_36M_CRYSTAL             1
  40 #define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
  41 #define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
  42
  43 #define BASIS_INPUT_CRYSTAL_USB         12000000
  44
  45 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  46 #define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  47
  48 #define CGU_PLL0_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
  49 #define CGU_PLL0_BYPASS                 (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
  50 #define CGU_PLL0_SRC                    (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
  51 #define CGU_PLL0_CFG_DSMSEL             (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
  52 #define CGU_PLL0_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
  53 #define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
  54 #define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
  55 #define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
  56 #define CGU_PLL1_SRC                    (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
  57 #define CGU_PLL1_BYPASS                 (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
  58 #define CGU_PLL1_CFG_DSMSEL             (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
  59 #define CGU_PLL1_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
  60 #define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
  61 #define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
  62 #define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
  63 #define CGU_PLL2_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
  64 #define CGU_PLL2_BYPASS                 (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
  65 #define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
  66 #define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
  67 #define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
  68 #define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
  69 #define CGU_SYS_PPESEL                  GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
  70 #define CGU_SYS_FPI_SEL                 (*IFXMIPS_CGU_SYS & (1 << 6))
  71 #define CGU_SYS_CPU1SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
  72 #define CGU_SYS_CPU0SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
  73 #define CGU_SYS_DDR_SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
  74 #define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
  75 #define CGU_IF_CLK_USBSEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
  76 #define CGU_IF_CLK_MIISEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
  77
  78 static u32 cgu_get_pll0_fdiv(void);
  79
  80 static inline u32 get_input_clock(int pll)
  81 {
  82         switch(pll)
  83         {
  84         case 0:
  85                 if(CGU_PLL0_SRC)
  86                         return BASIS_INPUT_CRYSTAL_USB;
  87                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  88                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  89                 else
  90                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  91         case 1:
  92                 if(CGU_PLL1_SRC)
  93                         return BASIS_INPUT_CRYSTAL_USB;
  94                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  95                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  96                 else
  97                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  98         case 2:
  99                 switch(CGU_PLL2_SRC)
 100                 {
 101                 case 0:
 102                         return cgu_get_pll0_fdiv();
 103                 case 1:
 104                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
 105                 case 2:
 106                         return BASIS_INPUT_CRYSTAL_USB;
 107                 }
 108         default:
 109                 return 0;
 110         }
 111 }
 112
 113 static inline u32
 114 cal_dsm(int pll, u32 num, u32 den)
 115 {
 116         u64 res, clock = get_input_clock(pll);
 117
 118         res = num * clock;
 119         do_div(res, den);
 120         return res;
 121 }
 122
 123 static inline u32
 124 mash_dsm(int pll, u32 M, u32 N, u32 K)
 125 {
 126         u32 num = ((N + 1) << 10) + K;
 127         u32 den = (M + 1) << 10;
 128
 129         return cal_dsm(pll, num, den);
 130 }
 131
 132 static inline u32 ssff_dsm_1(int pll, u32 M, u32 N, u32 K)
 133 {
 134         u32 num = ((N + 1) << 11) + K + 512;
 135         u32 den = (M + 1) << 11;
 136
 137         return cal_dsm(pll, num, den);
 138 }
 139
 140 static inline u32 ssff_dsm_2(int pll, u32 M, u32 N, u32 K)
 141 {
 142         u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 143         u32 den = (M + 1) << 12;
 144
 145         return cal_dsm(pll, num, den);
 146 }
 147
 148 static inline u32 dsm(int pll, u32 M, u32 N, u32 K, u32 dsmsel, u32 phase_div_en)
 149 {
 150         if ( !dsmsel )
 151                 return mash_dsm(pll, M, N, K);
 152         else if ( !phase_div_en )
 153                 return mash_dsm(pll, M, N, K);
 154         else
 155                 return ssff_dsm_2(pll, M, N, K);
 156 }
 157
 158 static inline u32 cgu_get_pll0_fosc(void)
 159 {
 160         if(CGU_PLL0_BYPASS)
 161                 return get_input_clock(0);
 162         else
 163                 return !CGU_PLL0_CFG_FRAC_EN
 164                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE)
 165                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 166 }
 167
 168 static inline u32 cgu_get_pll0_fps(int phase)
 169 {
 170         register u32 fps = cgu_get_pll0_fosc();
 171
 172         switch ( phase )
 173         {
 174         case 1:
 175                 /*  1.25    */
 176                 fps = ((fps << 2) + 2) / 5;
 177                 break;
 178         case 2:
 179                 /*  1.5     */
 180                 fps = ((fps << 1) + 1) / 3;
 181                 break;
 182         }
 183         return fps;
 184 }
 185
 186 static u32 cgu_get_pll0_fdiv(void)
 187 {
 188         register u32 div = CGU_PLL2_CFG_INPUT_DIV + 1;
 189
 190         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 191 }
 192
 193 static inline u32 cgu_get_pll1_fosc(void)
 194 {
 195         if(CGU_PLL1_BYPASS)
 196                 return get_input_clock(1);
 197         else
 198                 return !CGU_PLL1_CFG_FRAC_EN
 199                         ? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
 200                         : dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
 201 }
 202
 203 static inline u32 cgu_get_pll1_fps(void)
 204 {
 205         register u32 fps = cgu_get_pll1_fosc();
 206
 207         return ((fps << 1) + 1) / 3;
 208 }
 209
 210 static inline u32 cgu_get_pll1_fdiv(void)
 211 {
 212         return cgu_get_pll1_fosc();
 213 }
 214
 215 static inline u32 cgu_get_pll2_fosc(void)
 216 {
 217         u64 res, clock = get_input_clock(2);
 218
 219         if ( CGU_PLL2_BYPASS )
 220                 return get_input_clock(2);
 221
 222         res = (CGU_PLL2_CFG_PLLN + 1) * clock;
 223         do_div(res, CGU_PLL2_CFG_PLLM + 1);
 224
 225         return res;
 226 }
 227
 228 static inline u32 cgu_get_pll2_fps(int phase)
 229 {
 230         register u32 fps = cgu_get_pll2_fosc();
 231
 232         switch ( phase )
 233         {
 234         case 1:
 235                 /*  1.125   */
 236                 fps = ((fps << 2) + 2) / 5; break;
 237         case 2:
 238                 /*  1.25    */
 239                 fps = ((fps << 3) + 4) / 9;
 240         }
 241
 242         return fps;
 243 }
 244
 245 static inline u32 cgu_get_pll2_fdiv(void)
 246 {
 247         register u32 div = CGU_IF_CLK_PCI_CLK + 1;
 248         return (cgu_get_pll2_fosc() + (div >> 1)) / div;
 249 }
 250
 251 u32 cgu_get_mips_clock(int cpu)
 252 {
 253         register u32 ret = cgu_get_pll0_fosc();
 254         register u32 cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
 255
 256         if ( cpusel == 0 )
 257                 return ret;
 258         else if ( cpusel == 2 )
 259                 ret <<= 1;
 260
 261         switch ( CGU_SYS_DDR_SEL )
 262         {
 263         default:
 264         case 0:
 265                 return (ret + 1) / 2;
 266         case 1:
 267                 return (ret * 2 + 2) / 5;
 268         case 2:
 269                 return (ret + 1) / 3;
 270         case 3:
 271                 return (ret + 2) / 4;
 272         }
 273 }
 274
 275 u32 cgu_get_cpu_clock(void)
 276 {
 277         return cgu_get_mips_clock(0);
 278 }
 279
 280 u32 cgu_get_io_region_clock(void)
 281 {
 282         register u32 ret = cgu_get_pll0_fosc();
 283
 284         switch ( CGU_SYS_DDR_SEL )
 285         {
 286         default:
 287         case 0:
 288                 return (ret + 1) / 2;
 289         case 1:
 290                 return (ret * 2 + 2) / 5;
 291         case 2:
 292                 return (ret + 1) / 3;
 293         case 3:
 294                 return (ret + 2) / 4;
 295         }
 296 }
 297
 298 u32 cgu_get_fpi_bus_clock(int fpi)
 299 {
 300         register u32 ret = cgu_get_io_region_clock();
 301
 302         if((fpi == 2) && (CGU_SYS_FPI_SEL))
 303                 ret >>= 1;
 304
 305         return ret;
 306 }
 307
 308 u32 cgu_get_pp32_clock(void)
 309 {
 310         switch ( CGU_SYS_PPESEL )
 311         {
 312         default:
 313         case 0:
 314                 return cgu_get_pll2_fps(1);
 315         case 1:
 316                 return cgu_get_pll2_fps(2);
 317         case 2:
 318                 return (cgu_get_pll2_fps(1) + 1) >> 1;
 319         case 3:
 320                 return (cgu_get_pll2_fps(2) + 1) >> 1;
 321         }
 322 }
 323
 324 u32 cgu_get_ethernet_clock(int mii)
 325 {
 326         switch ( CGU_IF_CLK_MIISEL )
 327         {
 328         case 0:
 329                 return (cgu_get_pll2_fosc() + 3) / 12;
 330         case 1:
 331                 return (cgu_get_pll2_fosc() + 3) / 6;
 332         case 2:
 333                 return 50000000;
 334         case 3:
 335                 return 25000000;
 336         }
 337         return 0;
 338 }
 339
 340 u32 cgu_get_usb_clock(void)
 341 {
 342         switch ( CGU_IF_CLK_USBSEL )
 343         {
 344         case 0:
 345                 return (cgu_get_pll2_fosc() + 12) / 25;
 346         case 1:
 347                 return 12000000;
 348         case 2:
 349                 return 12000000 / 4;
 350         case 3:
 351                 return 12000000;
 352         }
 353         return 0;
 354 }
 355
 356 u32 cgu_get_clockout(int clkout)
 357 {
 358         u32 fosc1 = cgu_get_pll1_fosc();
 359         u32 fosc2 = cgu_get_pll2_fosc();
 360
 361         if ( clkout > 3 || clkout < 0 )
 362                 return 0;
 363
 364         switch ( ((u32)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2) )
 365         {
 366         case 0: /*  32.768KHz   */
 367         case 15:
 368                 return (fosc1 + 6000) / 12000;
 369         case 1: /*  1.536MHz    */
 370                 return (fosc1 + 128) / 256;
 371         case 2: /*  2.5MHz      */
 372                 return (fosc2 + 60) / 120;
 373         case 3: /*  12MHz       */
 374         case 5:
 375         case 12:
 376                 return (fosc2 + 12) / 25;
 377         case 4: /*  40MHz       */
 378                 return (cgu_get_pll2_fps(2) + 3) / 6;
 379         case 6: /*  24MHz       */
 380                 return (cgu_get_pll2_fps(2) + 5) / 10;
 381         case 7: /*  48MHz       */
 382                 return (cgu_get_pll2_fps(2) + 2) / 5;
 383         case 8: /*  25MHz       */
 384         case 14:
 385                 return (fosc2 + 6) / 12;
 386         case 9: /*  50MHz       */
 387         case 13:
 388                 return (fosc2 + 3) / 6;
 389         case 10:/*  30MHz       */
 390                 return (fosc2 + 5) / 10;
 391         case 11:/*  60MHz       */
 392                 return (fosc2 + 2) / 5;
 393         }
 394
 395         return 0;
 396 }