target/linux/ifxmips/files/arch/mips/ifxmips/cgu.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2007 Xu Liang, infineon
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/version.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/init.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/unistd.h>
  29 #include <asm/irq.h>
  30 #include <asm/div64.h>
  31 #include <linux/errno.h>
  32 #include <asm/ifxmips/ifxmips.h>
  33
  34 #define FIX_FOR_36M_CRYSTAL             1
  35 #define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
  36 #define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
  37
  38 #define BASIS_INPUT_CRYSTAL_USB         12000000
  39
  40 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  41 #define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  42
  43 #define CGU_PLL0_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
  44 #define CGU_PLL0_BYPASS                 (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
  45 #define CGU_PLL0_SRC                    (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
  46 #define CGU_PLL0_CFG_DSMSEL             (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
  47 #define CGU_PLL0_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
  48 #define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
  49 #define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
  50 #define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
  51 #define CGU_PLL1_SRC                    (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
  52 #define CGU_PLL1_BYPASS                 (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
  53 #define CGU_PLL1_CFG_DSMSEL             (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
  54 #define CGU_PLL1_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
  55 #define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
  56 #define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
  57 #define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
  58 #define CGU_PLL2_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
  59 #define CGU_PLL2_BYPASS                 (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
  60 #define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
  61 #define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
  62 #define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
  63 #define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
  64 #define CGU_SYS_PPESEL                  GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
  65 #define CGU_SYS_FPI_SEL                 (*IFXMIPS_CGU_SYS & (1 << 6))
  66 #define CGU_SYS_CPU1SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
  67 #define CGU_SYS_CPU0SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
  68 #define CGU_SYS_DDR_SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
  69 #define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
  70 #define CGU_IF_CLK_USBSEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
  71 #define CGU_IF_CLK_MIISEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
  72
  73 static unsigned int cgu_get_pll0_fdiv(void);
  74
  75 static inline unsigned int
  76 get_input_clock(int pll)
  77 {
  78         switch(pll)
  79         {
  80         case 0:
  81                 if(CGU_PLL0_SRC)
  82                         return BASIS_INPUT_CRYSTAL_USB;
  83                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  84                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  85                 else
  86                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  87         case 1:
  88                 if(CGU_PLL1_SRC)
  89                         return BASIS_INPUT_CRYSTAL_USB;
  90                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  91                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  92                 else
  93                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  94         case 2:
  95                 switch(CGU_PLL2_SRC)
  96                 {
  97                 case 0:
  98                         return cgu_get_pll0_fdiv();
  99                 case 1:
 100                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
 101                 case 2:
 102                         return BASIS_INPUT_CRYSTAL_USB;
 103                 }
 104         default:
 105                 return 0;
 106         }
 107 }
 108
 109 static inline unsigned int
 110 cal_dsm(int pll, unsigned int num, unsigned int den)
 111 {
 112         u64 res, clock = get_input_clock(pll);
 113
 114         res = num * clock;
 115         do_div(res, den);
 116         return res;
 117 }
 118
 119 static inline unsigned int
 120 mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
 121 {
 122         unsigned int num = ((N + 1) << 10) + K;
 123         unsigned int den = (M + 1) << 10;
 124
 125         return cal_dsm(pll, num, den);
 126 }
 127
 128 static inline unsigned int
 129 ssff_dsm_1(int pll, unsigned int M,     unsigned int N, unsigned int K)
 130 {
 131         unsigned int num = ((N + 1) << 11) + K + 512;
 132         unsigned int den = (M + 1) << 11;
 133
 134         return cal_dsm(pll, num, den);
 135 }
 136
 137 static inline unsigned int
 138 ssff_dsm_2(int pll, unsigned int M,     unsigned int N, unsigned int K)
 139 {
 140         unsigned int num = K >= 512 ?
 141                 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 142         unsigned int den = (M + 1) << 12;
 143
 144         return cal_dsm(pll, num, den);
 145 }
 146
 147 static inline unsigned int
 148 dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
 149         unsigned int dsmsel, unsigned int phase_div_en)
 150 {
 151         if(!dsmsel)
 152                 return mash_dsm(pll, M, N, K);
 153         else if(!phase_div_en)
 154                 return mash_dsm(pll, M, N, K);
 155         else
 156                 return ssff_dsm_2(pll, M, N, K);
 157 }
 158
 159 static inline unsigned int
 160 cgu_get_pll0_fosc(void)
 161 {
 162         if(CGU_PLL0_BYPASS)
 163                 return get_input_clock(0);
 164         else
 165                 return !CGU_PLL0_CFG_FRAC_EN
 166                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
 167                                 CGU_PLL0_PHASE_DIVIDER_ENABLE)
 168                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
 169                                 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 170 }
 171
 172 static inline unsigned int
 173 cgu_get_pll0_fps(int phase)
 174 {
 175         register unsigned int fps = cgu_get_pll0_fosc();
 176
 177         switch(phase)
 178         {
 179         case 1:
 180                 /*  1.25    */
 181                 fps = ((fps << 2) + 2) / 5;
 182                 break;
 183         case 2:
 184                 /*  1.5     */
 185                 fps = ((fps << 1) + 1) / 3;
 186                 break;
 187         }
 188         return fps;
 189 }
 190
 191 static unsigned int
 192 cgu_get_pll0_fdiv(void)
 193 {
 194         register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
 195
 196         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 197 }
 198
 199 static inline unsigned int
 200 cgu_get_pll1_fosc(void)
 201 {
 202         if(CGU_PLL1_BYPASS)
 203                 return get_input_clock(1);
 204         else
 205                 return !CGU_PLL1_CFG_FRAC_EN
 206                         ? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
 207                         : dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
 208 }
 209
 210 static inline unsigned int
 211 cgu_get_pll1_fps(void)
 212 {
 213         register unsigned int fps = cgu_get_pll1_fosc();
 214
 215         return ((fps << 1) + 1) / 3;
 216 }
 217
 218 static inline unsigned int
 219 cgu_get_pll1_fdiv(void)
 220 {
 221         return cgu_get_pll1_fosc();
 222 }
 223
 224 static inline unsigned int
 225 cgu_get_pll2_fosc(void)
 226 {
 227         u64 res, clock = get_input_clock(2);
 228
 229         if ( CGU_PLL2_BYPASS )
 230                 return get_input_clock(2);
 231
 232         res = (CGU_PLL2_CFG_PLLN + 1) * clock;
 233         do_div(res, CGU_PLL2_CFG_PLLM + 1);
 234
 235         return res;
 236 }
 237
 238 static inline unsigned int
 239 cgu_get_pll2_fps(int phase)
 240 {
 241         register unsigned int fps = cgu_get_pll2_fosc();
 242
 243         switch ( phase )
 244         {
 245         case 1:
 246                 /*  1.125   */
 247                 fps = ((fps << 2) + 2) / 5; break;
 248         case 2:
 249                 /*  1.25    */
 250                 fps = ((fps << 3) + 4) / 9;
 251         }
 252
 253         return fps;
 254 }
 255
 256 static inline unsigned int
 257 cgu_get_pll2_fdiv(void)
 258 {
 259         register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
 260         return (cgu_get_pll2_fosc() + (div >> 1)) / div;
 261 }
 262
 263 unsigned int
 264 cgu_get_mips_clock(int cpu)
 265 {
 266         register unsigned int ret = cgu_get_pll0_fosc();
 267         register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
 268
 269         if(cpusel == 0)
 270                 return ret;
 271         else if(cpusel == 2)
 272                 ret <<= 1;
 273
 274         switch(CGU_SYS_DDR_SEL)
 275         {
 276         default:
 277         case 0:
 278                 return (ret + 1) / 2;
 279         case 1:
 280                 return (ret * 2 + 2) / 5;
 281         case 2:
 282                 return (ret + 1) / 3;
 283         case 3:
 284                 return (ret + 2) / 4;
 285         }
 286 }
 287
 288 unsigned int
 289 cgu_get_cpu_clock(void)
 290 {
 291         return cgu_get_mips_clock(0);
 292 }
 293
 294 unsigned int
 295 cgu_get_io_region_clock(void)
 296 {
 297         register unsigned int ret = cgu_get_pll0_fosc();
 298
 299         switch(CGU_SYS_DDR_SEL)
 300         {
 301         default:
 302         case 0:
 303                 return (ret + 1) / 2;
 304         case 1:
 305                 return (ret * 2 + 2) / 5;
 306         case 2:
 307                 return (ret + 1) / 3;
 308         case 3:
 309                 return (ret + 2) / 4;
 310         }
 311 }
 312
 313 unsigned int
 314 cgu_get_fpi_bus_clock(int fpi)
 315 {
 316         register unsigned int ret = cgu_get_io_region_clock();
 317
 318         if((fpi == 2) && (CGU_SYS_FPI_SEL))
 319                 ret >>= 1;
 320
 321         return ret;
 322 }
 323
 324 unsigned int
 325 cgu_get_pp32_clock(void)
 326 {
 327         switch(CGU_SYS_PPESEL)
 328         {
 329         default:
 330         case 0:
 331                 return cgu_get_pll2_fps(1);
 332         case 1:
 333                 return cgu_get_pll2_fps(2);
 334         case 2:
 335                 return (cgu_get_pll2_fps(1) + 1) >> 1;
 336         case 3:
 337                 return (cgu_get_pll2_fps(2) + 1) >> 1;
 338         }
 339 }
 340
 341 unsigned int
 342 cgu_get_ethernet_clock(int mii)
 343 {
 344         switch(CGU_IF_CLK_MIISEL)
 345         {
 346         case 0:
 347                 return (cgu_get_pll2_fosc() + 3) / 12;
 348         case 1:
 349                 return (cgu_get_pll2_fosc() + 3) / 6;
 350         case 2:
 351                 return 50000000;
 352         case 3:
 353                 return 25000000;
 354         }
 355         return 0;
 356 }
 357
 358 unsigned int
 359 cgu_get_usb_clock(void)
 360 {
 361         switch(CGU_IF_CLK_USBSEL)
 362         {
 363         case 0:
 364                 return (cgu_get_pll2_fosc() + 12) / 25;
 365         case 1:
 366                 return 12000000;
 367         case 2:
 368                 return 12000000 / 4;
 369         case 3:
 370                 return 12000000;
 371         }
 372         return 0;
 373 }
 374
 375 unsigned int
 376 cgu_get_clockout(int clkout)
 377 {
 378         unsigned int fosc1 = cgu_get_pll1_fosc();
 379         unsigned int fosc2 = cgu_get_pll2_fosc();
 380
 381         if(clkout > 3 || clkout < 0)
 382                 return 0;
 383
 384         switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
 385         {
 386         case 0: /*  32.768KHz   */
 387         case 15:
 388                 return (fosc1 + 6000) / 12000;
 389         case 1: /*  1.536MHz    */
 390                 return (fosc1 + 128) / 256;
 391         case 2: /*  2.5MHz      */
 392                 return (fosc2 + 60) / 120;
 393         case 3: /*  12MHz       */
 394         case 5:
 395         case 12:
 396                 return (fosc2 + 12) / 25;
 397         case 4: /*  40MHz       */
 398                 return (cgu_get_pll2_fps(2) + 3) / 6;
 399         case 6: /*  24MHz       */
 400                 return (cgu_get_pll2_fps(2) + 5) / 10;
 401         case 7: /*  48MHz       */
 402                 return (cgu_get_pll2_fps(2) + 2) / 5;
 403         case 8: /*  25MHz       */
 404         case 14:
 405                 return (fosc2 + 6) / 12;
 406         case 9: /*  50MHz       */
 407         case 13:
 408                 return (fosc2 + 3) / 6;
 409         case 10:/*  30MHz       */
 410                 return (fosc2 + 5) / 10;
 411         case 11:/*  60MHz       */
 412                 return (fosc2 + 2) / 5;
 413         }
 414         return 0;
 415 }
 416
 417 void cgu_setup_pci_clk(int external_clock)
 418 {
 419         //set clock to 33Mhz
 420         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
 421         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
 422         // internal or external clock
 423         if(external_clock)
 424         {
 425                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
 426                 ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
 427         } else {
 428                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
 429                 ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 430         }
 431 }