495f2582fab402eb1b4b5db3984914cd0b3b149f
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / drivers / char / danube_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 // ### TO DO: general issues:
22 // - power management
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fs.h>
37 #include <linux/proc_fs.h>
38 #include <linux/fcntl.h>
39 #include <linux/ptrace.h>
40 #include <linux/mm.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/delay.h>
44 #include <linux/spinlock.h>
45 #include <linux/slab.h>
46
47 #include <asm/system.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/uaccess.h>
51 #include <asm/bitops.h>
52
53 #include <linux/types.h>
54 #include <linux/kernel.h>
55 #include <linux/version.h>
56
57 #include <asm/ifxmips/ifxmips.h>
58 #include <asm/ifxmips/ifxmips_irq.h>
59 #include <asm/ifxmips/ifx_ssc_defines.h>
60 #include <asm/ifxmips/ifx_ssc.h>
61
62 #ifdef SSC_FRAME_INT_ENABLE
63 #undef SSC_FRAME_INT_ENABLE
64 #endif
65
66 #define not_yet
67
68 #define SPI_VINETIC
69
70
71
72 /* allow the user to set the major device number */
73 static int maj = 0;
74
75 /*
76 * This is the per-channel data structure containing pointers, flags
77 * and variables for the port. This driver supports a maximum of PORT_CNT.
78 * isp is allocated in ifx_ssc_init() based on the chip version.
79 */
80 static struct ifx_ssc_port *isp;
81
82 /* prototypes for fops */
83 static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
84 static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
85 //static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
86 int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
87 unsigned long);
88 int ifx_ssc_open (struct inode *, struct file *);
89 int ifx_ssc_close (struct inode *, struct file *);
90
91 /* other forward declarations */
92 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
93 static void tx_int (struct ifx_ssc_port *);
94 static int ifx_ssc1_read_proc (char *, char **, off_t, int, int *, void *);
95
96 extern unsigned int ifxmips_get_fpi_hz (void);
97 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
98
99 static struct file_operations ifx_ssc_fops = {
100 .owner = THIS_MODULE,
101 .read = ifx_ssc_read,
102 .write = ifx_ssc_write,
103 .ioctl = ifx_ssc_ioctl,
104 .open = ifx_ssc_open,
105 .release = ifx_ssc_close,
106 };
107
108 static inline unsigned int
109 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
110 {
111 unsigned int rmc;
112
113 rmc = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
114 if (rmc == 0)
115 {
116 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
117 return 0;
118 }
119 return ifxmips_get_fpi_hz () / rmc;
120 }
121
122 #ifndef not_yet
123 #ifdef IFX_SSC_INT_USE_BH
124 /*
125 * This routine is used by the interrupt handler to schedule
126 * processing in the software interrupt portion of the driver
127 * (also known as the "bottom half"). This can be called any
128 * number of times for any channel without harm.
129 */
130 static inline void
131 ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
132 {
133 info->event |= 1 << event; /* remember what kind of event and who */
134 queue_task (&info->tqueue, &tq_cyclades); /* it belongs to */
135 mark_bh (CYCLADES_BH); /* then trigger event */
136 }
137
138 static void
139 do_softint (void *private_)
140 {
141 struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
142
143 if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event))
144 {
145 wake_up_interruptible (&info->open_wait);
146 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
147 }
148
149 if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event))
150 wake_up_interruptible (&info->open_wait);
151
152 if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event))
153 wake_up_interruptible (&info->delta_msr_wait);
154
155 if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event))
156 wake_up_interruptible (&tty->write_wait);
157 #ifdef Z_WAKE
158 if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event))
159 wake_up_interruptible (&info->shutdown_wait);
160 #endif
161 }
162 #endif
163 #endif
164
165 inline static void
166 rx_int (struct ifx_ssc_port *info)
167 {
168 int fifo_fill_lev, bytes_in_buf, i;
169 unsigned long tmp_val;
170 unsigned long *tmp_ptr;
171 unsigned int rx_valid_cnt;
172 /* number of words waiting in the RX FIFO */
173 fifo_fill_lev = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
174 // Note: There are always 32 bits in a fifo-entry except for the last
175 // word of a contigous transfer block and except for not in rx-only
176 // mode and CON.ENBV set. But for this case it should be a convention
177 // in software which helps:
178 // In tx or rx/tx mode all transfers from the buffer to the FIFO are
179 // 32-bit wide, except for the last three bytes, which could be a
180 // combination of 16- and 8-bit access.
181 // => The whole block is received as 32-bit words as a contigous stream,
182 // even if there was a gap in tx which has the fifo run out of data!
183 // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
184
185 /* free space in the RX buffer */
186 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
187 // transfer with 32 bits per entry
188 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
189 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
190 *tmp_ptr = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
191 info->rxbuf_ptr += 4;
192 info->stats.rxBytes += 4;
193 fifo_fill_lev--;
194 bytes_in_buf -= 4;
195 }
196
197 // now do the rest as mentioned in STATE.RXBV
198 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
199 rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
200 if (rx_valid_cnt == 0)
201 break;
202
203 if (rx_valid_cnt > bytes_in_buf)
204 rx_valid_cnt = bytes_in_buf;
205
206 tmp_val = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
207
208 for (i = 0; i < rx_valid_cnt; i++)
209 {
210 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
211 bytes_in_buf--;
212 info->rxbuf_ptr++;
213 }
214 info->stats.rxBytes += rx_valid_cnt;
215 }
216
217 // check if transfer is complete
218 if (info->rxbuf_ptr >= info->rxbuf_end)
219 {
220 disable_irq(info->rxirq);
221 wake_up_interruptible (&info->rwait);
222 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
223 {
224 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
225 WRITE_PERIPHERAL_REGISTER ((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
226 else
227 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
228 }
229 }
230
231 inline static void
232 tx_int (struct ifx_ssc_port *info)
233 {
234
235 int fifo_space, fill, i;
236 fifo_space = ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
237 - ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
238
239 if (fifo_space == 0)
240 return;
241
242 fill = info->txbuf_end - info->txbuf_ptr;
243
244 if (fill > fifo_space * 4)
245 fill = fifo_space * 4;
246
247 for (i = 0; i < fill / 4; i++)
248 {
249 // at first 32 bit access
250 WRITE_PERIPHERAL_REGISTER (*(UINT32 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
251 info->txbuf_ptr += 4;
252 }
253
254 fifo_space -= fill / 4;
255 info->stats.txBytes += fill & ~0x3;
256 fill &= 0x3;
257 if ((fifo_space > 0) & (fill > 1))
258 {
259 // trailing 16 bit access
260 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
261 info->txbuf_ptr += 2;
262 info->stats.txBytes += 2;
263 fifo_space--;
264 fill -= 2;
265 }
266
267 if ((fifo_space > 0) & (fill > 0))
268 {
269 // trailing 8 bit access
270 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
271 info->txbuf_ptr++;
272 info->stats.txBytes++;
273 }
274
275 // check if transmission complete
276 if (info->txbuf_ptr >= info->txbuf_end)
277 {
278 disable_irq(info->txirq);
279 kfree (info->txbuf);
280 info->txbuf = NULL;
281 }
282
283 }
284
285 irqreturn_t
286 ifx_ssc_rx_int (int irq, void *dev_id)
287 {
288 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
289 rx_int (info);
290
291 return IRQ_HANDLED;
292 }
293
294 irqreturn_t
295 ifx_ssc_tx_int (int irq, void *dev_id)
296 {
297 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
298 tx_int (info);
299
300 return IRQ_HANDLED;
301 }
302
303 irqreturn_t
304 ifx_ssc_err_int (int irq, void *dev_id)
305 {
306 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
307 unsigned int state;
308 unsigned int write_back = 0;
309 unsigned long flags;
310
311 local_irq_save (flags);
312 state = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE);
313
314 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
315 info->stats.rxUnErr++;
316 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
317 }
318
319 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
320 info->stats.rxOvErr++;
321 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
322 }
323
324 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
325 info->stats.txOvErr++;
326 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
327 }
328
329 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
330 info->stats.txUnErr++;
331 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
332 }
333
334 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
335 info->stats.modeErr++;
336 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
337 }
338
339 if (write_back)
340 WRITE_PERIPHERAL_REGISTER (write_back, info->mapbase + IFX_SSC_WHBSTATE);
341
342 local_irq_restore (flags);
343
344 return IRQ_HANDLED;
345 }
346
347 static void
348 ifx_ssc_abort (struct ifx_ssc_port *info)
349 {
350 unsigned long flags;
351 bool enabled;
352
353 local_irq_save (flags);
354
355 disable_irq(info->rxirq);
356 disable_irq(info->txirq);
357 disable_irq(info->errirq);
358
359 local_irq_restore (flags);
360
361 // disable SSC (also aborts a receive request!)
362 // ### TO DO: Perhaps it's better to abort after the receiption of a
363 // complete word. The disable cuts the transmission immediatly and
364 // releases the chip selects. This could result in unpredictable
365 // behavior of connected external devices!
366 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
367 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
368
369 // flush fifos
370 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_TXFCON);
371 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_RXFCON);
372
373 // free txbuf
374 if (info->txbuf != NULL)
375 {
376 kfree (info->txbuf);
377 info->txbuf = NULL;
378 }
379
380 // wakeup read process
381 if (info->rxbuf != NULL)
382 wake_up_interruptible (&info->rwait);
383
384 // clear pending int's
385 mask_and_ack_ifxmips_irq(info->rxirq);
386 mask_and_ack_ifxmips_irq(info->txirq);
387 mask_and_ack_ifxmips_irq(info->errirq);
388
389 // clear error flags
390 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
391
392 if (enabled)
393 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
394
395 }
396
397 /*
398 * This routine is called whenever a port is opened. It enforces
399 * exclusive opening of a port and enables interrupts, etc.
400 */
401 int
402 ifx_ssc_open (struct inode *inode, struct file *filp)
403 {
404 struct ifx_ssc_port *info;
405 int line;
406 int from_kernel = 0;
407
408 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
409 from_kernel = 1;
410 line = (int) inode;
411 } else {
412 line = MINOR (filp->f_dentry->d_inode->i_rdev);
413 filp->f_op = &ifx_ssc_fops;
414 }
415
416 /* don't open more minor devices than we can support */
417 if (line < 0 || line >= PORT_CNT)
418 return -ENXIO;
419
420 info = &isp[line];
421
422 /* exclusive open */
423 if (info->port_is_open != 0)
424 return -EBUSY;
425 info->port_is_open++;
426
427 disable_irq(info->rxirq);
428 disable_irq(info->txirq);
429 disable_irq(info->errirq);
430
431 /* Flush and enable TX/RX FIFO */
432 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_TXFCON);
433 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_RXFCON);
434
435 /* logically flush the software FIFOs */
436 info->rxbuf_ptr = 0;
437 info->txbuf_ptr = 0;
438
439 /* clear all error bits */
440 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
441
442 // clear pending interrupts
443 mask_and_ack_ifxmips_irq(info->rxirq);
444 mask_and_ack_ifxmips_irq(info->txirq);
445 mask_and_ack_ifxmips_irq(info->errirq);
446
447 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
448
449 return 0;
450 }
451 EXPORT_SYMBOL(ifx_ssc_open);
452
453 int
454 ifx_ssc_close (struct inode *inode, struct file *filp)
455 {
456 struct ifx_ssc_port *info;
457 int idx;
458
459 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
460 idx = (int) inode;
461 else
462 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
463
464 if (idx < 0 || idx >= PORT_CNT)
465 return -ENXIO;
466
467 info = &isp[idx];
468 if (!info)
469 return -ENXIO;
470
471 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
472
473 ifx_ssc_abort(info);
474
475 info->port_is_open--;
476
477 return 0;
478 }
479 EXPORT_SYMBOL(ifx_ssc_close);
480
481 static ssize_t
482 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
483 {
484 ssize_t ret_val;
485 unsigned long flags;
486
487 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
488 return -EFAULT;
489 local_irq_save (flags);
490 info->rxbuf_ptr = info->rxbuf;
491 info->rxbuf_end = info->rxbuf + len;
492 local_irq_restore (flags);
493 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
494 /* TXRX in poll mode */
495 while (info->rxbuf_ptr < info->rxbuf_end)
496 {
497 if (info->txbuf_ptr < info->txbuf_end)
498 tx_int (info);
499
500 rx_int (info);
501 };
502
503 ret_val = info->rxbuf_ptr - info->rxbuf;
504
505 return ret_val;
506 }
507
508 static ssize_t
509 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
510 {
511 ssize_t ret_val;
512 unsigned long flags;
513 DECLARE_WAITQUEUE (wait, current);
514
515 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
516 return -EFAULT;
517
518 local_irq_save (flags);
519 info->rxbuf_ptr = info->rxbuf;
520 info->rxbuf_end = info->rxbuf + len;
521
522 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
523 {
524 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
525 {
526 local_irq_restore (flags);
527 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
528 return -EFAULT;
529 }
530
531 local_irq_restore(flags);
532 tx_int (info);
533
534 if (info->txbuf_ptr < info->txbuf_end)
535 enable_irq(info->txirq);
536
537 enable_irq(info->rxirq);
538 } else {
539 local_irq_restore(flags);
540 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
541 return -EBUSY;
542 enable_irq(info->rxirq);
543 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
544 WRITE_PERIPHERAL_REGISTER (len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
545 else
546 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
547 }
548
549 __add_wait_queue (&info->rwait, &wait);
550 set_current_state (TASK_INTERRUPTIBLE);
551
552 do {
553 local_irq_save (flags);
554 if (info->rxbuf_ptr >= info->rxbuf_end)
555 break;
556
557 local_irq_restore (flags);
558
559 if (signal_pending (current))
560 {
561 ret_val = -ERESTARTSYS;
562 goto out;
563 }
564 schedule();
565 } while (1);
566
567 ret_val = info->rxbuf_ptr - info->rxbuf;
568 local_irq_restore (flags);
569
570 out:
571 current->state = TASK_RUNNING;
572 __remove_wait_queue (&info->rwait, &wait);
573
574 return (ret_val);
575 }
576
577 static ssize_t
578 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
579 size_t len, int from_kernel)
580 {
581 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
582 return -EFAULT;
583
584 info->txbuf_ptr = info->txbuf;
585 info->txbuf_end = len + info->txbuf;
586 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
587 {
588 tx_int (info);
589 if (info->txbuf_ptr < info->txbuf_end)
590 {
591 enable_irq(info->txirq);
592 }
593 }
594
595 return len;
596 }
597
598 ssize_t
599 ifx_ssc_kread (int port, char *kbuf, size_t len)
600 {
601 struct ifx_ssc_port *info;
602 ssize_t ret_val;
603
604 if (port < 0 || port >= PORT_CNT)
605 return -ENXIO;
606
607 if (len == 0)
608 return 0;
609
610 info = &isp[port];
611
612 if (info->rxbuf != NULL)
613 {
614 printk ("SSC device busy\n");
615 return -EBUSY;
616 }
617
618 info->rxbuf = kbuf;
619 if (info->rxbuf == NULL)
620 {
621 printk ("SSC device error\n");
622 return -EINVAL;
623 }
624
625 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
626 info->rxbuf = NULL;
627
628 disable_irq(info->rxirq);
629
630 return ret_val;
631 }
632 EXPORT_SYMBOL(ifx_ssc_kread);
633
634 ssize_t
635 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
636 {
637 struct ifx_ssc_port *info;
638 ssize_t ret_val;
639
640 if (port < 0 || port >= PORT_CNT)
641 return -ENXIO;
642
643 if (len == 0)
644 return 0;
645
646 info = &isp[port];
647
648 // check if transmission in progress
649 if (info->txbuf != NULL)
650 return -EBUSY;
651
652 info->txbuf = (char *) kbuf;
653
654 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
655
656 if (ret_val < 0)
657 info->txbuf = NULL;
658
659 return ret_val;
660 }
661 EXPORT_SYMBOL(ifx_ssc_kwrite);
662
663 static ssize_t
664 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
665 {
666 ssize_t ret_val;
667 int idx;
668 struct ifx_ssc_port *info;
669
670 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
671 info = &isp[idx];
672
673 if (info->rxbuf != NULL)
674 return -EBUSY;
675
676 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
677 if (info->rxbuf == NULL)
678 return -ENOMEM;
679
680 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
681 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
682 ret_val = -EFAULT;
683
684 disable_irq(info->rxirq);
685
686 kfree (info->rxbuf);
687 info->rxbuf = NULL;
688
689 return (ret_val);
690 }
691
692 static ssize_t
693 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
694 {
695 int idx;
696 struct ifx_ssc_port *info;
697 int ret_val;
698
699 if (len == 0)
700 return (0);
701
702 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
703 info = &isp[idx];
704
705 if (info->txbuf != NULL)
706 return -EBUSY;
707
708 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
709 if (info->txbuf == NULL)
710 return -ENOMEM;
711
712 ret_val = copy_from_user (info->txbuf, ubuf, len);
713 if (ret_val == 0)
714 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
715 else
716 ret_val = -EFAULT;
717
718 if (ret_val < 0)
719 {
720 kfree (info->txbuf);
721 info->txbuf = NULL;
722 }
723
724 return (ret_val);
725 }
726
727 static struct ifx_ssc_frm_status *
728 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
729 {
730 unsigned long tmp;
731
732 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFSTAT);
733 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
734 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
735 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
736 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
737 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
738 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
739 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
740
741 return &info->frm_status;
742 }
743
744
745 static struct ifx_ssc_frm_opts *
746 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
747 {
748 unsigned long tmp;
749
750 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
751 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
752 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
753 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
754 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
755 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
756 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
757
758 return &info->frm_opts;
759 }
760
761 static int
762 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
763 {
764 unsigned long tmp;
765
766 // check parameters
767 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
768 || (info->frm_opts.DataLength < 1)
769 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
770 || (info->frm_opts.PauseLength < 1)
771 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
772 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
773 return -EINVAL;
774
775 // read interrupt bits (they're not changed here)
776 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
777 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
778
779 // set all values with respect to it's bit position (for data and pause
780 // length set N-1)
781 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
782 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
783 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
784 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
785 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
786 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
787
788 WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
789
790 return 0;
791 }
792
793 static int
794 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
795 {
796 unsigned long tmp;
797
798 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
799 return -EINVAL;
800
801 if ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY)
802 || (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
803 return -EBUSY;
804
805 tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
806 WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
807 info->opts.modeRxTx = val;
808
809 return 0;
810 }
811
812 static int
813 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
814 {
815 unsigned long flags, bits;
816 struct ifx_ssc_hwopts *opts = &info->opts;
817
818 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
819 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
820 return -EINVAL;
821
822 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
823 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
824
825 if (opts->rxOvErrDetect)
826 bits |= IFX_SSC_CON_RX_OFL_CHECK;
827 if (opts->rxUndErrDetect)
828 bits |= IFX_SSC_CON_RX_UFL_CHECK;
829 if (opts->txOvErrDetect)
830 bits |= IFX_SSC_CON_TX_OFL_CHECK;
831 if (opts->txUndErrDetect)
832 bits |= IFX_SSC_CON_TX_UFL_CHECK;
833 if (opts->loopBack)
834 bits |= IFX_SSC_CON_LOOPBACK_MODE;
835 if (opts->echoMode)
836 bits |= IFX_SSC_CON_ECHO_MODE_ON;
837 if (opts->headingControl)
838 bits |= IFX_SSC_CON_MSB_FIRST;
839 if (opts->clockPhase)
840 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
841 if (opts->clockPolarity)
842 bits |= IFX_SSC_CON_CLOCK_FALL;
843
844 switch (opts->modeRxTx)
845 {
846 case IFX_SSC_MODE_TX:
847 bits |= IFX_SSC_CON_RX_OFF;
848 break;
849 case IFX_SSC_MODE_RX:
850 bits |= IFX_SSC_CON_TX_OFF;
851 break;
852 }
853
854 local_irq_save (flags);
855
856 WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
857 WRITE_PERIPHERAL_REGISTER ((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
858 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), info->mapbase + IFX_SSC_GPOCON);
859
860 WRITE_PERIPHERAL_REGISTER (info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, info->mapbase + IFX_SSC_WHBGPOSTAT);
861
862 //master mode
863 if (opts->masterSelect)
864 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
865 else
866 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
867
868 // init serial framing
869 WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
870 /* set up the port pins */
871 //check for general requirements to switch (external) pad/pin characteristics
872 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
873 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
874 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
875 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
876 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
877 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
878 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
879
880 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
881 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
882 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
883 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
884 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
885
886 /*CS3 */
887 /*TODO: CS4 CS5 CS6 */
888 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
889
890 local_irq_restore (flags);
891
892 return 0;
893 }
894
895 static int
896 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
897 {
898 unsigned int ifx_ssc_clock;
899 unsigned int br;
900 unsigned long flags;
901 bool enabled;
902 int retval = 0;
903
904 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
905 if (ifx_ssc_clock == 0)
906 {
907 retval = -EINVAL;
908 goto out;
909 }
910
911 local_irq_save (flags);
912
913 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
914 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
915
916 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
917 wmb();
918
919 if (br > 0xffff || ((br == 0) &&
920 ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
921 local_irq_restore (flags);
922 printk ("%s: invalid baudrate %u\n", __func__, baud);
923 return -EINVAL;
924 }
925
926 WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
927
928 if (enabled)
929 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
930
931 local_irq_restore(flags);
932
933 out:
934 return retval;
935 }
936
937 static int
938 ifx_ssc_hwinit (struct ifx_ssc_port *info)
939 {
940 unsigned long flags;
941 bool enabled;
942
943 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
944 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
945
946 if (ifx_ssc_sethwopts (info) < 0)
947 {
948 printk ("%s: setting the hardware options failed\n", __func__);
949 return -EINVAL;
950 }
951
952 if (ifx_ssc_set_baud (info, info->baud) < 0)
953 {
954 printk ("%s: setting the baud rate failed\n", __func__);
955 return -EINVAL;
956 }
957
958 local_irq_save (flags);
959
960 /* TX FIFO */
961 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
962 info->mapbase + IFX_SSC_TXFCON);
963 /* RX FIFO */
964 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
965 info->mapbase + IFX_SSC_RXFCON);
966
967 local_irq_restore (flags);
968
969 if (enabled)
970 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
971
972 return 0;
973 }
974
975 int
976 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
977 {
978 struct ifx_ssc_port *info;
979 int line, ret_val = 0;
980 unsigned long flags;
981 unsigned long tmp;
982 int from_kernel = 0;
983
984 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
985 {
986 from_kernel = 1;
987 line = (int) inode;
988 } else {
989 line = MINOR (filp->f_dentry->d_inode->i_rdev);
990 }
991
992 if (line < 0 || line >= PORT_CNT)
993 return -ENXIO;
994
995 info = &isp[line];
996
997 switch (cmd)
998 {
999 case IFX_SSC_STATS_READ:
1000 /* data must be a pointer to a struct ifx_ssc_statistics */
1001 if (from_kernel)
1002 memcpy ((void *) data, (void *) &info->stats,
1003 sizeof (struct ifx_ssc_statistics));
1004 else if (copy_to_user ((void *) data,
1005 (void *) &info->stats,
1006 sizeof (struct ifx_ssc_statistics)))
1007 ret_val = -EFAULT;
1008 break;
1009 case IFX_SSC_STATS_RESET:
1010 /* just resets the statistics counters */
1011 memset ((void *) &info->stats, 0,
1012 sizeof (struct ifx_ssc_statistics));
1013 break;
1014 case IFX_SSC_BAUD_SET:
1015 /* if the buffers are not empty then the port is */
1016 /* busy and we shouldn't change things on-the-fly! */
1017 if (!info->txbuf || !info->rxbuf ||
1018 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1019 & IFX_SSC_STATE_BUSY)) {
1020 ret_val = -EBUSY;
1021 break;
1022 }
1023 /* misuse flags */
1024 if (from_kernel)
1025 flags = *((unsigned long *) data);
1026 else if (copy_from_user ((void *) &flags,
1027 (void *) data, sizeof (flags))) {
1028 ret_val = -EFAULT;
1029 break;
1030 }
1031 if (flags == 0) {
1032 ret_val = -EINVAL;
1033 break;
1034 }
1035 if (ifx_ssc_set_baud (info, flags) < 0) {
1036 ret_val = -EINVAL;
1037 break;
1038 }
1039 info->baud = flags;
1040 break;
1041 case IFX_SSC_BAUD_GET:
1042 if (from_kernel)
1043 *((unsigned int *) data) = info->baud;
1044 else if (copy_to_user ((void *) data,
1045 (void *) &info->baud,
1046 sizeof (unsigned long)))
1047 ret_val = -EFAULT;
1048 break;
1049 case IFX_SSC_RXTX_MODE_SET:
1050 if (from_kernel)
1051 tmp = *((unsigned long *) data);
1052 else if (copy_from_user ((void *) &tmp,
1053 (void *) data, sizeof (tmp))) {
1054 ret_val = -EFAULT;
1055 break;
1056 }
1057 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
1058 break;
1059 case IFX_SSC_RXTX_MODE_GET:
1060 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
1061 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
1062 if (from_kernel)
1063 *((unsigned int *) data) = tmp;
1064 else if (copy_to_user ((void *) data,
1065 (void *) &tmp, sizeof (tmp)))
1066 ret_val = -EFAULT;
1067 break;
1068
1069 case IFX_SSC_ABORT:
1070 ifx_ssc_abort (info);
1071 break;
1072
1073 case IFX_SSC_GPO_OUT_SET:
1074 if (from_kernel)
1075 tmp = *((unsigned long *) data);
1076 else if (copy_from_user ((void *) &tmp,
1077 (void *) data, sizeof (tmp))) {
1078 ret_val = -EFAULT;
1079 break;
1080 }
1081 if (tmp > IFX_SSC_MAX_GPO_OUT)
1082 ret_val = -EINVAL;
1083 else
1084 WRITE_PERIPHERAL_REGISTER
1085 (1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
1086 info->mapbase + IFX_SSC_WHBGPOSTAT);
1087 break;
1088 case IFX_SSC_GPO_OUT_CLR:
1089 if (from_kernel)
1090 tmp = *((unsigned long *) data);
1091 else if (copy_from_user ((void *) &tmp,
1092 (void *) data, sizeof (tmp))) {
1093 ret_val = -EFAULT;
1094 break;
1095 }
1096 if (tmp > IFX_SSC_MAX_GPO_OUT)
1097 ret_val = -EINVAL;
1098 else {
1099 WRITE_PERIPHERAL_REGISTER
1100 (1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1101 info->mapbase + IFX_SSC_WHBGPOSTAT);
1102 }
1103 break;
1104 case IFX_SSC_GPO_OUT_GET:
1105 tmp = READ_PERIPHERAL_REGISTER
1106 (info->mapbase + IFX_SSC_GPOSTAT);
1107 if (from_kernel)
1108 *((unsigned int *) data) = tmp;
1109 else if (copy_to_user ((void *) data,
1110 (void *) &tmp, sizeof (tmp)))
1111 ret_val = -EFAULT;
1112 break;
1113 case IFX_SSC_FRM_STATUS_GET:
1114 ifx_ssc_frm_status_get (info);
1115 if (from_kernel)
1116 memcpy ((void *) data, (void *) &info->frm_status,
1117 sizeof (struct ifx_ssc_frm_status));
1118 else if (copy_to_user ((void *) data,
1119 (void *) &info->frm_status,
1120 sizeof (struct ifx_ssc_frm_status)))
1121 ret_val = -EFAULT;
1122 break;
1123 case IFX_SSC_FRM_CONTROL_GET:
1124 ifx_ssc_frm_control_get (info);
1125 if (from_kernel)
1126 memcpy ((void *) data, (void *) &info->frm_opts,
1127 sizeof (struct ifx_ssc_frm_opts));
1128 else if (copy_to_user ((void *) data,
1129 (void *) &info->frm_opts,
1130 sizeof (struct ifx_ssc_frm_opts)))
1131 ret_val = -EFAULT;
1132 break;
1133 case IFX_SSC_FRM_CONTROL_SET:
1134 if (from_kernel)
1135 memcpy ((void *) &info->frm_opts, (void *) data,
1136 sizeof (struct ifx_ssc_frm_opts));
1137 else if (copy_to_user ((void *) &info->frm_opts,
1138 (void *) data,
1139 sizeof (struct ifx_ssc_frm_opts))) {
1140 ret_val = -EFAULT;
1141 break;
1142 }
1143 ret_val = ifx_ssc_frm_control_set (info);
1144 break;
1145 case IFX_SSC_HWOPTS_SET:
1146 /* data must be a pointer to a struct ifx_ssc_hwopts */
1147 /* if the buffers are not empty then the port is */
1148 /* busy and we shouldn't change things on-the-fly! */
1149 if (!info->txbuf || !info->rxbuf ||
1150 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1151 & IFX_SSC_STATE_BUSY)) {
1152 ret_val = -EBUSY;
1153 break;
1154 }
1155 if (from_kernel)
1156 memcpy ((void *) &info->opts, (void *) data,
1157 sizeof (struct ifx_ssc_hwopts));
1158 else if (copy_from_user ((void *) &info->opts,
1159 (void *) data,
1160 sizeof (struct ifx_ssc_hwopts))) {
1161 ret_val = -EFAULT;
1162 break;
1163 }
1164 if (ifx_ssc_hwinit (info) < 0) {
1165 ret_val = -EIO;
1166 }
1167 break;
1168 case IFX_SSC_HWOPTS_GET:
1169 /* data must be a pointer to a struct ifx_ssc_hwopts */
1170 if (from_kernel)
1171 memcpy ((void *) data, (void *) &info->opts,
1172 sizeof (struct ifx_ssc_hwopts));
1173 else if (copy_to_user ((void *) data,
1174 (void *) &info->opts,
1175 sizeof (struct ifx_ssc_hwopts)))
1176 ret_val = -EFAULT;
1177 break;
1178 default:
1179 ret_val = -ENOIOCTLCMD;
1180 }
1181
1182 return ret_val;
1183 }
1184 EXPORT_SYMBOL(ifx_ssc_ioctl);
1185
1186 static int
1187 ifx_ssc1_read_proc (char *page, char **start, off_t offset, int count, int *eof, void *data)
1188 {
1189 int off = 0;
1190 unsigned long flags;
1191
1192 local_save_flags(flags);
1193 local_irq_disable();
1194
1195 off += sprintf (page + off, "Statistics for Infineon Synchronous Serial Controller SSC1\n");
1196 off += sprintf (page + off, "RX overflow errors %d\n", isp[0].stats.rxOvErr);
1197 off += sprintf (page + off, "RX underflow errors %d\n", isp[0].stats.rxUnErr);
1198 off += sprintf (page + off, "TX overflow errors %d\n", isp[0].stats.txOvErr);
1199 off += sprintf (page + off, "TX underflow errors %d\n", isp[0].stats.txUnErr);
1200 off += sprintf (page + off, "Abort errors %d\n", isp[0].stats.abortErr);
1201 off += sprintf (page + off, "Mode errors %d\n", isp[0].stats.modeErr);
1202 off += sprintf (page + off, "RX Bytes %d\n", isp[0].stats.rxBytes);
1203 off += sprintf (page + off, "TX Bytes %d\n", isp[0].stats.txBytes);
1204
1205 local_irq_restore(flags);
1206 *eof = 1;
1207
1208 return off;
1209 }
1210
1211 int __init
1212 ifx_ssc_init (void)
1213 {
1214 struct ifx_ssc_port *info;
1215 int i, nbytes;
1216 unsigned long flags;
1217 int ret_val;
1218
1219 ret_val = -ENOMEM;
1220 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1221 isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
1222
1223 if (isp == NULL)
1224 {
1225 printk("%s: no memory for isp\n", __func__);
1226 return (ret_val);
1227 }
1228 memset(isp, 0, nbytes);
1229
1230 ret_val = -ENXIO;
1231 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1232 {
1233 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1234 if (maj == 0)
1235 {
1236 goto errout;
1237 } else {
1238 maj = 0;
1239 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1240 {
1241 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1242 goto errout;
1243 }
1244 }
1245 }
1246
1247 if (maj == 0)
1248 maj = i;
1249
1250 /* set default values in ifx_ssc_port */
1251 for (i = 0; i < PORT_CNT; i++) {
1252 info = &isp[i];
1253 info->port_nr = i;
1254 /* default values for the HwOpts */
1255 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1256 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1257 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1258 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1259 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1260 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1261 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1262 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1263 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1264 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1265 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1266 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1267 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1268 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1269 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1270 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1271 info->baud = IFX_SSC_DEF_BAUDRATE;
1272 info->rxbuf = NULL;
1273 info->txbuf = NULL;
1274 /* values specific to SSC1 */
1275 if (i == 0) {
1276 info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
1277 info->txirq = IFXMIPS_SSC_TIR;
1278 info->rxirq = IFXMIPS_SSC_RIR;
1279 info->errirq = IFXMIPS_SSC_EIR;
1280 }
1281
1282 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
1283
1284 init_waitqueue_head (&info->rwait);
1285
1286 local_irq_save (flags);
1287
1288 // init serial framing register
1289 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
1290
1291 ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
1292 if (ret_val)
1293 {
1294 printk("%s: unable to get irq %d\n", __func__, info->txirq);
1295 local_irq_restore(flags);
1296 goto errout;
1297 }
1298
1299 ret_val = request_irq(info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
1300 if (ret_val)
1301 {
1302 printk ("%s: unable to get irq %d\n", __func__, info->rxirq);
1303 local_irq_restore (flags);
1304 goto irqerr;
1305 }
1306
1307 ret_val = request_irq(info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
1308 if (ret_val)
1309 {
1310 printk ("%s: unable to get irq %d\n", __func__, info->errirq);
1311 local_irq_restore (flags);
1312 goto irqerr;
1313 }
1314 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
1315
1316 enable_irq(info->txirq);
1317 enable_irq(info->rxirq);
1318 enable_irq(info->errirq);
1319
1320 local_irq_restore (flags);
1321 }
1322
1323 for (i = 0; i < PORT_CNT; i++) {
1324 info = &isp[i];
1325 if (ifx_ssc_hwinit (info) < 0)
1326 {
1327 printk ("%s: hardware init failed for port %d\n", __func__, i);
1328 goto irqerr;
1329 }
1330 }
1331
1332 create_proc_read_entry ("driver/ssc1", 0, NULL, ifx_ssc1_read_proc, NULL);
1333
1334 return 0;
1335
1336 irqerr:
1337 free_irq(isp[0].txirq, &isp[0]);
1338 free_irq(isp[0].rxirq, &isp[0]);
1339 free_irq(isp[0].errirq, &isp[0]);
1340 errout:
1341 kfree (isp);
1342 return (ret_val);
1343 }
1344
1345 void
1346 ifx_ssc_cleanup_module (void)
1347 {
1348 int i;
1349
1350 for (i = 0; i < PORT_CNT; i++) {
1351 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, isp[i].mapbase + IFX_SSC_WHBSTATE);
1352 free_irq(isp[i].txirq, &isp[i]);
1353 free_irq(isp[i].rxirq, &isp[i]);
1354 free_irq(isp[i].errirq, &isp[i]);
1355 }
1356 kfree (isp);
1357 remove_proc_entry ("driver/ssc1", NULL);
1358 }
1359
1360 module_init(ifx_ssc_init);
1361 module_exit(ifx_ssc_cleanup_module);
1362
1363
1364 inline int
1365 ifx_ssc_cs_low (u32 pin)
1366 {
1367 int ret = 0;
1368 if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
1369 printk ("clear CS %d fails\n", pin);
1370 wmb ();
1371
1372 return ret;
1373 }
1374 EXPORT_SYMBOL(ifx_ssc_cs_low);
1375
1376 inline int
1377 ifx_ssc_cs_high (u32 pin)
1378 {
1379 int ret = 0;
1380 if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
1381 printk ("set CS %d fails\n", pin);
1382 wmb ();
1383
1384 return ret;
1385 }
1386 EXPORT_SYMBOL(ifx_ssc_cs_high);
1387
1388 static int
1389 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1390 {
1391 int ret = 0;
1392
1393 char *ssc_tx_buf = NULL;
1394 char *ssc_rx_buf = NULL;
1395 int eff_size = 0;
1396 u8 mode = 0;
1397
1398 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1399 printk ("invalid parameters\n");
1400 ret = -EINVAL;
1401 goto ssc_session_exit;
1402 }
1403 else if (tx_buf == NULL || tx_len == 0) {
1404 if (rx_buf != NULL && rx_len != 0) {
1405 mode = IFX_SSC_MODE_RX;
1406 }
1407 else {
1408 printk ("invalid parameters\n");
1409 ret = -EINVAL;
1410 goto ssc_session_exit;
1411 }
1412 }
1413 else if (rx_buf == NULL || rx_len == 0) {
1414 if (tx_buf != NULL && tx_len != 0) {
1415 mode = IFX_SSC_MODE_TX;
1416 }
1417 else {
1418 printk ("invalid parameters\n");
1419 ret = -EINVAL;
1420 goto ssc_session_exit;
1421 }
1422 }
1423 else {
1424 mode = IFX_SSC_MODE_RXTX;
1425 }
1426
1427 if (mode == IFX_SSC_MODE_RXTX) {
1428 eff_size = tx_len + rx_len;
1429 }
1430 else if (mode == IFX_SSC_MODE_RX) {
1431 eff_size = rx_len;
1432 }
1433 else {
1434 eff_size = tx_len;
1435 }
1436
1437 //4 bytes alignment, required by driver
1438 /* change by TaiCheng */
1439 //if (in_irq()){
1440 if (1) {
1441 ssc_tx_buf =
1442 (char *) kmalloc (sizeof (char) *
1443 ((eff_size + 3) & (~3)),
1444 GFP_ATOMIC);
1445 ssc_rx_buf =
1446 (char *) kmalloc (sizeof (char) *
1447 ((eff_size + 3) & (~3)),
1448 GFP_ATOMIC);
1449 }
1450 else {
1451 ssc_tx_buf =
1452 (char *) kmalloc (sizeof (char) *
1453 ((eff_size + 3) & (~3)),
1454 GFP_KERNEL);
1455 ssc_rx_buf =
1456 (char *) kmalloc (sizeof (char) *
1457 ((eff_size + 3) & (~3)),
1458 GFP_KERNEL);
1459 }
1460 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1461 printk ("no memory for size of %d\n", eff_size);
1462 ret = -ENOMEM;
1463 goto ssc_session_exit;
1464 }
1465 memset ((void *) ssc_tx_buf, 0, eff_size);
1466 memset ((void *) ssc_rx_buf, 0, eff_size);
1467
1468 if (tx_len > 0) {
1469 memcpy (ssc_tx_buf, tx_buf, tx_len);
1470 }
1471
1472 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
1473
1474 if (ret > 0) {
1475 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
1476 }
1477
1478 if (ret != eff_size) {
1479 printk ("ifx_ssc_write return %d\n", ret);
1480 goto ssc_session_exit;
1481 }
1482 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
1483 if (ret != eff_size) {
1484 printk ("ifx_ssc_read return %d\n", ret);
1485 goto ssc_session_exit;
1486 }
1487
1488 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
1489
1490 if (mode == IFX_SSC_MODE_TX) {
1491 ret = tx_len;
1492 }
1493 else {
1494 ret = rx_len;
1495 }
1496 ssc_session_exit:
1497
1498 if (ssc_tx_buf != NULL)
1499 kfree (ssc_tx_buf);
1500 if (ssc_rx_buf != NULL)
1501 kfree (ssc_rx_buf);
1502
1503 if (ret < 0) {
1504 printk ("ssc session fails\n");
1505 }
1506 return ret;
1507 }
1508
1509 int
1510 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1511 {
1512 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1513 }
1514 EXPORT_SYMBOL(ifx_ssc_txrx);
1515
1516 int
1517 ifx_ssc_tx (char *tx_buf, u32 tx_len)
1518 {
1519 return ssc_session(tx_buf, tx_len, NULL, 0);
1520 }
1521 EXPORT_SYMBOL(ifx_ssc_tx);
1522
1523 int
1524 ifx_ssc_rx (char *rx_buf, u32 rx_len)
1525 {
1526 return ssc_session(NULL, 0, rx_buf, rx_len);
1527 }
1528 EXPORT_SYMBOL(ifx_ssc_rx);
1529
1530 MODULE_LICENSE("GPL");
1531 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1532 MODULE_DESCRIPTION("ifxmips ssc driver");
1533