target/linux/ifxmips/files/drivers/crypto/ifxmips/ifxmips_deu_danube.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
  17  *   Copyright (C) 2009 Mohammad Firdaus / Infineon Technologies
  18  */
  19
  20 /*!
  21   \defgroup IFX_DEU IFX_DEU_DRIVERS
  22   \ingroup API
  23   \brief deu driver module
  24 */
  25
  26 /*!
  27   \file    ifxmips_deu_danube.h
  28   \brief board specific driver header file for danube
  29 */
  30
  31 /*!
  32   \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS
  33   \ingroup IFX_DEU
  34   \brief board specific deu header files
  35 */
  36
  37 #ifndef IFXMIPS_DEU_DANUBE_H
  38 #define IFXMIPS_DEU_DANUBE_H
  39
  40 #ifdef CONFIG_CRYPTO_DEV_DMA
  41 #define DEU_DWORD_REORDERING(ptr, buffer, in_out, bytes)      memory_alignment(ptr, buffer, in_out, bytes)
  42 #define AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes)    aes_dma_memory_copy(outcopy, out_dma, out_arg, nbytes)
  43 #define DES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes)    des_dma_memory_copy(outcopy, out_dma, out_arg, nbytes)
  44 #define BUFFER_IN       1
  45 #define BUFFER_OUT      0
  46 #define DELAY_PERIOD    9
  47 #define AES_ALGO        1
  48 #define DES_ALGO        0
  49 #define FREE_MEMORY(buff)   memory_release(buff)
  50 #define ALLOCATE_MEMORY(val, type) type ? aes_memory_allocate(val) : des_memory_allocate(val)
  51 #endif /* CONFIG_CRYPTO_DEV_DMA */
  52
  53 #define INPUT_ENDIAN_SWAP(input) input_swap(input)
  54 #define DEU_ENDIAN_SWAP(input)   endian_swap(input)
  55 #define AES_DMA_MISC_CONFIG()
  56
  57 #define WAIT_AES_DMA_READY()          \
  58     do {                   \
  59         int i;                  \
  60         volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
  61         volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
  62         for (i = 0; i < 10; i++)      \
  63             udelay(DELAY_PERIOD);     \
  64         while (dma->controlr.BSY) {}; \
  65         while (aes->controlr.BUS) {}; \
  66     } while (0)
  67
  68 #define WAIT_DES_DMA_READY()          \
  69     do {                   \
  70         int i;                  \
  71         volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
  72         volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
  73         for (i = 0; i < 10; i++)      \
  74             udelay(DELAY_PERIOD);     \
  75         while (dma->controlr.BSY) {}; \
  76         while (des->controlr.BUS) {}; \
  77     } while (0)
  78
  79 #define SHA_HASH_INIT                  \
  80     do {                               \
  81         volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
  82         hash->controlr.SM = 1;    \
  83         hash->controlr.ALGO = 0;  \
  84         hash->controlr.INIT = 1;  \
  85     } while(0)
  86
  87 /* DEU STRUCTURES */
  88
  89 struct clc_controlr_t {
  90     u32 Res:26;
  91     u32 FSOE:1;
  92     u32 SBWE:1;
  93     u32 EDIS:1;
  94     u32 SPEN:1;
  95     u32 DISS:1;
  96     u32 DISR:1;
  97
  98 };
  99
 100 struct des_t {
 101     struct des_controlr {
 102         u32 KRE:1;
 103         u32 reserved1:5;
 104         u32 GO:1;
 105         u32 STP:1;
 106         u32 Res2:6;
 107         u32 NDC:1;
 108         u32 ENDI:1;
 109         u32 Res3:2;
 110         u32 F:3;
 111         u32 O:3;
 112         u32 BUS:1;
 113         u32 DAU:1;
 114         u32 ARS:1;
 115         u32 SM:1;
 116         u32 E_D:1;
 117         u32 M:3;
 118
 119     } controlr;
 120     u32 IHR;
 121     u32 ILR;
 122     u32 K1HR;
 123     u32 K1LR;
 124     u32 K2HR;
 125     u32 K2LR;
 126     u32 K3HR;
 127     u32 K3LR;
 128     u32 IVHR;
 129     u32 IVLR;
 130     u32 OHR;
 131     u32 OLR;
 132 };
 133
 134 struct aes_t {
 135     struct aes_controlr {
 136
 137         u32 KRE:1;
 138         u32 reserved1:4;
 139         u32 PNK:1;
 140         u32 GO:1;
 141         u32 STP:1;
 142
 143         u32 reserved2:6;
 144         u32 NDC:1;
 145         u32 ENDI:1;
 146         u32 reserved3:2;
 147
 148         u32 F:3;    //fbs
 149         u32 O:3;    //om
 150         u32 BUS:1;  //bsy
 151         u32 DAU:1;
 152         u32 ARS:1;
 153         u32 SM:1;
 154         u32 E_D:1;
 155         u32 KV:1;
 156         u32 K:2;    //KL
 157
 158     } controlr;
 159     u32 ID3R;       //80h
 160     u32 ID2R;       //84h
 161     u32 ID1R;       //88h
 162     u32 ID0R;       //8Ch
 163     u32 K7R;        //90h
 164     u32 K6R;        //94h
 165     u32 K5R;        //98h
 166     u32 K4R;        //9Ch
 167     u32 K3R;        //A0h
 168     u32 K2R;        //A4h
 169     u32 K1R;        //A8h
 170     u32 K0R;        //ACh
 171     u32 IV3R;       //B0h
 172     u32 IV2R;       //B4h
 173     u32 IV1R;       //B8h
 174     u32 IV0R;       //BCh
 175     u32 OD3R;       //D4h
 176     u32 OD2R;       //D8h
 177     u32 OD1R;       //DCh
 178     u32 OD0R;       //E0h
 179 };
 180
 181 struct deu_hash_t {
 182     struct hash_controlr {
 183         u32 reserved1:5;
 184         u32 KHS:1;
 185         u32 GO:1;
 186         u32 INIT:1;
 187         u32 reserved2:6;
 188         u32 NDC:1;
 189         u32 ENDI:1;
 190         u32 reserved3:7;
 191         u32 DGRY:1;
 192         u32 BSY:1;
 193         u32 reserved4:1;
 194         u32 IRCL:1;
 195         u32 SM:1;
 196         u32 KYUE:1;
 197                 u32 HMEN:1;
 198         u32 SSEN:1;
 199         u32 ALGO:1;
 200
 201     } controlr;
 202     u32 MR;         //B4h
 203     u32 D1R;        //B8h
 204     u32 D2R;        //BCh
 205     u32 D3R;        //C0h
 206     u32 D4R;        //C4h
 207     u32 D5R;        //C8h
 208
 209     u32 dummy;      //CCh
 210
 211     u32 KIDX;       //D0h
 212     u32 KEY;        //D4h
 213     u32 DBN;        //D8h
 214 };
 215
 216 struct deu_dma_t {
 217     struct dma_controlr {
 218         u32 reserved1:22;
 219         u32 BS:2;
 220         u32 BSY:1;
 221         u32 reserved2:1;
 222         u32 ALGO:2;
 223         u32 RXCLS:2;
 224         u32 reserved3:1;
 225         u32 EN:1;
 226
 227     } controlr;
 228 };
 229
 230 #endif  /* IFXMIPS_DEU_DANUBE_H */