target/linux/ifxmips/files/drivers/net/danube_mii0.c

   1 /*
   2  *   drivers/net/ifxmips_mii0.c
   3  *
   4  *   This program is free software; you can redistribute it and/or modify
   5  *   it under the terms of the GNU General Public License as published by
   6  *   the Free Software Foundation; either version 2 of the License, or
   7  *   (at your option) any later version.
   8  *
   9  *   This program is distributed in the hope that it will be useful,
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *   GNU General Public License for more details.
  13  *
  14  *   You should have received a copy of the GNU General Public License
  15  *   along with this program; if not, write to the Free Software
  16  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  17  *
  18  *   Copyright (C) 2005 Infineon
  19  *
  20  *   Rewrite of Infineon IFXMips code, thanks to infineon for the support,
  21  *   software and hardware
  22  *
  23  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  24  *
  25  */
  26
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/errno.h>
  30 #include <linux/types.h>
  31 #include <linux/interrupt.h>
  32 #include <asm/uaccess.h>
  33 #include <linux/in.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/mm.h>
  40 #include <linux/ethtool.h>
  41 #include <asm/checksum.h>
  42 #include <linux/init.h>
  43 #include <asm/delay.h>
  44 #include <asm/ifxmips/ifxmips.h>
  45 #include <asm/ifxmips/ifxmips_mii0.h>
  46 #include <asm/ifxmips/ifxmips_dma.h>
  47 #include <asm/ifxmips/ifxmips_pmu.h>
  48
  49 static struct net_device ifxmips_mii0_dev;
  50 static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
  51
  52 void
  53 ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
  54 {
  55         u32 val = MDIO_ACC_REQUEST |
  56                 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
  57                 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
  58                 phy_data;
  59
  60         while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
  61         writel(val, IFXMIPS_PPE32_MDIO_ACC);
  62 }
  63
  64 unsigned short
  65 ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
  66 {
  67         u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
  68                 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
  69                 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
  70
  71         writel(val, IFXMIPS_PPE32_MDIO_ACC);
  72         while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
  73         val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
  74
  75         return val;
  76 }
  77
  78 int
  79 ifxmips_switch_open (struct net_device *dev)
  80 {
  81         struct switch_priv* priv = (struct switch_priv*)dev->priv;
  82         struct dma_device_info* dma_dev = priv->dma_device;
  83         int i;
  84
  85         for (i = 0; i < dma_dev->max_rx_chan_num; i++)
  86         {
  87                 if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
  88                         (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
  89         }
  90
  91         netif_start_queue(dev);
  92
  93         return 0;
  94 }
  95
  96 int
  97 switch_release (struct net_device *dev){
  98         struct switch_priv* priv = (struct switch_priv*)dev->priv;
  99         struct dma_device_info* dma_dev = priv->dma_device;
 100         int i;
 101
 102         for (i = 0; i < dma_dev->max_rx_chan_num; i++)
 103                 dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
 104
 105         netif_stop_queue(dev);
 106
 107         return 0;
 108 }
 109
 110 int
 111 switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
 112 {
 113         struct switch_priv *priv = (struct switch_priv*)dev->priv;
 114         unsigned char* buf = NULL;
 115         struct sk_buff *skb = NULL;
 116         int len = 0;
 117
 118         len = dma_device_read(dma_dev, &buf, (void**)&skb);
 119
 120         if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
 121         {
 122                 printk("packet too large %d\n",len);
 123                 goto switch_hw_receive_err_exit;
 124         }
 125
 126         /* remove CRC */
 127         len -= 4;
 128         if (skb == NULL )
 129         {
 130                 printk("cannot restore pointer\n");
 131                 goto switch_hw_receive_err_exit;
 132         }
 133
 134         if (len > (skb->end - skb->tail))
 135         {
 136                 printk("BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
 137                 goto switch_hw_receive_err_exit;
 138         }
 139
 140         skb_put(skb, len);
 141         skb->dev = dev;
 142         skb->protocol = eth_type_trans(skb, dev);
 143         netif_rx(skb);
 144
 145         priv->stats.rx_packets++;
 146         priv->stats.rx_bytes += len;
 147
 148         return 0;
 149
 150 switch_hw_receive_err_exit:
 151         if (len == 0)
 152         {
 153                 if(skb)
 154                         dev_kfree_skb_any(skb);
 155                 priv->stats.rx_errors++;
 156                 priv->stats.rx_dropped++;
 157
 158                 return -EIO;
 159         } else {
 160                 return len;
 161         }
 162 }
 163
 164 int
 165 switch_hw_tx (char *buf, int len, struct net_device *dev)
 166 {
 167         int ret = 0;
 168         struct switch_priv *priv = dev->priv;
 169         struct dma_device_info* dma_dev = priv->dma_device;
 170
 171         ret = dma_device_write(dma_dev, buf, len, priv->skb);
 172
 173         return ret;
 174 }
 175
 176 int
 177 switch_tx (struct sk_buff *skb, struct net_device *dev)
 178 {
 179         int len;
 180         char *data;
 181         struct switch_priv *priv = dev->priv;
 182         struct dma_device_info* dma_dev = priv->dma_device;
 183
 184         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 185         data = skb->data;
 186         priv->skb = skb;
 187         dev->trans_start = jiffies;
 188         // TODO we got more than 1 dma channel, so we should do something intelligent
 189         // here to select one
 190         dma_dev->current_tx_chan = 0;
 191
 192         wmb();
 193
 194         if (switch_hw_tx(data, len, dev) != len)
 195         {
 196                 dev_kfree_skb_any(skb);
 197                 priv->stats.tx_errors++;
 198                 priv->stats.tx_dropped++;
 199         } else {
 200                 priv->stats.tx_packets++;
 201                 priv->stats.tx_bytes+=len;
 202         }
 203
 204         return 0;
 205 }
 206
 207 void
 208 switch_tx_timeout (struct net_device *dev)
 209 {
 210         int i;
 211         struct switch_priv* priv = (struct switch_priv*)dev->priv;
 212
 213         priv->stats.tx_errors++;
 214
 215         for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
 216         {
 217                 priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
 218         }
 219
 220         netif_wake_queue(dev);
 221
 222         return;
 223 }
 224
 225 int
 226 dma_intr_handler (struct dma_device_info* dma_dev, int status)
 227 {
 228         int i;
 229
 230         switch (status)
 231         {
 232         case RCV_INT:
 233                 switch_hw_receive(&ifxmips_mii0_dev, dma_dev);
 234                 break;
 235
 236         case TX_BUF_FULL_INT:
 237                 printk("tx buffer full\n");
 238                 netif_stop_queue(&ifxmips_mii0_dev);
 239                 for (i = 0; i < dma_dev->max_tx_chan_num; i++)
 240                 {
 241                         if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
 242                                 dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
 243                 }
 244                 break;
 245
 246         case TRANSMIT_CPT_INT:
 247                 for (i = 0; i < dma_dev->max_tx_chan_num; i++)
 248                         dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
 249
 250                 netif_wake_queue(&ifxmips_mii0_dev);
 251                 break;
 252         }
 253
 254         return 0;
 255 }
 256
 257 unsigned char*
 258 ifxmips_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
 259 {
 260         unsigned char *buffer = NULL;
 261         struct sk_buff *skb = NULL;
 262
 263         skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
 264         if (skb == NULL)
 265                 return NULL;
 266
 267         buffer = (unsigned char*)(skb->data);
 268         skb_reserve(skb, 2);
 269         *(int*)opt = (int)skb;
 270         *byte_offset = 2;
 271
 272         return buffer;
 273 }
 274
 275 void
 276 ifxmips_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
 277 {
 278         struct sk_buff *skb = NULL;
 279
 280         if(opt == NULL)
 281         {
 282                 kfree(dataptr);
 283         } else {
 284                 skb = (struct sk_buff*)opt;
 285                 dev_kfree_skb_any(skb);
 286         }
 287 }
 288
 289 static struct net_device_stats*
 290 ifxmips_get_stats (struct net_device *dev)
 291 {
 292         return (struct net_device_stats *)dev->priv;
 293 }
 294
 295 static int
 296 switch_init (struct net_device *dev)
 297 {
 298         u64 retval = 0;
 299         int i;
 300         struct switch_priv *priv;
 301
 302         ether_setup(dev);
 303
 304         printk("%s up\n", dev->name);
 305
 306         dev->open = ifxmips_switch_open;
 307         dev->stop = switch_release;
 308         dev->hard_start_xmit = switch_tx;
 309         dev->get_stats = ifxmips_get_stats;
 310         dev->tx_timeout = switch_tx_timeout;
 311         dev->watchdog_timeo = 10 * HZ;
 312         dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
 313
 314         if (dev->priv == NULL)
 315                 return -ENOMEM;
 316
 317         memset(dev->priv, 0, sizeof(struct switch_priv));
 318         priv = dev->priv;
 319
 320         priv->dma_device = dma_device_reserve("PPE");
 321
 322         if (!priv->dma_device){
 323                 BUG();
 324                 return -ENODEV;
 325         }
 326
 327         priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
 328         priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
 329         priv->dma_device->intr_handler = &dma_intr_handler;
 330         priv->dma_device->max_rx_chan_num = 4;
 331
 332         for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
 333         {
 334                 priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
 335                 priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
 336         }
 337
 338         for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
 339         {
 340                 if(i == 0)
 341                         priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
 342                 else
 343                         priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
 344         }
 345
 346         dma_device_register(priv->dma_device);
 347
 348         /*read the mac address from the mac table and put them into the mac table.*/
 349         for (i = 0; i < 6; i++)
 350         {
 351                 retval += u_boot_ethaddr[i];
 352         }
 353
 354         //TODO
 355         /* ethaddr not set in u-boot ? */
 356         if (retval == 0)
 357         {
 358                 printk("use default MAC address\n");
 359                 dev->dev_addr[0] = 0x00;
 360                 dev->dev_addr[1] = 0x11;
 361                 dev->dev_addr[2] = 0x22;
 362                 dev->dev_addr[3] = 0x33;
 363                 dev->dev_addr[4] = 0x44;
 364                 dev->dev_addr[5] = 0x55;
 365         } else {
 366                 for (i = 0; i < 6; i++)
 367                         dev->dev_addr[i] = u_boot_ethaddr[i];
 368         }
 369
 370         return 0;
 371 }
 372
 373 static void
 374 ifxmips_sw_chip_init (int mode)
 375 {
 376         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
 377         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
 378
 379         if(mode == REV_MII_MODE)
 380                 writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
 381         else if(mode == MII_MODE)
 382                 writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
 383
 384         writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
 385
 386         writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
 387
 388         wmb();
 389 }
 390
 391 int __init
 392 switch_init_module(void)
 393 {
 394         int result = 0;
 395
 396         ifxmips_mii0_dev.init = switch_init;
 397
 398         strcpy(ifxmips_mii0_dev.name, "eth%d");
 399         SET_MODULE_OWNER(dev);
 400
 401         result = register_netdev(&ifxmips_mii0_dev);
 402         if (result)
 403         {
 404                 printk("error %i registering device \"%s\"\n", result, ifxmips_mii0_dev.name);
 405                 goto out;
 406         }
 407
 408         /* ifxmips eval kit connects the phy/switch in REV mode */
 409         ifxmips_sw_chip_init(REV_MII_MODE);
 410         printk("ifxmips MAC driver loaded!\n");
 411
 412 out:
 413         return result;
 414 }
 415
 416 static void __exit
 417 switch_cleanup(void)
 418 {
 419         struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev.priv;
 420
 421         printk("ifxmips_mii0 cleanup\n");
 422
 423         dma_device_unregister(priv->dma_device);
 424         dma_device_release(priv->dma_device);
 425         kfree(priv->dma_device);
 426         kfree(ifxmips_mii0_dev.priv);
 427         unregister_netdev(&ifxmips_mii0_dev);
 428
 429         return;
 430 }
 431
 432 module_init(switch_init_module);
 433 module_exit(switch_cleanup);