target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/errno.h>
  23 #include <linux/types.h>
  24 #include <linux/interrupt.h>
  25 #include <asm/uaccess.h>
  26 #include <linux/in.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/ip.h>
  30 #include <linux/tcp.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/mm.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/ethtool.h>
  35 #include <asm/checksum.h>
  36 #include <linux/init.h>
  37 #include <asm/delay.h>
  38 #include <asm/ifxmips/ifxmips.h>
  39 #include <asm/ifxmips/ifxmips_mii0.h>
  40 #include <asm/ifxmips/ifxmips_dma.h>
  41 #include <asm/ifxmips/ifxmips_pmu.h>
  42
  43 #define DRVNAME         "ifxmips_mii0"
  44
  45 static struct net_device *ifxmips_mii0_dev;
  46 static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
  47
  48 void
  49 ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data)
  50 {
  51         u32 val = MDIO_ACC_REQUEST |
  52                 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
  53                 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
  54                 phy_data;
  55
  56         while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
  57         ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
  58 }
  59
  60 unsigned short
  61 ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
  62 {
  63         u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
  64                 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
  65                 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
  66
  67         ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
  68         while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
  69         val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
  70         return val;
  71 }
  72
  73 int
  74 ifxmips_ifxmips_mii_open(struct net_device *dev)
  75 {
  76         struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
  77         struct dma_device_info* dma_dev = priv->dma_device;
  78         int i;
  79
  80         for(i = 0; i < dma_dev->max_rx_chan_num; i++)
  81         {
  82                 if((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
  83                         (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
  84         }
  85         netif_start_queue(dev);
  86         return 0;
  87 }
  88
  89 int
  90 ifxmips_mii_release(struct net_device *dev){
  91         struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
  92         struct dma_device_info* dma_dev = priv->dma_device;
  93         int i;
  94
  95         for(i = 0; i < dma_dev->max_rx_chan_num; i++)
  96                 dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
  97         netif_stop_queue(dev);
  98         return 0;
  99 }
 100
 101 int
 102 ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev)
 103 {
 104         struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)dev->priv;
 105         unsigned char* buf = NULL;
 106         struct sk_buff *skb = NULL;
 107         int len = 0;
 108
 109         len = dma_device_read(dma_dev, &buf, (void**)&skb);
 110
 111         if(len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
 112         {
 113                 printk(KERN_INFO DRVNAME ": packet too large %d\n",len);
 114                 goto ifxmips_mii_hw_receive_err_exit;
 115         }
 116
 117         /* remove CRC */
 118         len -= 4;
 119         if(skb == NULL)
 120         {
 121                 printk(KERN_INFO DRVNAME ": cannot restore pointer\n");
 122                 goto ifxmips_mii_hw_receive_err_exit;
 123         }
 124
 125         if(len > (skb->end - skb->tail))
 126         {
 127                 printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n",
 128                         (len+4), skb->end, skb->tail);
 129                 goto ifxmips_mii_hw_receive_err_exit;
 130         }
 131
 132         skb_put(skb, len);
 133         skb->dev = dev;
 134         skb->protocol = eth_type_trans(skb, dev);
 135         netif_rx(skb);
 136
 137         priv->stats.rx_packets++;
 138         priv->stats.rx_bytes += len;
 139         return 0;
 140
 141 ifxmips_mii_hw_receive_err_exit:
 142         if(len == 0)
 143         {
 144                 if(skb)
 145                         dev_kfree_skb_any(skb);
 146                 priv->stats.rx_errors++;
 147                 priv->stats.rx_dropped++;
 148                 return -EIO;
 149         } else {
 150                 return len;
 151         }
 152 }
 153
 154 int
 155 ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev)
 156 {
 157         int ret = 0;
 158         struct ifxmips_mii_priv *priv = dev->priv;
 159         struct dma_device_info* dma_dev = priv->dma_device;
 160
 161         ret = dma_device_write(dma_dev, buf, len, priv->skb);
 162
 163         return ret;
 164 }
 165
 166 int
 167 ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev)
 168 {
 169         int len;
 170         char *data;
 171         struct ifxmips_mii_priv *priv = dev->priv;
 172         struct dma_device_info* dma_dev = priv->dma_device;
 173
 174         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 175         data = skb->data;
 176         priv->skb = skb;
 177         dev->trans_start = jiffies;
 178         // TODO we got more than 1 dma channel, so we should do something intelligent
 179         // here to select one
 180         dma_dev->current_tx_chan = 0;
 181
 182         wmb();
 183
 184         if(ifxmips_mii_hw_tx(data, len, dev) != len)
 185         {
 186                 dev_kfree_skb_any(skb);
 187                 priv->stats.tx_errors++;
 188                 priv->stats.tx_dropped++;
 189         } else {
 190                 priv->stats.tx_packets++;
 191                 priv->stats.tx_bytes+=len;
 192         }
 193
 194         return 0;
 195 }
 196
 197 void
 198 ifxmips_mii_tx_timeout(struct net_device *dev)
 199 {
 200         int i;
 201         struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
 202
 203         priv->stats.tx_errors++;
 204         for(i = 0; i < priv->dma_device->max_tx_chan_num; i++)
 205                 priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
 206         netif_wake_queue(dev);
 207         return;
 208 }
 209
 210 int
 211 dma_intr_handler(struct dma_device_info* dma_dev, int status)
 212 {
 213         int i;
 214
 215         switch(status)
 216         {
 217         case RCV_INT:
 218                 ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev);
 219                 break;
 220
 221         case TX_BUF_FULL_INT:
 222                 printk(KERN_INFO DRVNAME ": tx buffer full\n");
 223                 netif_stop_queue(ifxmips_mii0_dev);
 224                 for (i = 0; i < dma_dev->max_tx_chan_num; i++)
 225                 {
 226                         if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
 227                                 dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
 228                 }
 229                 break;
 230
 231         case TRANSMIT_CPT_INT:
 232                 for(i = 0; i < dma_dev->max_tx_chan_num; i++)
 233                         dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
 234
 235                 netif_wake_queue(ifxmips_mii0_dev);
 236                 break;
 237         }
 238
 239         return 0;
 240 }
 241
 242 unsigned char*
 243 ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
 244 {
 245         unsigned char *buffer = NULL;
 246         struct sk_buff *skb = NULL;
 247
 248         skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
 249         if(skb == NULL)
 250                 return NULL;
 251
 252         buffer = (unsigned char*)(skb->data);
 253         skb_reserve(skb, 2);
 254         *(int*)opt = (int)skb;
 255         *byte_offset = 2;
 256
 257         return buffer;
 258 }
 259
 260 void
 261 ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
 262 {
 263         struct sk_buff *skb = NULL;
 264
 265         if(opt == NULL)
 266         {
 267                 kfree(dataptr);
 268         } else {
 269                 skb = (struct sk_buff*)opt;
 270                 dev_kfree_skb_any(skb);
 271         }
 272 }
 273
 274 static struct net_device_stats*
 275 ifxmips_get_stats(struct net_device *dev)
 276 {
 277         return (struct net_device_stats *)dev->priv;
 278 }
 279
 280 static int
 281 ifxmips_mii_dev_init(struct net_device *dev)
 282 {
 283         u64 retval = 0;
 284         int i;
 285         struct ifxmips_mii_priv *priv;
 286
 287         ether_setup(dev);
 288         printk(KERN_INFO DRVNAME ": %s is up\n", dev->name);
 289         dev->open = ifxmips_ifxmips_mii_open;
 290         dev->stop = ifxmips_mii_release;
 291         dev->hard_start_xmit = ifxmips_mii_tx;
 292         dev->get_stats = ifxmips_get_stats;
 293         dev->tx_timeout = ifxmips_mii_tx_timeout;
 294         dev->watchdog_timeo = 10 * HZ;
 295         memset(dev->priv, 0, sizeof(struct ifxmips_mii_priv));
 296         priv = dev->priv;
 297         priv->dma_device = dma_device_reserve("PPE");
 298         if(!priv->dma_device){
 299                 BUG();
 300                 return -ENODEV;
 301         }
 302         priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
 303         priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
 304         priv->dma_device->intr_handler = &dma_intr_handler;
 305         priv->dma_device->max_rx_chan_num = 4;
 306
 307         for(i = 0; i < priv->dma_device->max_rx_chan_num; i++)
 308         {
 309                 priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
 310                 priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
 311         }
 312
 313         for(i = 0; i < priv->dma_device->max_tx_chan_num; i++)
 314                 if(i == 0)
 315                         priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
 316                 else
 317                         priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
 318
 319         dma_device_register(priv->dma_device);
 320
 321         /*read the mac address from the mac table and put them into the mac table.*/
 322         for (i = 0; i < 6; i++)
 323                 retval += u_boot_ethaddr[i];
 324
 325         //TODO
 326         /* ethaddr not set in u-boot ? */
 327         if(retval == 0)
 328         {
 329                 printk(KERN_INFO DRVNAME ": using default MAC address\n");
 330                 dev->dev_addr[0] = 0x00;
 331                 dev->dev_addr[1] = 0x11;
 332                 dev->dev_addr[2] = 0x22;
 333                 dev->dev_addr[3] = 0x33;
 334                 dev->dev_addr[4] = 0x44;
 335                 dev->dev_addr[5] = 0x55;
 336         } else {
 337                 for(i = 0; i < 6; i++)
 338                         dev->dev_addr[i] = u_boot_ethaddr[i];
 339         }
 340
 341         return 0;
 342 }
 343
 344 static void
 345 ifxmips_mii_chip_init(int mode)
 346 {
 347         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
 348         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
 349
 350         if(mode == REV_MII_MODE)
 351                 ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
 352         else if(mode == MII_MODE)
 353                 ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
 354         ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
 355         ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
 356         wmb();
 357 }
 358
 359 static int
 360 ifxmips_mii_probe(struct platform_device *dev)
 361 {
 362         int result = 0;
 363
 364         ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
 365         ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
 366         strcpy(ifxmips_mii0_dev->name, "eth%d");
 367         result = register_netdev(ifxmips_mii0_dev);
 368         if (result)
 369         {
 370                 printk(KERN_INFO DRVNAME ": error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
 371                 goto out;
 372         }
 373
 374         /* ifxmips eval kit connects the phy/switch in REV mode */
 375         ifxmips_mii_chip_init(REV_MII_MODE);
 376         printk(KERN_INFO DRVNAME ": driver loaded!\n");
 377
 378 out:
 379         return result;
 380 }
 381
 382 static int
 383 ifxmips_mii_remove(struct platform_device *dev)
 384 {
 385         struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv;
 386
 387         printk(KERN_INFO DRVNAME ": ifxmips_mii0 cleanup\n");
 388
 389         dma_device_unregister(priv->dma_device);
 390         dma_device_release(priv->dma_device);
 391         kfree(priv->dma_device);
 392         kfree(ifxmips_mii0_dev->priv);
 393         unregister_netdev(ifxmips_mii0_dev);
 394         return 0;
 395 }
 396
 397 static struct
 398 platform_driver ifxmips_mii_driver = {
 399         .probe = ifxmips_mii_probe,
 400         .remove = ifxmips_mii_remove,
 401         .driver = {
 402                 .name = DRVNAME,
 403                 .owner = THIS_MODULE,
 404         },
 405 };
 406
 407 int __init
 408 ifxmips_mii_init(void)
 409 {
 410         int ret = platform_driver_register(&ifxmips_mii_driver);
 411         if (ret)
 412                 printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
 413         return ret;
 414 }
 415
 416 static void __exit
 417 ifxmips_mii_cleanup(void)
 418 {
 419         platform_driver_unregister(&ifxmips_mii_driver);
 420 }
 421
 422 module_init(ifxmips_mii_init);
 423 module_exit(ifxmips_mii_cleanup);
 424
 425 MODULE_LICENSE("GPL");
 426 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 427 MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards");