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adds ifxmips, uboot-ifxmips and removes etrax from 8.09 branch
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / drivers / serial / ifxmips_asc.c
1 /*
2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (C) 2004 Infineon IFAP DC COM CPE
19 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
20 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
21 */
22
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/signal.h>
26 #include <linux/sched.h>
27 #include <linux/interrupt.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/fcntl.h>
33 #include <linux/ptrace.h>
34 #include <linux/ioport.h>
35 #include <linux/mm.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/circ_buf.h>
39 #include <linux/serial.h>
40 #include <linux/serial_core.h>
41 #include <linux/console.h>
42 #include <linux/sysrq.h>
43 #include <linux/irq.h>
44 #include <linux/platform_device.h>
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/uaccess.h>
48 #include <asm/bitops.h>
49 #include <asm/ifxmips/ifxmips.h>
50 #include <asm/ifxmips/ifxmips_irq.h>
51
52 #define PORT_IFXMIPSASC 111
53
54 #include <linux/serial_core.h>
55
56 #define UART_DUMMY_UER_RX 1
57
58 static void ifxmipsasc_tx_chars(struct uart_port *port);
59 extern void prom_printf(const char * fmt, ...);
60 static struct uart_port ifxmipsasc_port[2];
61 static struct uart_driver ifxmipsasc_reg;
62 extern unsigned int ifxmips_get_fpi_hz(void);
63
64 static void
65 ifxmipsasc_stop_tx(struct uart_port *port)
66 {
67 return;
68 }
69
70 static void
71 ifxmipsasc_start_tx(struct uart_port *port)
72 {
73 unsigned long flags;
74 local_irq_save(flags);
75 ifxmipsasc_tx_chars(port);
76 local_irq_restore(flags);
77 return;
78 }
79
80 static void
81 ifxmipsasc_stop_rx(struct uart_port *port)
82 {
83 ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
84 }
85
86 static void
87 ifxmipsasc_enable_ms(struct uart_port *port)
88 {
89 }
90
91 static void
92 ifxmipsasc_rx_chars(struct uart_port *port)
93 {
94 struct tty_struct *tty = port->info->tty;
95 unsigned int ch = 0, rsr = 0, fifocnt;
96
97 fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
98 while(fifocnt--)
99 {
100 u8 flag = TTY_NORMAL;
101 ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
102 rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
103 tty_flip_buffer_push(tty);
104 port->icount.rx++;
105
106 /*
107 * Note that the error handling code is
108 * out of the main execution path
109 */
110 if(rsr & ASCSTATE_ANY)
111 {
112 if(rsr & ASCSTATE_PE)
113 {
114 port->icount.parity++;
115 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
116 } else if(rsr & ASCSTATE_FE)
117 {
118 port->icount.frame++;
119 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
120 }
121 if(rsr & ASCSTATE_ROE)
122 {
123 port->icount.overrun++;
124 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
125 }
126
127 rsr &= port->read_status_mask;
128
129 if(rsr & ASCSTATE_PE)
130 flag = TTY_PARITY;
131 else if(rsr & ASCSTATE_FE)
132 flag = TTY_FRAME;
133 }
134
135 if((rsr & port->ignore_status_mask) == 0)
136 tty_insert_flip_char(tty, ch, flag);
137
138 if(rsr & ASCSTATE_ROE)
139 /*
140 * Overrun is special, since it's reported
141 * immediately, and doesn't affect the current
142 * character
143 */
144 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
145 }
146 if(ch != 0)
147 tty_flip_buffer_push(tty);
148 return;
149 }
150
151
152 static void
153 ifxmipsasc_tx_chars(struct uart_port *port)
154 {
155 struct circ_buf *xmit = &port->info->xmit;
156 if(uart_tx_stopped(port))
157 {
158 ifxmipsasc_stop_tx(port);
159 return;
160 }
161
162 while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
163 >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL)
164 {
165 if(port->x_char)
166 {
167 ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
168 port->icount.tx++;
169 port->x_char = 0;
170 continue;
171 }
172
173 if(uart_circ_empty(xmit))
174 break;
175
176 ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
177 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
178 port->icount.tx++;
179 }
180
181 if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
182 uart_write_wakeup(port);
183 }
184
185 static irqreturn_t
186 ifxmipsasc_tx_int(int irq, void *_port)
187 {
188 struct uart_port *port = (struct uart_port*) _port;
189 ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
190 ifxmipsasc_start_tx(port);
191 ifxmips_mask_and_ack_irq(irq);
192 return IRQ_HANDLED;
193 }
194
195 static irqreturn_t
196 ifxmipsasc_er_int(int irq, void *_port)
197 {
198 struct uart_port *port = (struct uart_port*) _port;
199 /* clear any pending interrupts */
200 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
201 ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
202 return IRQ_HANDLED;
203 }
204
205 static irqreturn_t
206 ifxmipsasc_rx_int(int irq, void *_port)
207 {
208 struct uart_port *port = (struct uart_port*)_port;
209 ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
210 ifxmipsasc_rx_chars((struct uart_port*)port);
211 ifxmips_mask_and_ack_irq(irq);
212 return IRQ_HANDLED;
213 }
214
215 static unsigned int
216 ifxmipsasc_tx_empty(struct uart_port *port)
217 {
218 int status;
219 status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
220 return status ? 0 : TIOCSER_TEMT;
221 }
222
223 static unsigned int
224 ifxmipsasc_get_mctrl(struct uart_port *port)
225 {
226 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
227 }
228
229 static void
230 ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
231 {
232 }
233
234 static void
235 ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
236 {
237 }
238
239 static int
240 ifxmipsasc_startup(struct uart_port *port)
241 {
242 unsigned long flags;
243 int retval;
244
245 port->uartclk = ifxmips_get_fpi_hz();
246
247 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
248 ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
249 ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
250 ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
251 ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
252 wmb ();
253 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
254
255 local_irq_save(flags);
256
257 retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
258 if(retval)
259 {
260 printk("failed to request ifxmipsasc_tx_int\n");
261 return retval;
262 }
263
264 retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
265 if(retval)
266 {
267 printk("failed to request ifxmipsasc_rx_int\n");
268 goto err1;
269 }
270
271 retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
272 if(retval)
273 {
274 printk("failed to request ifxmipsasc_er_int\n");
275 goto err2;
276 }
277
278 ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
279
280 local_irq_restore(flags);
281 return 0;
282
283 err2:
284 free_irq(port->irq + 2, port);
285 err1:
286 free_irq(port->irq, port);
287 local_irq_restore(flags);
288 return retval;
289 }
290
291 static void
292 ifxmipsasc_shutdown(struct uart_port *port)
293 {
294 free_irq(port->irq, port);
295 free_irq(port->irq + 2, port);
296 free_irq(port->irq + 3, port);
297
298 ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
299 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
300 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
301 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
302 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
303 }
304
305 static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
306 {
307 unsigned int cflag;
308 unsigned int iflag;
309 unsigned int quot;
310 unsigned int baud;
311 unsigned int con = 0;
312 unsigned long flags;
313
314 cflag = new->c_cflag;
315 iflag = new->c_iflag;
316
317 switch(cflag & CSIZE)
318 {
319 case CS7:
320 con = ASCCON_M_7ASYNC;
321 break;
322
323 case CS5:
324 case CS6:
325 default:
326 con = ASCCON_M_8ASYNC;
327 break;
328 }
329
330 if(cflag & CSTOPB)
331 con |= ASCCON_STP;
332
333 if(cflag & PARENB)
334 {
335 if(!(cflag & PARODD))
336 con &= ~ASCCON_ODD;
337 else
338 con |= ASCCON_ODD;
339 }
340
341 port->read_status_mask = ASCSTATE_ROE;
342 if(iflag & INPCK)
343 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
344
345 port->ignore_status_mask = 0;
346 if(iflag & IGNPAR)
347 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
348
349 if(iflag & IGNBRK)
350 {
351 /*
352 * If we're ignoring parity and break indicators,
353 * ignore overruns too (for real raw support).
354 */
355 if(iflag & IGNPAR)
356 port->ignore_status_mask |= ASCSTATE_ROE;
357 }
358
359 if((cflag & CREAD) == 0)
360 port->ignore_status_mask |= UART_DUMMY_UER_RX;
361
362 /* set error signals - framing, parity and overrun, enable receiver */
363 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
364
365 local_irq_save(flags);
366
367 /* set up CON */
368 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
369
370 /* Set baud rate - take a divider of 2 into account */
371 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
372 quot = uart_get_divisor(port, baud);
373 quot = quot / 2 - 1;
374
375 /* disable the baudrate generator */
376 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
377
378 /* make sure the fractional divider is off */
379 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
380
381 /* set up to use divisor of 2 */
382 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
383
384 /* now we can write the new baudrate into the register */
385 ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
386
387 /* turn the baudrate generator back on */
388 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
389
390 /* enable rx */
391 ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
392
393 local_irq_restore(flags);
394 }
395
396 static const char*
397 ifxmipsasc_type(struct uart_port *port)
398 {
399 if(port->type == PORT_IFXMIPSASC)
400 {
401 if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR)
402 return "asc0";
403 else
404 return "asc1";
405 } else {
406 return NULL;
407 }
408 }
409
410 static void
411 ifxmipsasc_release_port(struct uart_port *port)
412 {
413 }
414
415 static int
416 ifxmipsasc_request_port(struct uart_port *port)
417 {
418 return 0;
419 }
420
421 static void
422 ifxmipsasc_config_port(struct uart_port *port, int flags)
423 {
424 if(flags & UART_CONFIG_TYPE)
425 {
426 port->type = PORT_IFXMIPSASC;
427 ifxmipsasc_request_port(port);
428 }
429 }
430
431 static int
432 ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
433 {
434 int ret = 0;
435 if(ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
436 ret = -EINVAL;
437 if(ser->irq < 0 || ser->irq >= NR_IRQS)
438 ret = -EINVAL;
439 if(ser->baud_base < 9600)
440 ret = -EINVAL;
441 return ret;
442 }
443
444 static struct uart_ops ifxmipsasc_pops =
445 {
446 .tx_empty = ifxmipsasc_tx_empty,
447 .set_mctrl = ifxmipsasc_set_mctrl,
448 .get_mctrl = ifxmipsasc_get_mctrl,
449 .stop_tx = ifxmipsasc_stop_tx,
450 .start_tx = ifxmipsasc_start_tx,
451 .stop_rx = ifxmipsasc_stop_rx,
452 .enable_ms = ifxmipsasc_enable_ms,
453 .break_ctl = ifxmipsasc_break_ctl,
454 .startup = ifxmipsasc_startup,
455 .shutdown = ifxmipsasc_shutdown,
456 .set_termios = ifxmipsasc_set_termios,
457 .type = ifxmipsasc_type,
458 .release_port = ifxmipsasc_release_port,
459 .request_port = ifxmipsasc_request_port,
460 .config_port = ifxmipsasc_config_port,
461 .verify_port = ifxmipsasc_verify_port,
462 };
463
464 static struct uart_port ifxmipsasc_port[2] =
465 {
466 {
467 membase: (void *)IFXMIPS_ASC_BASE_ADDR,
468 mapbase: IFXMIPS_ASC_BASE_ADDR,
469 iotype: SERIAL_IO_MEM,
470 irq: IFXMIPSASC_TIR(0),
471 uartclk: 0,
472 fifosize: 16,
473 type: PORT_IFXMIPSASC,
474 ops: &ifxmipsasc_pops,
475 flags: ASYNC_BOOT_AUTOCONF,
476 line: 0
477 }, {
478 membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
479 mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
480 iotype: SERIAL_IO_MEM,
481 irq: IFXMIPSASC_TIR(1),
482 uartclk: 0,
483 fifosize: 16,
484 type: PORT_IFXMIPSASC,
485 ops: &ifxmipsasc_pops,
486 flags: ASYNC_BOOT_AUTOCONF,
487 line: 1
488 }
489 };
490
491 static void
492 ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
493 {
494 int port = co->index;
495 int i, fifocnt;
496 unsigned long flags;
497 local_irq_save(flags);
498 for(i = 0; i < count; i++)
499 {
500 do {
501 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
502 >> ASCFSTAT_TXFFLOFF;
503 } while(fifocnt == TXFIFO_FULL);
504
505 if(s[i] == '\0')
506 break;
507
508 if(s[i] == '\n')
509 {
510 ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
511 do {
512 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
513 >> ASCFSTAT_TXFFLOFF;
514 } while(fifocnt == TXFIFO_FULL);
515 }
516 ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
517 }
518
519 local_irq_restore(flags);
520 }
521
522 static int __init
523 ifxmipsasc_console_setup(struct console *co, char *options)
524 {
525 int port = co->index;
526 int baud = 115200;
527 int bits = 8;
528 int parity = 'n';
529 int flow = 'n';
530 ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
531 ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
532 if(options)
533 uart_parse_options(options, &baud, &parity, &bits, &flow);
534 return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
535 }
536
537 static struct console ifxmipsasc_console[2] =
538 {
539 {
540 name: "ttyS",
541 write: ifxmipsasc_console_write,
542 device: uart_console_device,
543 setup: ifxmipsasc_console_setup,
544 flags: CON_PRINTBUFFER,
545 index: 0,
546 data: &ifxmipsasc_reg,
547 }, {
548 name: "ttyS",
549 write: ifxmipsasc_console_write,
550 device: uart_console_device,
551 setup: ifxmipsasc_console_setup,
552 flags: CON_PRINTBUFFER,
553 index: 1,
554 data: &ifxmipsasc_reg,
555 }
556 };
557
558 static int __init
559 ifxmipsasc_console_init(void)
560 {
561 register_console(&ifxmipsasc_console[0]);
562 register_console(&ifxmipsasc_console[1]);
563 return 0;
564 }
565 console_initcall(ifxmipsasc_console_init);
566
567 static struct uart_driver ifxmipsasc_reg =
568 {
569 .owner = THIS_MODULE,
570 .driver_name = "serial",
571 .dev_name = "ttyS",
572 .major = TTY_MAJOR,
573 .minor = 64,
574 .nr = 2,
575 .cons = &ifxmipsasc_console[1],
576 };
577
578 int __init
579 ifxmipsasc_init(void)
580 {
581 int ret;
582 uart_register_driver(&ifxmipsasc_reg);
583 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
584 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
585 return 0;
586 }
587
588 void __exit
589 ifxmipsasc_exit(void)
590 {
591 uart_unregister_driver(&ifxmipsasc_reg);
592 }
593
594 module_init(ifxmipsasc_init);
595 module_exit(ifxmipsasc_exit);
596
597 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
598 MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
599 MODULE_LICENSE("GPL");
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