b96d091823f83e59555dece038003146b4bebd3e
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / include / asm-mips / danube / danube_irq.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2005 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20 #ifndef _IFXMIPS_IRQ__
21 #define _IFXMIPS_IRQ__
22
23 #define INT_NUM_IRQ0 8
24 #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
25 #define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
26 #define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
27 #define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
28 #define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
29 #define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
30
31 #define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
32 #define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
33 #define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
34
35 #define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
36 #define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
37 #define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
38
39 #define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
40
41 #define MIPS_CPU_TIMER_IRQ 7
42
43 #define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
44 #define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
45 #define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
46 #define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
47 #define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
48 #define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
49 #define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
50 #define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
51 #define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
52 #define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
53 #define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
54 #define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
55 #define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
56 #define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
57 #define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
58 #define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
59 #define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
60 #define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
61 #define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
62 #define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
63
64 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
65
66 #endif