target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h

   1 /* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
   2
   3 #ifndef __IFXMIPS_ASC_H
   4 #define __IFXMIPS_ASC_H
   5
   6 /******************************************************************************
   7 **
   8 ** FILE NAME    : serial.c
   9 ** PROJECT      : Danube
  10 ** MODULES      : ASC/UART
  11 **
  12 ** DATE         : 27 MAR 2006
  13 ** AUTHOR       : Liu Peng
  14 ** DESCRIPTION  : Asynchronous Serial Channel (ASC/UART) Driver Header File
  15 ** COPYRIGHT    :       Copyright (c) 2006
  16 **                      Infineon Technologies AG
  17 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  18 **
  19 **    This program is free software; you can redistribute it and/or modify
  20 **    it under the terms of the GNU General Public License as published by
  21 **    the Free Software Foundation; either version 2 of the License, or
  22 **    (at your option) any later version.
  23 **
  24 ** HISTORY
  25 ** $Date        $Author         $Comment
  26 ** 27 MAR 2006  Liu Peng        Initiate Version (rev 1.7)
  27 ** 23 OCT 2006  Xu Liang        Add GPL header.
  28 *******************************************************************************/
  29
  30 /* channel operating modes */
  31 /*#define       ASCOPT_CSIZE    0x00000003
  32 #define ASCOPT_CS7      0x00000001
  33 #define ASCOPT_CS8      0x00000002
  34 #define ASCOPT_PARENB   0x00000004
  35 #define ASCOPT_STOPB    0x00000008
  36 #define ASCOPT_PARODD   0x00000010
  37 #define ASCOPT_CREAD    0x00000020
  38 */
  39 #define ASC_OPTIONS             (ASCOPT_CREAD | ASCOPT_CS8)
  40
  41 /* ASC input select (0 or 1) */
  42 #define CONSOLE_TTY     0
  43
  44 #define IFXMIPSASC_TXFIFO_FL       1
  45 #define IFXMIPSASC_RXFIFO_FL       1
  46 #define IFXMIPSASC_TXFIFO_FULL     16
  47
  48 /* interrupt lines masks for the ASC device interrupts*/
  49 /* change these macroses if it's necessary */
  50 #define IFXMIPSASC_IRQ_LINE_ALL        0x0000007f       /* all IRQs */
  51
  52 #define IFXMIPSASC_IRQ_LINE_TIR            0x00000001   /* Tx Int */
  53 #define IFXMIPSASC_IRQ_LINE_TBIR           0x00000002   /* Tx Buffer Int */
  54 #define IFXMIPSASC_IRQ_LINE_RIR            0x00000004   /* Rx Int */
  55 #define IFXMIPSASC_IRQ_LINE_EIR            0x00000008   /* Error Int */
  56 #define IFXMIPSASC_IRQ_LINE_ABSTIR         0x00000010   /* Autobaud Start Int */
  57 #define IFXMIPSASC_IRQ_LINE_ABDETIP        0x00000020   /* Autobaud Detection Int */
  58 #define IFXMIPSASC_IRQ_LINE_SFCIR          0x00000040   /* Software Flow Control Int */
  59
  60 /* interrupt controller access macros */
  61 #define ASC_INTERRUPTS_ENABLE(X)  \
  62 *((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
  63 #define ASC_INTERRUPTS_DISABLE(X) \
  64 *((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
  65 #define ASC_INTERRUPTS_CLEAR(X)   \
  66 *((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
  67
  68 /* CLC register's bits and bitfields */
  69 #define ASCCLC_DISR        0x00000001
  70 #define ASCCLC_DISS        0x00000002
  71 #define ASCCLC_RMCMASK     0x0000FF00
  72 #define ASCCLC_RMCOFFSET   8
  73
  74 /* CON register's bits and bitfields */
  75 #define ASCCON_MODEMASK 0x0000000f
  76 #define ASCCON_M_8ASYNC 0x0
  77 #define ASCCON_M_8IRDA  0x1
  78 #define ASCCON_M_7ASYNC 0x2
  79 #define ASCCON_M_7IRDA  0x3
  80 #define ASCCON_WLSMASK  0x0000000c
  81 #define ASCCON_WLSOFFSET        2
  82 #define ASCCON_WLS_8BIT 0x0
  83 #define ASCCON_WLS_7BIT 0x1
  84 #define ASCCON_PEN      0x00000010
  85 #define ASCCON_ODD      0x00000020
  86 #define ASCCON_SP       0x00000040
  87 #define ASCCON_STP      0x00000080
  88 #define ASCCON_BRS      0x00000100
  89 #define ASCCON_FDE      0x00000200
  90 #define ASCCON_ERRCLK   0x00000400
  91 #define ASCCON_EMMASK   0x00001800
  92 #define ASCCON_EMOFFSET 11
  93 #define ASCCON_EM_ECHO_OFF      0x0
  94 #define ASCCON_EM_ECHO_AB       0x1
  95 #define ASCCON_EM_ECHO_ON       0x2
  96 #define ASCCON_LB               0x00002000
  97 #define ASCCON_ACO              0x00004000
  98 #define ASCCON_R                0x00008000
  99 #define ASCCON_PAL              0x00010000
 100 #define ASCCON_FEN              0x00020000
 101 #define ASCCON_RUEN             0x00040000
 102 #define ASCCON_ROEN             0x00080000
 103 #define ASCCON_TOEN             0x00100000
 104 #define ASCCON_BEN              0x00200000
 105 #define ASCCON_TXINV            0x01000000
 106 #define ASCCON_RXINV            0x02000000
 107 #define ASCCON_TXMSB            0x04000000
 108 #define ASCCON_RXMSB            0x08000000
 109
 110 /* STATE register's bits and bitfields */
 111 #define ASCSTATE_REN            0x00000001
 112 #define ASCSTATE_PE             0x00010000
 113 #define ASCSTATE_FE             0x00020000
 114 #define ASCSTATE_RUE            0x00040000
 115 #define ASCSTATE_ROE            0x00080000
 116 #define ASCSTATE_TOE            0x00100000
 117 #define ASCSTATE_BE             0x00200000
 118 #define ASCSTATE_TXBVMASK       0x07000000
 119 #define ASCSTATE_TXBVOFFSET     24
 120 #define ASCSTATE_TXEOM          0x08000000
 121 #define ASCSTATE_RXBVMASK       0x70000000
 122 #define ASCSTATE_RXBVOFFSET     28
 123 #define ASCSTATE_RXEOM          0x80000000
 124 #define ASCSTATE_ANY    (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
 125
 126 /* WHBSTATE register's bits and bitfields */
 127 #define ASCWHBSTATE_CLRREN    0x00000001
 128 #define ASCWHBSTATE_SETREN    0x00000002
 129 #define ASCWHBSTATE_CLRPE     0x00000004
 130 #define ASCWHBSTATE_CLRFE     0x00000008
 131 #define ASCWHBSTATE_CLRRUE    0x00000010
 132 #define ASCWHBSTATE_CLRROE    0x00000020
 133 #define ASCWHBSTATE_CLRTOE    0x00000040
 134 #define ASCWHBSTATE_CLRBE     0x00000080
 135 #define ASCWHBSTATE_SETPE     0x00000100
 136 #define ASCWHBSTATE_SETFE     0x00000200
 137 #define ASCWHBSTATE_SETRUE    0x00000400
 138 #define ASCWHBSTATE_SETROE    0x00000800
 139 #define ASCWHBSTATE_SETTOE    0x00001000
 140 #define ASCWHBSTATE_SETBE     0x00002000
 141
 142 /* ABCON register's bits and bitfields */
 143 #define ASCABCON_ABEN       0x0001
 144 #define ASCABCON_AUREN      0x0002
 145 #define ASCABCON_ABSTEN     0x0004
 146 #define ASCABCON_ABDETEN    0x0008
 147 #define ASCABCON_FCDETEN    0x0010
 148
 149 /* FDV register mask, offset and bitfields*/
 150 #define ASCFDV_VALUE_MASK     0x000001FF
 151
 152 /* WHBABCON register's bits and bitfields */
 153 #define ASCWHBABCON_CLRABEN     0x0001
 154 #define ASCWHBABCON_SETABEN     0x0002
 155
 156 /* ABSTAT register's bits and bitfields */
 157 #define ASCABSTAT_FCSDET    0x0001
 158 #define ASCABSTAT_FCCDET    0x0002
 159 #define ASCABSTAT_SCSDET    0x0004
 160 #define ASCABSTAT_SCCDET    0x0008
 161 #define ASCABSTAT_DETWAIT   0x0010
 162
 163 /* WHBABSTAT register's bits and bitfields */
 164 #define ASCWHBABSTAT_CLRFCSDET  0x0001
 165 #define ASCWHBABSTAT_SETFCSDET  0x0002
 166 #define ASCWHBABSTAT_CLRFCCDET  0x0004
 167 #define ASCWHBABSTAT_SETFCCDET  0x0008
 168 #define ASCWHBABSTAT_CLRSCSDET  0x0010
 169 #define ASCWHBABSTAT_SETSCSDET  0x0020
 170 #define ASCWHBABSTAT_CLRSCCDET  0x0040
 171 #define ASCWHBABSTAT_SETSCCDET  0x0080
 172 #define ASCWHBABSTAT_CLRDETWAIT 0x0100
 173 #define ASCWHBABSTAT_SETDETWAIT 0x0200
 174
 175 /* TXFCON register's bits and bitfields */
 176 #define ASCTXFCON_TXFIFO1       0x00000400
 177 #define ASCTXFCON_TXFEN         0x0001
 178 #define ASCTXFCON_TXFFLU        0x0002
 179 #define ASCTXFCON_TXFITLMASK    0x3F00
 180 #define ASCTXFCON_TXFITLOFF     8
 181
 182 /* RXFCON register's bits and bitfields */
 183 #define ASCRXFCON_RXFIFO1       0x00000400
 184 #define ASCRXFCON_RXFEN         0x0001
 185 #define ASCRXFCON_RXFFLU        0x0002
 186 #define ASCRXFCON_RXFITLMASK    0x3F00
 187 #define ASCRXFCON_RXFITLOFF     8
 188
 189 /* FSTAT register's bits and bitfields */
 190 #define ASCFSTAT_RXFFLMASK      0x003F
 191 #define ASCFSTAT_TXFFLMASK      0x3F00
 192 #define ASCFSTAT_TXFFLOFF       8
 193
 194 #endif /* __IFXMIPS_ASC_H */