danube to ifxmips transition
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / include / asm-mips / danube / ifx_ssc.h
1 /*
2 * ifx_ssc.h defines some data sructures used in ifx_ssc.c
3 *
4 * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
5 *
6 *
7 */
8
9 #ifndef __IFX_SSC_H
10 #define __IFX_SSC_H
11 #ifdef __KERNEL__
12 #include <asm/ifxmips/ifx_ssc_defines.h>
13 #endif //__KERNEL__
14
15 #define PORT_CNT 1 // assume default value
16
17 /* symbolic constants to be used in SSC routines */
18
19 // ### TO DO: bad performance
20 #define IFX_SSC_TXFIFO_ITL 1
21 #define IFX_SSC_RXFIFO_ITL 1
22
23 struct ifx_ssc_statistics {
24 unsigned int abortErr; /* abort error */
25 unsigned int modeErr; /* master/slave mode error */
26 unsigned int txOvErr; /* TX Overflow error */
27 unsigned int txUnErr; /* TX Underrun error */
28 unsigned int rxOvErr; /* RX Overflow error */
29 unsigned int rxUnErr; /* RX Underrun error */
30 unsigned int rxBytes;
31 unsigned int txBytes;
32 };
33
34 struct ifx_ssc_hwopts {
35 unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
36 unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
37 unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
38 unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
39 unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
40 unsigned int echoMode:1; /* Echo mode */
41 unsigned int loopBack:1; /* Loopback mode */
42 unsigned int idleValue:1; /* Idle value */
43 unsigned int clockPolarity:1; /* Idle clock is high or low */
44 unsigned int clockPhase:1; /* Tx on trailing or leading edge */
45 unsigned int headingControl:1; /* LSB first or MSB first */
46 unsigned int dataWidth:6; /* from 2 up to 32 bits */
47 unsigned int masterSelect:1; /* Master or Slave mode */
48 unsigned int modeRxTx:2; /* rx/tx mode */
49 unsigned int gpoCs:8; /* choose outputs to use for chip select */
50 unsigned int gpoInv:8; /* invert GPO outputs */
51 };
52
53 struct ifx_ssc_frm_opts {
54 bool FrameEnable; // SFCON.SFEN
55 unsigned int DataLength; // SFCON.DLEN
56 unsigned int PauseLength; // SFCON.PLEN
57 unsigned int IdleData; // SFCON.IDAT
58 unsigned int IdleClock; // SFCON.ICLK
59 bool StopAfterPause; // SFCON.STOP
60 };
61
62 struct ifx_ssc_frm_status {
63 bool DataBusy; // SFSTAT.DBSY
64 bool PauseBusy; // SFSTAT.PBSY
65 unsigned int DataCount; // SFSTAT.DCNT
66 unsigned int PauseCount; // SFSTAT.PCNT
67 bool EnIntAfterData; // SFCON.IBEN
68 bool EnIntAfterPause; // SFCON.IAEN
69 };
70
71 typedef struct {
72 char *buf;
73 size_t len;
74 } ifx_ssc_buf_item_t;
75
76 // data structures for batch execution
77 typedef union {
78 struct {
79 bool save_options;
80 } init;
81 ifx_ssc_buf_item_t read;
82 ifx_ssc_buf_item_t write;
83 ifx_ssc_buf_item_t rd_wr;
84 unsigned int set_baudrate;
85 struct ifx_ssc_frm_opts set_frm;
86 unsigned int set_gpo;
87 struct ifx_ssc_hwopts set_hwopts;
88 } ifx_ssc_batch_cmd_param;
89
90 struct ifx_ssc_batch_list {
91 unsigned int cmd;
92 ifx_ssc_batch_cmd_param cmd_param;
93 struct ifx_ssc_batch_list *next;
94 };
95
96 #ifdef __KERNEL__
97 #define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
98
99 struct ifx_ssc_port {
100 unsigned long mapbase;
101 struct ifx_ssc_hwopts opts;
102 struct ifx_ssc_statistics stats;
103 struct ifx_ssc_frm_status frm_status;
104 struct ifx_ssc_frm_opts frm_opts;
105 /* wait queue for ifx_ssc_read() */
106 wait_queue_head_t rwait, pwait;
107 int port_nr;
108 char port_is_open; /* exclusive open - boolean */
109 // int no_of_bits; /* number of _valid_ bits */
110 // int elem_size; /* shift for element (no of bytes)*/
111 /* buffer and pointers to the read/write position */
112 char *rxbuf; /* buffer for RX */
113 char *rxbuf_end; /* buffer end pointer for RX */
114 volatile char *rxbuf_ptr; /* buffer write pointer for RX */
115 char *txbuf; /* buffer for TX */
116 char *txbuf_end; /* buffer end pointer for TX */
117 volatile char *txbuf_ptr; /* buffer read pointer for TX */
118 unsigned int baud;
119 /* each channel has its own interrupts */
120 /* (transmit/receive/error/frame) */
121 unsigned int txirq, rxirq, errirq, frmirq;
122 };
123 /* default values for SSC configuration */
124 // values of CON
125 #define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
126 #define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
127 #define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
128 #define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
129 #define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
130 #define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
131 #define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
132 #define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
133 #define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
134 #define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
135 #define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
136 #define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
137 #define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
138 #define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
139 // other values
140 #define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
141 #ifdef CONFIG_USE_EMULATOR
142 #define IFX_SSC_DEF_BAUDRATE 10000
143 #else
144 #define IFX_SSC_DEF_BAUDRATE 2000000
145 #endif
146 #define IFX_SSC_DEF_RMC 0x10
147
148 #define IFX_SSC_DEF_TXFIFO_FL 8
149 #define IFX_SSC_DEF_RXFIFO_FL 1
150
151 #if 1 //TODO
152 #define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
153 #define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
154 #else
155 #error "what is ur Chip Select???"
156 #endif
157 #define IFX_SSC_DEF_SFCON 0 /* no serial framing */
158 #if 0
159 #define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
160 IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
161 #endif
162 #define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
163 IFX_SSC_R_BIT | IFX_SSC_E_BIT
164 #endif /* __KERNEL__ */
165
166 // batch execution commands
167 #define IFX_SSC_BATCH_CMD_INIT 1
168 #define IFX_SSC_BATCH_CMD_READ 2
169 #define IFX_SSC_BATCH_CMD_WRITE 3
170 #define IFX_SSC_BATCH_CMD_RD_WR 4
171 #define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
172 #define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
173 #define IFX_SSC_BATCH_CMD_SET_FRM 7
174 #define IFX_SSC_BATCH_CMD_SET_GPO 8
175 #define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
176 //#define IFX_SSC_BATCH_CMD_
177 //#define IFX_SSC_BATCH_CMD_
178 #define IFX_SSC_BATCH_CMD_END_EXEC 0
179
180 /* Macros to configure SSC hardware */
181 /* headingControl: */
182 #define IFX_SSC_LSB_FIRST 0
183 #define IFX_SSC_MSB_FIRST 1
184 /* dataWidth: */
185 #define IFX_SSC_MIN_DATA_WIDTH 2
186 #define IFX_SSC_MAX_DATA_WIDTH 32
187 /* master/slave mode select */
188 #define IFX_SSC_MASTER_MODE 1
189 #define IFX_SSC_SLAVE_MODE 0
190 /* rx/tx mode */
191 // ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
192 #define IFX_SSC_MODE_RXTX 0
193 #define IFX_SSC_MODE_RX 1
194 #define IFX_SSC_MODE_TX 2
195 #define IFX_SSC_MODE_OFF 3
196 #define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
197
198 /* GPO values */
199 #define IFX_SSC_MAX_GPO_OUT 7
200
201 #define IFX_SSC_RXREQ_BLOCK_SIZE 32768
202
203 /***********************/
204 /* defines for ioctl's */
205 /***********************/
206 #define IFX_SSC_IOCTL_MAGIC 'S'
207 /* read out the statistics */
208 #define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
209 /* clear the statistics */
210 #define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
211 /* set the baudrate */
212 #define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
213 /* get the current baudrate */
214 #define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
215 /* set hardware options */
216 #define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
217 /* get the current hardware options */
218 #define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
219 /* set transmission mode */
220 #define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
221 /* get the current transmission mode */
222 #define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
223 /* abort transmission */
224 #define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
225 #define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
226
227 /* set general purpose outputs */
228 #define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
229 /* clear general purpose outputs */
230 #define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
231 /* get general purpose outputs */
232 #define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
233
234 /*** serial framing ***/
235 /* get status of serial framing */
236 #define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
237 /* get counter reload values and control bits */
238 #define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
239 /* set counter reload values and control bits */
240 #define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
241
242 /*** batch execution ***/
243 /* do batch execution */
244 #define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
245
246 #ifdef __KERNEL__
247 // routines from ifx_ssc.c
248 // ### TO DO
249 /* kernel interface for read and write */
250 ssize_t ifx_ssc_kread (int, char *, size_t);
251 ssize_t ifx_ssc_kwrite (int, const char *, size_t);
252
253 #ifdef CONFIG_IFX_VP_KERNEL_TEST
254 void ifx_ssc_tc (void);
255 #endif // CONFIG_IFX_VP_KERNEL_TEST
256
257 #endif //__KERNEL__
258 #endif // __IFX_SSC_H