adds ifxmips, uboot-ifxmips and removes etrax from 8.09 branch
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / include / asm-mips / ifxmips / ifx_ssc_defines.h
1 #ifndef IFX_SSC_DEFINES_H
2 #define IFX_SSC_DEFINES_H
3
4 #include "ifx_peripheral_definitions.h"
5
6 /* maximum SSC FIFO size */
7 #define IFX_SSC_MAX_FIFO_SIZE 32
8
9 /* register map of SSC */
10
11 /* address of the Clock Control Register of the SSC */
12 #define IFX_SSC_CLC 0x00000000
13 /* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
14 bit 1 is hardware modified*/
15 #define IFX_SSC_CLC_readmask 0x00FFFFEF
16 #define IFX_SSC_CLC_writemask 0x00FFFF3D
17 #define IFX_SSC_CLC_hwmask 0x00000002
18 #define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
19
20 /* address of Port Input Select Register of the SSC */
21 #define IFX_SSC_PISEL 0x00000004
22 /* IFX_SSC_PISEL register is significant in lowest three bits only */
23 #define IFX_SSC_PISEL_readmask 0x00000007
24 #define IFX_SSC_PISEL_writemask 0x00000007
25 #define IFX_SSC_PISEL_hwmask 0x00000000
26 #define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
27
28 /* address of Identification Register of the SSC */
29 #define IFX_SSC_ID 0x00000008
30 /* IFX_SSC_ID register is significant in no bit */
31 #define IFX_SSC_ID_readmask 0x0000FF3F
32 #define IFX_SSC_ID_writemask 0x00000000
33 #define IFX_SSC_ID_hwmask 0x00000000
34 #define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
35
36 /* address of the Control Register of the SSC */
37 #define IFX_SSC_CON 0x00000010
38 /* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
39 #define IFX_SSC_CON_readmask 0x01DF1FFF
40 #define IFX_SSC_CON_writemask 0x01DF1FFF
41 #define IFX_SSC_CON_hwmask 0x00000000
42 #define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
43
44 /* address of the Status Register of the SSC */
45 #define IFX_SSC_STATE 0x00000014
46 /* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
47 all bits except 1:0 are hardware modified */
48 #define IFX_SSC_STATE_readmask 0x771F3F87
49 #define IFX_SSC_STATE_writemask 0x00000000
50 #define IFX_SSC_STATE_hwmask 0x771F3F84
51 #define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
52
53 /* address of the Write Hardware Modified Control Register Bits of the SSC */
54 #define IFX_SSC_WHBSTATE 0x00000018
55 /* IFX_SSC_WHBSTATE register is write only */
56 #define IFX_SSC_WHBSTATE_readmask 0x00000000
57 #define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
58 #define IFX_SSC_WHBSTATE_hwmask 0x00000000
59 #define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
60
61 /* address of the Baudrate Timer Reload Register of the SSC */
62 #define IFX_SSC_BR 0x00000040
63 /* IFX_SSC_BR register is significant in bit 15 downto 0*/
64 #define IFX_SSC_BR_readmask 0x0000FFFF
65 #define IFX_SSC_BR_writemask 0x0000FFFF
66 #define IFX_SSC_BR_hwmask 0x00000000
67 #define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
68
69 /* address of the Baudrate Timer Status Register of the SSC */
70 #define IFX_SSC_BRSTAT 0x00000044
71 /* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
72 #define IFX_SSC_BRSTAT_readmask 0x0000FFFF
73 #define IFX_SSC_BRSTAT_writemask 0x00000000
74 #define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
75 #define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
76
77 /* address of the Transmitter Buffer Register of the SSC */
78 #define IFX_SSC_TB 0x00000020
79 /* IFX_SSC_TB register is significant in bit 31 downto 0*/
80 #define IFX_SSC_TB_readmask 0xFFFFFFFF
81 #define IFX_SSC_TB_writemask 0xFFFFFFFF
82 #define IFX_SSC_TB_hwmask 0x00000000
83 #define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
84
85 /* address of the Reciver Buffer Register of the SSC */
86 #define IFX_SSC_RB 0x00000024
87 /* IFX_SSC_RB register is significant in no bits*/
88 #define IFX_SSC_RB_readmask 0xFFFFFFFF
89 #define IFX_SSC_RB_writemask 0x00000000
90 #define IFX_SSC_RB_hwmask 0xFFFFFFFF
91 #define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
92
93 /* address of the Receive FIFO Control Register of the SSC */
94 #define IFX_SSC_RXFCON 0x00000030
95 /* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
96 #define IFX_SSC_RXFCON_readmask 0x00003F03
97 #define IFX_SSC_RXFCON_writemask 0x00003F03
98 #define IFX_SSC_RXFCON_hwmask 0x00000000
99 #define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
100
101 /* address of the Transmit FIFO Control Register of the SSC */
102 #define IFX_SSC_TXFCON 0x00000034
103 /* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
104 #define IFX_SSC_TXFCON_readmask 0x00003F03
105 #define IFX_SSC_TXFCON_writemask 0x00003F03
106 #define IFX_SSC_TXFCON_hwmask 0x00000000
107 #define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
108
109 /* address of the FIFO Status Register of the SSC */
110 #define IFX_SSC_FSTAT 0x00000038
111 /* IFX_SSC_FSTAT register is significant in no bit*/
112 #define IFX_SSC_FSTAT_readmask 0x00003F3F
113 #define IFX_SSC_FSTAT_writemask 0x00000000
114 #define IFX_SSC_FSTAT_hwmask 0x00003F3F
115 #define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
116
117 /* address of the Data Frame Control register of the SSC */
118 #define IFX_SSC_SFCON 0x00000060
119 #define IFX_SSC_SFCON_readmask 0xFFDFFFFD
120 #define IFX_SSC_SFCON_writemask 0xFFDFFFFD
121 #define IFX_SSC_SFCON_hwmask 0x00000000
122 #define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
123
124 /* address of the Data Frame Status register of the SSC */
125 #define IFX_SSC_SFSTAT 0x00000064
126 #define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
127 #define IFX_SSC_SFSTAT_writemask 0x00000000
128 #define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
129 #define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
130
131 /* address of the General Purpose Output Control register of the SSC */
132 #define IFX_SSC_GPOCON 0x00000070
133 #define IFX_SSC_GPOCON_readmask 0x0000FFFF
134 #define IFX_SSC_GPOCON_writemask 0x0000FFFF
135 #define IFX_SSC_GPOCON_hwmask 0x00000000
136 #define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
137
138 /* address of the General Purpose Output Status register of the SSC */
139 #define IFX_SSC_GPOSTAT 0x00000074
140 #define IFX_SSC_GPOSTAT_readmask 0x000000FF
141 #define IFX_SSC_GPOSTAT_writemask 0x00000000
142 #define IFX_SSC_GPOSTAT_hwmask 0x00000000
143 #define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
144
145 /* address of the Force GPO Status register of the SSC */
146 #define IFX_SSC_WHBGPOSTAT 0x00000078
147 #define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
148 #define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
149 #define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
150 #define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
151
152 /* address of the Receive Request Register of the SSC */
153 #define IFX_SSC_RXREQ 0x00000080
154 #define IFX_SSC_RXREQ_readmask 0x0000FFFF
155 #define IFX_SSC_RXREQ_writemask 0x0000FFFF
156 #define IFX_SSC_RXREQ_hwmask 0x00000000
157 #define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
158
159 /* address of the Receive Count Register of the SSC */
160 #define IFX_SSC_RXCNT 0x00000084
161 #define IFX_SSC_RXCNT_readmask 0x0000FFFF
162 #define IFX_SSC_RXCNT_writemask 0x00000000
163 #define IFX_SSC_RXCNT_hwmask 0x0000FFFF
164 #define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
165
166 /* address of the DMA Configuration Register of the SSC */
167 #define IFX_SSC_DMACON 0x000000EC
168 #define IFX_SSC_DMACON_readmask 0x0000FFFF
169 #define IFX_SSC_DMACON_writemask 0x00000000
170 #define IFX_SSC_DMACON_hwmask 0x0000FFFF
171 #define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
172
173 //------------------------------------------------------
174 // interrupt register for enabling interrupts, mask register of irq_reg
175 #define IFX_SSC_IRN_EN 0xF4
176 // read/write
177 #define IFX_SSC_IRN_EN_readmask 0x0000000F
178 #define IFX_SSC_IRN_EN_writemask 0x0000000F
179 #define IFX_SSC_IRN_EN_hwmask 0x00000000
180 #define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
181
182 // interrupt register for accessing interrupts
183 #define IFX_SSC_IRN_CR 0xF8
184 // read/write
185 #define IFX_SSC_IRN_CR_readmask 0x0000000F
186 #define IFX_SSC_IRN_CR_writemask 0x0000000F
187 #define IFX_SSC_IRN_CR_hwmask 0x0000000F
188 #define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
189
190 // interrupt register for stimulating interrupts
191 #define IFX_SSC_IRN_ICR 0xFC
192 // read/write
193 #define IFX_SSC_IRN_ICR_readmask 0x0000000F
194 #define IFX_SSC_IRN_ICR_writemask 0x0000000F
195 #define IFX_SSC_IRN_ICR_hwmask 0x00000000
196 #define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
197
198 //---------------------------------------------------------------------
199 // Number of IRQs and bitposition of IRQ
200 #define IFX_SSC_NUM_IRQ 4
201 #define IFX_SSC_T_BIT 0x00000001
202 #define IFX_SSC_R_BIT 0x00000002
203 #define IFX_SSC_E_BIT 0x00000004
204 #define IFX_SSC_F_BIT 0x00000008
205
206 /* bit masks for SSC registers */
207
208 /* ID register */
209 #define IFX_SSC_PERID_REV_MASK 0x0000001F
210 #define IFX_SSC_PERID_CFG_MASK 0x00000020
211 #define IFX_SSC_PERID_ID_MASK 0x0000FF00
212 #define IFX_SSC_PERID_REV_OFFSET 0
213 #define IFX_SSC_PERID_CFG_OFFSET 5
214 #define IFX_SSC_PERID_ID_OFFSET 8
215 #define IFX_SSC_PERID_ID 0x45
216 #define IFX_SSC_PERID_DMA_ON 0x00000020
217 #define IFX_SSC_PERID_RXFS_MASK 0x003F0000
218 #define IFX_SSC_PERID_RXFS_OFFSET 16
219 #define IFX_SSC_PERID_TXFS_MASK 0x3F000000
220 #define IFX_SSC_PERID_TXFS_OFFSET 24
221
222 /* PISEL register */
223 #define IFX_SSC_PISEL_MASTER_IN_A 0x0000
224 #define IFX_SSC_PISEL_MASTER_IN_B 0x0001
225 #define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
226 #define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
227 #define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
228 #define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
229
230 /* IFX_SSC_CON register */
231 #define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
232 #define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
233 #define IFX_SSC_CON_IDLE_HIGH 0x00800000
234 #define IFX_SSC_CON_IDLE_LOW 0x00000000
235 #define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
236 #define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
237 #define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
238 #define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
239 #define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
240
241 #define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
242 #define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
243
244 #define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
245 #define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
246 #define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
247 #define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
248 #define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
249 #define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
250 #define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
251 #define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
252 #define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
253 #define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
254 #define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
255 #define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
256
257 #define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
258 #define IFX_SSC_CON_NO_LOOPBACK 0x00000000
259 #define IFX_SSC_CON_HALF_DUPLEX 0x00000080
260 #define IFX_SSC_CON_FULL_DUPLEX 0x00000000
261 #define IFX_SSC_CON_CLOCK_FALL 0x00000040
262 #define IFX_SSC_CON_CLOCK_RISE 0x00000000
263 #define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
264 #define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
265 #define IFX_SSC_CON_MSB_FIRST 0x00000010
266 #define IFX_SSC_CON_LSB_FIRST 0x00000000
267 #define IFX_SSC_CON_ENABLE_CSB 0x00000008
268 #define IFX_SSC_CON_DISABLE_CSB 0x00000000
269 #define IFX_SSC_CON_INVERT_CSB 0x00000004
270 #define IFX_SSC_CON_TRUE_CSB 0x00000000
271 #define IFX_SSC_CON_RX_OFF 0x00000002
272 #define IFX_SSC_CON_RX_ON 0x00000000
273 #define IFX_SSC_CON_TX_OFF 0x00000001
274 #define IFX_SSC_CON_TX_ON 0x00000000
275
276 /* IFX_SSC_STATE register */
277 #define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
278 #define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
279 #define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
280 #define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
281 #define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
282 #define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
283 #define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
284 #define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
285 #define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
286 #define IFX_SSC_STATE_BUSY 0x00002000
287 #define IFX_SSC_STATE_RX_UFL 0x00001000
288 #define IFX_SSC_STATE_TX_UFL 0x00000800
289 #define IFX_SSC_STATE_ABORT_ERR 0x00000400
290 #define IFX_SSC_STATE_RX_OFL 0x00000200
291 #define IFX_SSC_STATE_TX_OFL 0x00000100
292 #define IFX_SSC_STATE_MODE_ERR 0x00000080
293 #define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
294 #define IFX_SSC_STATE_IS_MASTER 0x00000002
295 #define IFX_SSC_STATE_IS_ENABLED 0x00000001
296
297 /* WHBSTATE register */
298 #define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
299 #define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
300 #define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
301
302 #define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
303 #define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
304 #define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
305
306 #define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
307 #define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
308
309 #define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
310 #define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
311
312 #define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
313 #define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
314
315 #define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
316 #define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
317
318 #define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
319 #define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
320 #define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
321 #define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
322 #define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
323 #define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
324 #define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
325 #define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
326 #define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
327 #define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
328
329 /* BR register */
330 #define IFX_SSC_BR_BAUDRATE_OFFSET 0
331 #define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
332
333 /* BR_STAT register */
334 #define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
335 #define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
336
337 /* TB register */
338 #define IFX_SSC_TB_DATA_OFFSET 0
339 #define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
340
341 /* RB register */
342 #define IFX_SSC_RB_DATA_OFFSET 0
343 #define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
344
345 /* RXFCON and TXFCON registers */
346 #define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
347 #define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
348 #define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
349 #define IFX_SSC_XFCON_ITL_MASK 0x00003F00
350 #define IFX_SSC_XFCON_ITL_OFFSET 8
351
352 /* FSTAT register */
353 #define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
354 #define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
355 #define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
356 #define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
357
358 /* GPOCON register */
359 #define IFX_SSC_GPOCON_INVOUT0_POS 0
360 #define IFX_SSC_GPOCON_INV_OUT0 0x00000001
361 #define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
362 #define IFX_SSC_GPOCON_INVOUT1_POS 1
363 #define IFX_SSC_GPOCON_INV_OUT1 0x00000002
364 #define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
365 #define IFX_SSC_GPOCON_INVOUT2_POS 2
366 #define IFX_SSC_GPOCON_INV_OUT2 0x00000003
367 #define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
368 #define IFX_SSC_GPOCON_INVOUT3_POS 3
369 #define IFX_SSC_GPOCON_INV_OUT3 0x00000008
370 #define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
371 #define IFX_SSC_GPOCON_INVOUT4_POS 4
372 #define IFX_SSC_GPOCON_INV_OUT4 0x00000010
373 #define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
374 #define IFX_SSC_GPOCON_INVOUT5_POS 5
375 #define IFX_SSC_GPOCON_INV_OUT5 0x00000020
376 #define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
377 #define IFX_SSC_GPOCON_INVOUT6_POS 6
378 #define IFX_SSC_GPOCON_INV_OUT6 0x00000040
379 #define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
380 #define IFX_SSC_GPOCON_INVOUT7_POS 7
381 #define IFX_SSC_GPOCON_INV_OUT7 0x00000080
382 #define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
383 #define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
384 #define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
385
386 #define IFX_SSC_GPOCON_ISCSB0_POS 8
387 #define IFX_SSC_GPOCON_IS_CSB0 0x00000100
388 #define IFX_SSC_GPOCON_IS_GPO0 0x00000000
389 #define IFX_SSC_GPOCON_ISCSB1_POS 9
390 #define IFX_SSC_GPOCON_IS_CSB1 0x00000200
391 #define IFX_SSC_GPOCON_IS_GPO1 0x00000000
392 #define IFX_SSC_GPOCON_ISCSB2_POS 10
393 #define IFX_SSC_GPOCON_IS_CSB2 0x00000400
394 #define IFX_SSC_GPOCON_IS_GPO2 0x00000000
395 #define IFX_SSC_GPOCON_ISCSB3_POS 11
396 #define IFX_SSC_GPOCON_IS_CSB3 0x00000800
397 #define IFX_SSC_GPOCON_IS_GPO3 0x00000000
398 #define IFX_SSC_GPOCON_ISCSB4_POS 12
399 #define IFX_SSC_GPOCON_IS_CSB4 0x00001000
400 #define IFX_SSC_GPOCON_IS_GPO4 0x00000000
401 #define IFX_SSC_GPOCON_ISCSB5_POS 13
402 #define IFX_SSC_GPOCON_IS_CSB5 0x00002000
403 #define IFX_SSC_GPOCON_IS_GPO5 0x00000000
404 #define IFX_SSC_GPOCON_ISCSB6_POS 14
405 #define IFX_SSC_GPOCON_IS_CSB6 0x00004000
406 #define IFX_SSC_GPOCON_IS_GPO6 0x00000000
407 #define IFX_SSC_GPOCON_ISCSB7_POS 15
408 #define IFX_SSC_GPOCON_IS_CSB7 0x00008000
409 #define IFX_SSC_GPOCON_IS_GPO7 0x00000000
410 #define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
411 #define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
412
413 /* GPOSTAT register */
414 #define IFX_SSC_GPOSTAT_OUT0 0x00000001
415 #define IFX_SSC_GPOSTAT_OUT1 0x00000002
416 #define IFX_SSC_GPOSTAT_OUT2 0x00000004
417 #define IFX_SSC_GPOSTAT_OUT3 0x00000008
418 #define IFX_SSC_GPOSTAT_OUT4 0x00000010
419 #define IFX_SSC_GPOSTAT_OUT5 0x00000020
420 #define IFX_SSC_GPOSTAT_OUT6 0x00000040
421 #define IFX_SSC_GPOSTAT_OUT7 0x00000080
422 #define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
423
424 /* WHBGPOSTAT register */
425 #define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
426 #define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
427 #define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
428 #define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
429 #define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
430 #define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
431 #define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
432 #define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
433 #define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
434 #define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
435 #define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
436 #define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
437 #define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
438 #define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
439 #define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
440 #define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
441 #define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
442
443 #define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
444 #define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
445 #define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
446 #define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
447 #define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
448 #define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
449 #define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
450 #define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
451
452 #define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
453 #define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
454 #define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
455 #define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
456 #define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
457 #define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
458 #define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
459 #define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
460 #define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
461 #define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
462 #define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
463 #define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
464 #define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
465 #define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
466 #define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
467 #define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
468 #define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
469
470 /* SFCON register */
471 #define IFX_SSC_SFCON_SF_ENABLE 0x00000001
472 #define IFX_SSC_SFCON_SF_DISABLE 0x00000000
473 #define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
474 #define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
475 #define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
476 #define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
477 #define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
478 #define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
479 #define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
480 #define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
481 #define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
482 #define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
483 #define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
484 #define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
485 #define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
486 #define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
487 #define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
488 #define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
489 #define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
490 #define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
491 #define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
492 #define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
493 #define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
494 #define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
495 #define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
496
497 #define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
498 #define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
499 #define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
500 #define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
501
502 /* SFSTAT register */
503 #define IFX_SSC_SFSTAT_IN_DATA 0x00000001
504 #define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
505 #define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
506 #define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
507 #define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
508 #define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
509
510 #define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
511 #define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
512
513 /* RXREQ register */
514 #define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
515 #define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
516
517 /* RXCNT register */
518 #define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
519 #define IFX_SSC_RXCNT_TODO_OFFSET 0
520
521 /* DMACON register */
522 #define IFX_SSC_DMACON_RXON 0x00000001
523 #define IFX_SSC_DMACON_RXOFF 0x00000000
524 #define IFX_SSC_DMACON_TXON 0x00000002
525 #define IFX_SSC_DMACON_TXOFF 0x00000000
526 #define IFX_SSC_DMACON_DMAON 0x00000003
527 #define IFX_SSC_DMACON_DMAOFF 0x00000000
528 #define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
529 #define IFX_SSC_DMACON_CLASS_OFFSET 2
530
531 /* register access macros */
532 #define ifx_ssc_fstat_received_words(status) (status & 0x003F)
533 #define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
534
535 #define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
536 #define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
537 #define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
538 #define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
539 #define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
540 #define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
541 #define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
542 #define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
543
544 #define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
545 #define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
546
547 #endif