adds ifxmips, uboot-ifxmips and removes etrax from 8.09 branch
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / include / asm-mips / ifxmips / ifxmips.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2005 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 */
19 #ifndef _IFXMIPS_H__
20 #define _IFXMIPS_H__
21
22 #define ifxmips_r32(reg) __raw_readl(reg)
23 #define ifxmips_w32(val,reg) __raw_writel(val,reg)
24 #define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
25
26 /*------------ GENERAL */
27
28 #define BOARD_SYSTEM_TYPE "IFXMIPS"
29
30 #define IOPORT_RESOURCE_START 0x10000000
31 #define IOPORT_RESOURCE_END 0xffffffff
32 #define IOMEM_RESOURCE_START 0x10000000
33 #define IOMEM_RESOURCE_END 0xffffffff
34
35 #define IFXMIPS_FLASH_START 0x10000000
36 #define IFXMIPS_FLASH_MAX 0x2000000
37
38
39 /*------------ ASC1 */
40
41 #define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)
42 #define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)
43
44 #define IFXMIPS_ASC_FSTAT 0x0048
45 #define IFXMIPS_ASC_TBUF 0x0020
46 #define IFXMIPS_ASC_WHBSTATE 0x0018
47 #define IFXMIPS_ASC_RBUF 0x0024
48 #define IFXMIPS_ASC_STATE 0x0014
49 #define IFXMIPS_ASC_IRNCR 0x00F8
50 #define IFXMIPS_ASC_CLC 0x0000
51 #define IFXMIPS_ASC_PISEL 0x0004
52 #define IFXMIPS_ASC_TXFCON 0x0044
53 #define IFXMIPS_ASC_RXFCON 0x0040
54 #define IFXMIPS_ASC_CON 0x0010
55 #define IFXMIPS_ASC_BG 0x0050
56 #define IFXMIPS_ASC_IRNREN 0x00F4
57
58 #define IFXMIPS_ASC_CLC_DISS 0x2
59 #define ASC_IRNREN_RX_BUF 0x8
60 #define ASC_IRNREN_TX_BUF 0x4
61 #define ASC_IRNREN_ERR 0x2
62 #define ASC_IRNREN_TX 0x1
63 #define ASC_IRNCR_TIR 0x4
64 #define ASC_IRNCR_RIR 0x2
65 #define ASC_IRNCR_EIR 0x4
66 #define ASCOPT_CSIZE 0x3
67 #define ASCOPT_CS7 0x1
68 #define ASCOPT_CS8 0x2
69 #define ASCOPT_PARENB 0x4
70 #define ASCOPT_STOPB 0x8
71 #define ASCOPT_PARODD 0x0
72 #define ASCOPT_CREAD 0x20
73 #define TXFIFO_FL 1
74 #define RXFIFO_FL 1
75 #define TXFIFO_FULL 16
76 #define ASCCLC_RMCMASK 0x0000FF00
77 #define ASCCLC_RMCOFFSET 8
78 #define ASCCON_M_8ASYNC 0x0
79 #define ASCCON_M_7ASYNC 0x2
80 #define ASCCON_ODD 0x00000020
81 #define ASCCON_STP 0x00000080
82 #define ASCCON_BRS 0x00000100
83 #define ASCCON_FDE 0x00000200
84 #define ASCCON_R 0x00008000
85 #define ASCCON_FEN 0x00020000
86 #define ASCCON_ROEN 0x00080000
87 #define ASCCON_TOEN 0x00100000
88 #define ASCSTATE_PE 0x00010000
89 #define ASCSTATE_FE 0x00020000
90 #define ASCSTATE_ROE 0x00080000
91 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
92 #define ASCWHBSTATE_CLRREN 0x00000001
93 #define ASCWHBSTATE_SETREN 0x00000002
94 #define ASCWHBSTATE_CLRPE 0x00000004
95 #define ASCWHBSTATE_CLRFE 0x00000008
96 #define ASCWHBSTATE_CLRROE 0x00000020
97 #define ASCTXFCON_TXFEN 0x0001
98 #define ASCTXFCON_TXFFLU 0x0002
99 #define ASCTXFCON_TXFITLMASK 0x3F00
100 #define ASCTXFCON_TXFITLOFF 8
101 #define ASCRXFCON_RXFEN 0x0001
102 #define ASCRXFCON_RXFFLU 0x0002
103 #define ASCRXFCON_RXFITLMASK 0x3F00
104 #define ASCRXFCON_RXFITLOFF 8
105 #define ASCFSTAT_RXFFLMASK 0x003F
106 #define ASCFSTAT_TXFFLMASK 0x3F00
107 #define ASCFSTAT_TXFFLOFF 8
108
109
110
111 /*------------ RCU */
112 #define IFXMIPS_RCU_BASE_ADDR 0xBF203000
113
114 /* reset request */
115 #define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
116 #define IFXMIPS_RCU_RST_CPU1 (1 << 3)
117 #define IFXMIPS_RCU_RST_ALL 0x40000000
118
119 #define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
120 #define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
121 #define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)
122
123
124 /*------------ GPTU */
125
126 #define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
127
128 /* clock control register */
129 #define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
130
131 /* captur reload register */
132 #define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
133
134 /* timer 6 control register */
135 #define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
136
137
138 /*------------ EBU */
139
140 #define IFXMIPS_EBU_BASE_ADDR 0xBE105300
141
142 /* bus configuration register */
143 #define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
144 #define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
145 #define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
146 #define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
147
148
149 /*------------ CGU */
150 #define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
151 #define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
152 #define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
153 #define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
154 #define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
155 #define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
156 #define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
157 #define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
158 #define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
159 #define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
160 #define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
161 #define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
162 #define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
163 #define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
164 #define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
165
166 /* clock mux */
167 #define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
168 #define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
169 #define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
170
171 #define CLOCK_60M 60000000
172 #define CLOCK_83M 83333333
173 #define CLOCK_111M 111111111
174 #define CLOCK_133M 133333333
175 #define CLOCK_167M 166666667
176 #define CLOCK_333M 333333333
177
178
179 /*------------ CGU */
180
181 #define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
182
183 #define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
184 #define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
185
186
187 /*------------ ICU */
188
189 #define IFXMIPS_ICU_BASE_ADDR 0xBF880200
190
191
192 #define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
193 #define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
194 #define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
195 #define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
196 #define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
197
198 #define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
199 #define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
200 #define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
201
202 #define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
203
204
205 /*------------ ETOP */
206
207 #define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
208
209 #define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
210
211 #define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
212 #define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
213
214 #define MII_MODE 1
215 #define REV_MII_MODE 2
216
217 /* mdio access */
218 #define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
219 #define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
220
221 #define MDIO_ACC_REQUEST 0x80000000
222 #define MDIO_ACC_READ 0x40000000
223 #define MDIO_ACC_ADDR_MASK 0x1f
224 #define MDIO_ACC_ADDR_OFFSET 0x15
225 #define MDIO_ACC_REG_MASK 0xff
226 #define MDIO_ACC_REG_OFFSET 0x10
227 #define MDIO_ACC_VAL_MASK 0xffff
228
229 /* configuration */
230 #define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
231
232 #define PPE32_MII_MASK 0xfffffffc
233 #define PPE32_MII_NORMAL 0x8
234 #define PPE32_MII_REVERSE 0xe
235
236 /* packet length */
237 #define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
238
239 #define PPE32_PLEN_OVER 0x5ee
240 #define PPE32_PLEN_UNDER 0x400000
241
242 /* enet */
243 #define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
244
245 #define PPE32_CGEN 0x800
246
247
248 /*------------ DMA */
249 #define IFXMIPS_DMA_BASE_ADDR 0xBE104100
250
251 #define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18))
252 #define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
253 #define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
254 #define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
255 #define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28))
256 #define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
257 #define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
258 #define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
259 #define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
260 #define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
261 #define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
262
263
264 /*------------ PCI */
265 #define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
266
267 #define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
268 #define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
269 #define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
270 #define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
271 #define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
272 #define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
273 #define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
274 #define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
275 #define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
276 #define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
277 #define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
278 #define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
279 #define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
280 #define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
281 #define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
282 #define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
283 #define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
284 #define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
285 #define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
286
287 #define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
288
289 #define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
290
291 #define PCI_MASTER0_REQ_MASK_2BITS 8
292 #define PCI_MASTER1_REQ_MASK_2BITS 10
293 #define PCI_MASTER2_REQ_MASK_2BITS 12
294 #define INTERNAL_ARB_ENABLE_BIT 0
295
296
297 /*------------ WDT */
298
299 #define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
300
301 #define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
302 #define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
303
304
305 /*------------ LED */
306
307 #define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
308 #define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
309 #define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
310 #define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
311 #define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
312 #define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
313
314 #define LED_CON0_SWU (1 << 31)
315 #define LED_CON0_AD1 (1 << 25)
316 #define LED_CON0_AD0 (1 << 24)
317
318 #define IFXMIPS_LED_2HZ (0)
319 #define IFXMIPS_LED_4HZ (1 << 23)
320 #define IFXMIPS_LED_8HZ (2 << 23)
321 #define IFXMIPS_LED_10HZ (3 << 23)
322 #define IFXMIPS_LED_MASK (0xf << 23)
323
324 #define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
325 #define IFXMIPS_LED_UPD_MASK (3 << 30)
326 #define IFXMIPS_LED_ADSL_SRC (3 << 24)
327
328 #define IFXMIPS_LED_GROUP0 (1 << 0)
329 #define IFXMIPS_LED_GROUP1 (1 << 1)
330 #define IFXMIPS_LED_GROUP2 (1 << 2)
331
332 #define IFXMIPS_LED_RISING 0
333 #define IFXMIPS_LED_FALLING (1 << 26)
334 #define IFXMIPS_LED_EDGE_MASK (1 << 26)
335
336
337 /*------------ GPIO */
338
339 #define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
340
341 #define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
342 #define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
343 #define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
344 #define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
345 #define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
346 #define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
347 #define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
348 #define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
349 #define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
350 #define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
351 #define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
352 #define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
353 #define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
354 #define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
355 #define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
356 #define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
357 #define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
358 #define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
359
360
361 /*------------ SSC */
362
363 #define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
364
365
366 #define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
367 #define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
368 #define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
369 #define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
370 #define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
371 #define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
372 #define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
373 #define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
374 #define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
375 #define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
376 #define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
377 #define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
378 #define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
379 #define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
380 #define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
381 #define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
382 #define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
383 #define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
384 #define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
385 #define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
386
387
388 /*------------ MEI */
389
390 #define IFXMIPS_MEI_BASE_ADDR (0xBE116000)
391
392 #define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
393 #define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
394 #define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
395 #define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
396 #define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
397 #define MEI_MAX_WAIT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0014))
398 #define MEI_TO_ARC_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0018))
399 #define ARC_TO_MEI_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x001C))
400 #define ARC_TO_MEI_INT_MASK ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0020))
401 #define MEI_DEBUG_WAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0024))
402 #define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
403 #define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
404 #define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
405 #define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
406 #define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
407 #define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
408 #define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
409 #define MEI_BIST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0044))
410 #define MEI_BIST_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0048))
411 #define MEI_XDATA_BASE_SH ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x004c))
412 #define MEI_XDATA_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0050))
413 #define MEI_XMEM_BAR_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
414 #define MEI_XMEM_BAR0 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
415 #define MEI_XMEM_BAR1 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0058))
416 #define MEI_XMEM_BAR2 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x005C))
417 #define MEI_XMEM_BAR3 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0060))
418 #define MEI_XMEM_BAR4 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0064))
419 #define MEI_XMEM_BAR5 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0068))
420 #define MEI_XMEM_BAR6 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x006C))
421 #define MEI_XMEM_BAR7 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0070))
422 #define MEI_XMEM_BAR8 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0074))
423 #define MEI_XMEM_BAR9 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0078))
424 #define MEI_XMEM_BAR10 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x007C))
425 #define MEI_XMEM_BAR11 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0080))
426 #define MEI_XMEM_BAR12 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0084))
427 #define MEI_XMEM_BAR13 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0088))
428 #define MEI_XMEM_BAR14 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x008C))
429 #define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
430 #define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
431
432
433 /*------------ DEU */
434
435 #define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
436 #define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
437 #define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
438
439 #define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
440 #define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
441 #define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
442 #define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
443 #define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
444 #define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
445 #define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
446 #define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
447 #define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
448 #define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
449 #define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
450 #define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
451 #define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
452 #define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
453 #define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
454 #define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
455 #define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
456 #define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
457 #define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
458 #define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
459 #define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
460 #define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
461 #define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
462 #define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
463 #define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
464 #define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
465 #define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
466 #define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
467 #define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
468 #define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
469 #define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
470 #define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
471
472 /*------------ FUSE */
473
474 #define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
475
476
477 /*------------ MPS */
478
479 #define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
480 #define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000))
481
482 #define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
483 #define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
484 #define IFXMIPS_MPS_VC1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
485 #define IFXMIPS_MPS_VC2ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
486 #define IFXMIPS_MPS_VC3ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
487 #define IFXMIPS_MPS_RVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
488 #define IFXMIPS_MPS_RVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
489 #define IFXMIPS_MPS_RVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
490 #define IFXMIPS_MPS_RVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
491 #define IFXMIPS_MPS_SVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
492 #define IFXMIPS_MPS_SVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
493 #define IFXMIPS_MPS_SVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
494 #define IFXMIPS_MPS_SVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
495 #define IFXMIPS_MPS_CVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
496 #define IFXMIPS_MPS_CVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
497 #define IFXMIPS_MPS_CVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
498 #define IFXMIPS_MPS_CVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
499 #define IFXMIPS_MPS_RAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
500 #define IFXMIPS_MPS_RAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
501 #define IFXMIPS_MPS_SAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
502 #define IFXMIPS_MPS_SAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
503 #define IFXMIPS_MPS_CAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
504 #define IFXMIPS_MPS_CAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
505 #define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
506 #define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
507
508 #define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
509 #define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
510 #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
511 #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
512 #define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
513 #define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
514
515 #endif