target/linux/imx23/patches/105-imx23-dcp.patch

   1 --- a/drivers/crypto/Kconfig
   2 +++ b/drivers/crypto/Kconfig
   3 @@ -287,6 +287,16 @@ config CRYPTO_DEV_SAHARA
   4           This option enables support for the SAHARA HW crypto accelerator
   5           found in some Freescale i.MX chips.
   6
   7 +config CRYPTO_DEV_DCP
   8 +       tristate "Support for the DCP engine"
   9 +       depends on ARCH_MXS && OF
  10 +       select CRYPTO_BLKCIPHER
  11 +       select CRYPTO_AES
  12 +       select CRYPTO_CBC
  13 +       help
  14 +         This options enables support for the hardware crypto-acceleration
  15 +         capabilities of the DCP co-processor
  16 +
  17  config CRYPTO_DEV_S5P
  18         tristate "Support for Samsung S5PV210 crypto accelerator"
  19         depends on ARCH_S5PV210
  20 --- a/drivers/crypto/Makefile
  21 +++ b/drivers/crypto/Makefile
  22 @@ -13,6 +13,7 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += om
  23  obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
  24  obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
  25  obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
  26 +obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o
  27  obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
  28  obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
  29  obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
  30 --- /dev/null
  31 +++ b/drivers/crypto/dcp.c
  32 @@ -0,0 +1,925 @@
  33 +/*
  34 + * Cryptographic API.
  35 + *
  36 + * Support for DCP cryptographic accelerator.
  37 + *
  38 + * Copyright (c) 2013
  39 + * Author: Tobias Rauter <tobias.rau...@gmail.com>
  40 + *
  41 + * This program is free software; you can redistribute it and/or modify
  42 + * it under the terms of the GNU General Public License version 2 as published
  43 + * by the Free Software Foundation.
  44 + *
  45 + * Based on tegra-aes.c, dcp.c (from freescale SDK) and sahara.c
  46 + */
  47 +#include <linux/module.h>
  48 +#include <linux/init.h>
  49 +#include <linux/errno.h>
  50 +#include <linux/kernel.h>
  51 +#include <linux/platform_device.h>
  52 +#include <linux/dma-mapping.h>
  53 +#include <linux/io.h>
  54 +#include <linux/mutex.h>
  55 +#include <linux/interrupt.h>
  56 +#include <linux/completion.h>
  57 +#include <linux/workqueue.h>
  58 +#include <linux/delay.h>
  59 +#include <linux/crypto.h>
  60 +#include <linux/miscdevice.h>
  61 +
  62 +#include <crypto/scatterwalk.h>
  63 +#include <crypto/aes.h>
  64 +
  65 +
  66 +/* IOCTL for DCP OTP Key AES - taken from Freescale's SDK*/
  67 +#define DBS_IOCTL_BASE   'd'
  68 +#define DBS_ENC        _IOW(DBS_IOCTL_BASE, 0x00, uint8_t[16])
  69 +#define DBS_DEC _IOW(DBS_IOCTL_BASE, 0x01, uint8_t[16])
  70 +
  71 +/* DCP channel used for AES */
  72 +#define USED_CHANNEL 1
  73 +/* Ring Buffers' maximum size */
  74 +#define DCP_MAX_PKG 20
  75 +
  76 +/* Control Register */
  77 +#define DCP_REG_CTRL 0x000
  78 +#define DCP_CTRL_SFRST (1<<31)
  79 +#define DCP_CTRL_CLKGATE (1<<30)
  80 +#define DCP_CTRL_CRYPTO_PRESENT (1<<29)
  81 +#define DCP_CTRL_SHA_PRESENT (1<<28)
  82 +#define DCP_CTRL_GATHER_RES_WRITE (1<<23)
  83 +#define DCP_CTRL_ENABLE_CONTEXT_CACHE (1<<22)
  84 +#define DCP_CTRL_ENABLE_CONTEXT_SWITCH (1<<21)
  85 +#define DCP_CTRL_CH_IRQ_E_0 0x01
  86 +#define DCP_CTRL_CH_IRQ_E_1 0x02
  87 +#define DCP_CTRL_CH_IRQ_E_2 0x04
  88 +#define DCP_CTRL_CH_IRQ_E_3 0x08
  89 +
  90 +/* Status register */
  91 +#define DCP_REG_STAT 0x010
  92 +#define DCP_STAT_OTP_KEY_READY (1<<28)
  93 +#define DCP_STAT_CUR_CHANNEL(stat) ((stat>>24)&0x0F)
  94 +#define DCP_STAT_READY_CHANNEL(stat) ((stat>>16)&0x0F)
  95 +#define DCP_STAT_IRQ(stat) (stat&0x0F)
  96 +#define DCP_STAT_CHAN_0 (0x01)
  97 +#define DCP_STAT_CHAN_1 (0x02)
  98 +#define DCP_STAT_CHAN_2 (0x04)
  99 +#define DCP_STAT_CHAN_3 (0x08)
 100 +
 101 +/* Channel Control Register */
 102 +#define DCP_REG_CHAN_CTRL 0x020
 103 +#define DCP_CHAN_CTRL_CH0_IRQ_MERGED (1<<16)
 104 +#define DCP_CHAN_CTRL_HIGH_PRIO_0 (0x0100)
 105 +#define DCP_CHAN_CTRL_HIGH_PRIO_1 (0x0200)
 106 +#define DCP_CHAN_CTRL_HIGH_PRIO_2 (0x0400)
 107 +#define DCP_CHAN_CTRL_HIGH_PRIO_3 (0x0800)
 108 +#define DCP_CHAN_CTRL_ENABLE_0 (0x01)
 109 +#define DCP_CHAN_CTRL_ENABLE_1 (0x02)
 110 +#define DCP_CHAN_CTRL_ENABLE_2 (0x04)
 111 +#define DCP_CHAN_CTRL_ENABLE_3 (0x08)
 112 +
 113 +/*
 114 + * Channel Registers:
 115 + * The DCP has 4 channels. Each of this channels
 116 + * has 4 registers (command pointer, semaphore, status and options).
 117 + * The address of register REG of channel CHAN is obtained by
 118 + * dcp_chan_reg(REG, CHAN)
 119 + */
 120 +#define DCP_REG_CHAN_PTR       0x00000100
 121 +#define DCP_REG_CHAN_SEMA      0x00000110
 122 +#define DCP_REG_CHAN_STAT      0x00000120
 123 +#define DCP_REG_CHAN_OPT       0x00000130
 124 +
 125 +#define DCP_CHAN_STAT_NEXT_CHAIN_IS_0  0x010000
 126 +#define DCP_CHAN_STAT_NO_CHAIN         0x020000
 127 +#define DCP_CHAN_STAT_CONTEXT_ERROR    0x030000
 128 +#define DCP_CHAN_STAT_PAYLOAD_ERROR    0x040000
 129 +#define DCP_CHAN_STAT_INVALID_MODE     0x050000
 130 +#define DCP_CHAN_STAT_PAGEFAULT                0x40
 131 +#define DCP_CHAN_STAT_DST              0x20
 132 +#define DCP_CHAN_STAT_SRC              0x10
 133 +#define DCP_CHAN_STAT_PACKET           0x08
 134 +#define DCP_CHAN_STAT_SETUP            0x04
 135 +#define DCP_CHAN_STAT_MISMATCH         0x02
 136 +
 137 +/* hw packet control*/
 138 +
 139 +#define DCP_PKT_PAYLOAD_KEY    (1<<11)
 140 +#define DCP_PKT_OTP_KEY                (1<<10)
 141 +#define DCP_PKT_CIPHER_INIT    (1<<9)
 142 +#define DCP_PKG_CIPHER_ENCRYPT (1<<8)
 143 +#define DCP_PKT_CIPHER_ENABLE  (1<<5)
 144 +#define DCP_PKT_DECR_SEM       (1<<1)
 145 +#define DCP_PKT_CHAIN          (1<<2)
 146 +#define DCP_PKT_IRQ            1
 147 +
 148 +#define DCP_PKT_MODE_CBC       (1<<4)
 149 +#define DCP_PKT_KEYSELECT_OTP  (0xFF<<8)
 150 +
 151 +/* cipher flags */
 152 +#define DCP_ENC                0x0001
 153 +#define DCP_DEC                0x0002
 154 +#define DCP_ECB                0x0004
 155 +#define DCP_CBC                0x0008
 156 +#define DCP_CBC_INIT   0x0010
 157 +#define DCP_NEW_KEY    0x0040
 158 +#define DCP_OTP_KEY    0x0080
 159 +#define DCP_AES                0x1000
 160 +
 161 +/* DCP Flags */
 162 +#define DCP_FLAG_BUSY  0x01
 163 +#define DCP_FLAG_PRODUCING     0x02
 164 +
 165 +/* clock defines */
 166 +#define CLOCK_ON       1
 167 +#define CLOCK_OFF      0
 168 +
 169 +struct dcp_dev_req_ctx {
 170 +       int mode;
 171 +};
 172 +
 173 +struct dcp_op {
 174 +       unsigned int            flags;
 175 +       u8                      key[AES_KEYSIZE_128];
 176 +       int                     keylen;
 177 +
 178 +       struct ablkcipher_request       *req;
 179 +       struct crypto_ablkcipher        *fallback;
 180 +
 181 +       uint32_t stat;
 182 +       uint32_t pkt1;
 183 +       uint32_t pkt2;
 184 +       struct ablkcipher_walk walk;
 185 +};
 186 +
 187 +struct dcp_dev {
 188 +       struct device *dev;
 189 +       void __iomem *dcp_regs_base;
 190 +
 191 +       int dcp_vmi_irq;
 192 +       int dcp_irq;
 193 +
 194 +       spinlock_t queue_lock;
 195 +       struct crypto_queue queue;
 196 +
 197 +       uint32_t pkt_produced;
 198 +       uint32_t pkt_consumed;
 199 +
 200 +       struct dcp_hw_packet *hw_pkg[DCP_MAX_PKG];
 201 +       dma_addr_t hw_phys_pkg;
 202 +
 203 +       /* [KEY][IV] Both with 16 Bytes */
 204 +       u8 *payload_base;
 205 +       dma_addr_t payload_base_dma;
 206 +
 207 +
 208 +       struct tasklet_struct   done_task;
 209 +       struct tasklet_struct   queue_task;
 210 +       struct timer_list       watchdog;
 211 +
 212 +       unsigned long           flags;
 213 +
 214 +       struct dcp_op *ctx;
 215 +
 216 +       struct miscdevice dcp_bootstream_misc;
 217 +};
 218 +
 219 +struct dcp_hw_packet {
 220 +       uint32_t next;
 221 +       uint32_t pkt1;
 222 +       uint32_t pkt2;
 223 +       uint32_t src;
 224 +       uint32_t dst;
 225 +       uint32_t size;
 226 +       uint32_t payload;
 227 +       uint32_t stat;
 228 +};
 229 +
 230 +struct dcp_dev *global_dev;
 231 +
 232 +static inline u32 dcp_chan_reg(u32 reg, int chan)
 233 +{
 234 +       return reg + (chan) * 0x40;
 235 +}
 236 +
 237 +static inline void dcp_write(struct dcp_dev *dev, u32 data, u32 reg)
 238 +{
 239 +       writel(data, dev->dcp_regs_base + reg);
 240 +}
 241 +
 242 +static inline void dcp_set(struct dcp_dev *dev, u32 data, u32 reg)
 243 +{
 244 +       writel(data, dev->dcp_regs_base + (reg | 0x04));
 245 +}
 246 +
 247 +static inline void dcp_clear(struct dcp_dev *dev, u32 data, u32 reg)
 248 +{
 249 +       writel(data, dev->dcp_regs_base + (reg | 0x08));
 250 +}
 251 +
 252 +static inline void dcp_toggle(struct dcp_dev *dev, u32 data, u32 reg)
 253 +{
 254 +       writel(data, dev->dcp_regs_base + (reg | 0x0C));
 255 +}
 256 +
 257 +static inline unsigned int dcp_read(struct dcp_dev *dev, u32 reg)
 258 +{
 259 +       return readl(dev->dcp_regs_base + reg);
 260 +}
 261 +
 262 +void dcp_dma_unmap(struct dcp_dev *dev, struct dcp_hw_packet *pkt)
 263 +{
 264 +       dma_unmap_page(dev->dev, pkt->src, pkt->size, DMA_TO_DEVICE);
 265 +       dma_unmap_page(dev->dev, pkt->dst, pkt->size, DMA_FROM_DEVICE);
 266 +       dev_dbg(dev->dev, "unmap packet %x", (unsigned int) pkt);
 267 +}
 268 +
 269 +int dcp_dma_map(struct dcp_dev *dev,
 270 +       struct ablkcipher_walk *walk, struct dcp_hw_packet *pkt)
 271 +{
 272 +       dev_dbg(dev->dev, "map packet %x", (unsigned int) pkt);
 273 +       /* align to length = 16 */
 274 +       pkt->size = walk->nbytes - (walk->nbytes % 16);
 275 +
 276 +       pkt->src = dma_map_page(dev->dev, walk->src.page, walk->src.offset,
 277 +               pkt->size, DMA_TO_DEVICE);
 278 +
 279 +       if (pkt->src == 0) {
 280 +               dev_err(dev->dev, "Unable to map src");
 281 +               return -ENOMEM;
 282 +       }
 283 +
 284 +       pkt->dst = dma_map_page(dev->dev, walk->dst.page, walk->dst.offset,
 285 +               pkt->size, DMA_FROM_DEVICE);
 286 +
 287 +       if (pkt->dst == 0) {
 288 +               dev_err(dev->dev, "Unable to map dst");
 289 +               dma_unmap_page(dev->dev, pkt->src, pkt->size, DMA_TO_DEVICE);
 290 +               return -ENOMEM;
 291 +       }
 292 +
 293 +       return 0;
 294 +}
 295 +
 296 +static void dcp_op_one(struct dcp_dev *dev, struct dcp_hw_packet *pkt,
 297 +                       uint8_t last)
 298 +{
 299 +       struct dcp_op *ctx = dev->ctx;
 300 +       pkt->pkt1 = ctx->pkt1;
 301 +       pkt->pkt2 = ctx->pkt2;
 302 +
 303 +       pkt->payload = (u32) dev->payload_base_dma;
 304 +       pkt->stat = 0;
 305 +
 306 +       if (ctx->flags & DCP_CBC_INIT) {
 307 +               pkt->pkt1 |= DCP_PKT_CIPHER_INIT;
 308 +               ctx->flags &= ~DCP_CBC_INIT;
 309 +       }
 310 +
 311 +       mod_timer(&dev->watchdog, jiffies + msecs_to_jiffies(500));
 312 +       pkt->pkt1 |= DCP_PKT_IRQ;
 313 +       if (!last)
 314 +               pkt->pkt1 |= DCP_PKT_CHAIN;
 315 +
 316 +       dev->pkt_produced++;
 317 +
 318 +       dcp_write(dev, 1,
 319 +               dcp_chan_reg(DCP_REG_CHAN_SEMA, USED_CHANNEL));
 320 +}
 321 +
 322 +static void dcp_op_proceed(struct dcp_dev *dev)
 323 +{
 324 +       struct dcp_op *ctx = dev->ctx;
 325 +       struct dcp_hw_packet *pkt;
 326 +
 327 +       while (ctx->walk.nbytes) {
 328 +               int err = 0;
 329 +
 330 +               pkt = dev->hw_pkg[dev->pkt_produced % DCP_MAX_PKG];
 331 +               err = dcp_dma_map(dev, &ctx->walk, pkt);
 332 +               if (err) {
 333 +                       dev->ctx->stat |= err;
 334 +                       /* start timer to wait for already set up calls */
 335 +                       mod_timer(&dev->watchdog,
 336 +                               jiffies + msecs_to_jiffies(500));
 337 +                       break;
 338 +               }
 339 +
 340 +
 341 +               err = ctx->walk.nbytes - pkt->size;
 342 +               ablkcipher_walk_done(dev->ctx->req, &dev->ctx->walk, err);
 343 +
 344 +               dcp_op_one(dev, pkt, ctx->walk.nbytes == 0);
 345 +               /* we have to wait if no space is left in buffer */
 346 +               if (dev->pkt_produced - dev->pkt_consumed == DCP_MAX_PKG)
 347 +                       break;
 348 +       }
 349 +       clear_bit(DCP_FLAG_PRODUCING, &dev->flags);
 350 +}
 351 +
 352 +static void dcp_op_start(struct dcp_dev *dev, uint8_t use_walk)
 353 +{
 354 +       struct dcp_op *ctx = dev->ctx;
 355 +
 356 +       if (ctx->flags & DCP_NEW_KEY) {
 357 +               memcpy(dev->payload_base, ctx->key, ctx->keylen);
 358 +               ctx->flags &= ~DCP_NEW_KEY;
 359 +       }
 360 +
 361 +       ctx->pkt1 = 0;
 362 +       ctx->pkt1 |= DCP_PKT_CIPHER_ENABLE;
 363 +       ctx->pkt1 |= DCP_PKT_DECR_SEM;
 364 +
 365 +       if (ctx->flags & DCP_OTP_KEY)
 366 +               ctx->pkt1 |= DCP_PKT_OTP_KEY;
 367 +       else
 368 +               ctx->pkt1 |= DCP_PKT_PAYLOAD_KEY;
 369 +
 370 +       if (ctx->flags & DCP_ENC)
 371 +               ctx->pkt1 |= DCP_PKG_CIPHER_ENCRYPT;
 372 +
 373 +       ctx->pkt2 = 0;
 374 +       if (ctx->flags & DCP_CBC)
 375 +               ctx->pkt2 |= DCP_PKT_MODE_CBC;
 376 +
 377 +       dev->pkt_produced = 0;
 378 +       dev->pkt_consumed = 0;
 379 +
 380 +       ctx->stat = 0;
 381 +       dcp_clear(dev, -1, dcp_chan_reg(DCP_REG_CHAN_STAT, USED_CHANNEL));
 382 +       dcp_write(dev, (u32) dev->hw_phys_pkg,
 383 +               dcp_chan_reg(DCP_REG_CHAN_PTR, USED_CHANNEL));
 384 +
 385 +       set_bit(DCP_FLAG_PRODUCING, &dev->flags);
 386 +
 387 +       if (use_walk) {
 388 +               ablkcipher_walk_init(&ctx->walk, ctx->req->dst,
 389 +                               ctx->req->src, ctx->req->nbytes);
 390 +               ablkcipher_walk_phys(ctx->req, &ctx->walk);
 391 +               dcp_op_proceed(dev);
 392 +       } else {
 393 +               dcp_op_one(dev, dev->hw_pkg[0], 1);
 394 +               clear_bit(DCP_FLAG_PRODUCING, &dev->flags);
 395 +       }
 396 +}
 397 +
 398 +static void dcp_done_task(unsigned long data)
 399 +{
 400 +       struct dcp_dev *dev = (struct dcp_dev *)data;
 401 +       struct dcp_hw_packet *last_packet;
 402 +       int fin;
 403 +       fin = 0;
 404 +
 405 +       for (last_packet = dev->hw_pkg[(dev->pkt_consumed) % DCP_MAX_PKG];
 406 +               last_packet->stat == 1;
 407 +               last_packet =
 408 +                       dev->hw_pkg[++(dev->pkt_consumed) % DCP_MAX_PKG]) {
 409 +
 410 +               dcp_dma_unmap(dev, last_packet);
 411 +               last_packet->stat = 0;
 412 +               fin++;
 413 +       }
 414 +       /* the last call of this function already consumed this IRQ's packet */
 415 +       if (fin == 0)
 416 +               return;
 417 +
 418 +       dev_dbg(dev->dev,
 419 +               "Packet(s) done with status %x; finished: %d, produced:%d, complete consumed: %d",
 420 +               dev->ctx->stat, fin, dev->pkt_produced, dev->pkt_consumed);
 421 +
 422 +       last_packet = dev->hw_pkg[(dev->pkt_consumed - 1) % DCP_MAX_PKG];
 423 +       if (!dev->ctx->stat && last_packet->pkt1 & DCP_PKT_CHAIN) {
 424 +               if (!test_and_set_bit(DCP_FLAG_PRODUCING, &dev->flags))
 425 +                       dcp_op_proceed(dev);
 426 +               return;
 427 +       }
 428 +
 429 +       while (unlikely(dev->pkt_consumed < dev->pkt_produced)) {
 430 +               dcp_dma_unmap(dev,
 431 +                       dev->hw_pkg[dev->pkt_consumed++ % DCP_MAX_PKG]);
 432 +       }
 433 +
 434 +       if (dev->ctx->flags & DCP_OTP_KEY) {
 435 +               /* we used the miscdevice, no walk to finish */
 436 +               clear_bit(DCP_FLAG_BUSY, &dev->flags);
 437 +               return;
 438 +       }
 439 +
 440 +       ablkcipher_walk_complete(&dev->ctx->walk);
 441 +       dev->ctx->req->base.complete(&dev->ctx->req->base,
 442 +                       dev->ctx->stat);
 443 +       dev->ctx->req = 0;
 444 +       /* in case there are other requests in the queue */
 445 +       tasklet_schedule(&dev->queue_task);
 446 +}
 447 +
 448 +void dcp_watchdog(unsigned long data)
 449 +{
 450 +       struct dcp_dev *dev = (struct dcp_dev *)data;
 451 +       dev->ctx->stat |= dcp_read(dev,
 452 +                       dcp_chan_reg(DCP_REG_CHAN_STAT, USED_CHANNEL));
 453 +
 454 +       dev_err(dev->dev, "Timeout, Channel status: %x", dev->ctx->stat);
 455 +
 456 +       if (!dev->ctx->stat)
 457 +               dev->ctx->stat = -ETIMEDOUT;
 458 +
 459 +       dcp_done_task(data);
 460 +}
 461 +
 462 +
 463 +static irqreturn_t dcp_common_irq(int irq, void *context)
 464 +{
 465 +       u32 msk;
 466 +       struct dcp_dev *dev = (struct dcp_dev *) context;
 467 +
 468 +       del_timer(&dev->watchdog);
 469 +
 470 +       msk = DCP_STAT_IRQ(dcp_read(dev, DCP_REG_STAT));
 471 +       dcp_clear(dev, msk, DCP_REG_STAT);
 472 +       if (msk == 0)
 473 +               return IRQ_NONE;
 474 +
 475 +       dev->ctx->stat |= dcp_read(dev,
 476 +                       dcp_chan_reg(DCP_REG_CHAN_STAT, USED_CHANNEL));
 477 +
 478 +       if (msk & DCP_STAT_CHAN_1)
 479 +               tasklet_schedule(&dev->done_task);
 480 +
 481 +       return IRQ_HANDLED;
 482 +}
 483 +
 484 +static irqreturn_t dcp_vmi_irq(int irq, void *context)
 485 +{
 486 +       return dcp_common_irq(irq, context);
 487 +}
 488 +
 489 +static irqreturn_t dcp_irq(int irq, void *context)
 490 +{
 491 +       return dcp_common_irq(irq, context);
 492 +}
 493 +
 494 +static void dcp_crypt(struct dcp_dev *dev, struct dcp_op *ctx)
 495 +{
 496 +       dev->ctx = ctx;
 497 +
 498 +       if ((ctx->flags & DCP_CBC) && ctx->req->info) {
 499 +               ctx->flags |= DCP_CBC_INIT;
 500 +               memcpy(dev->payload_base + AES_KEYSIZE_128,
 501 +                       ctx->req->info, AES_KEYSIZE_128);
 502 +       }
 503 +
 504 +       dcp_op_start(dev, 1);
 505 +}
 506 +
 507 +static void dcp_queue_task(unsigned long data)
 508 +{
 509 +       struct dcp_dev *dev = (struct dcp_dev *) data;
 510 +       struct crypto_async_request *async_req, *backlog;
 511 +       struct crypto_ablkcipher *tfm;
 512 +       struct dcp_op *ctx;
 513 +       struct dcp_dev_req_ctx *rctx;
 514 +       struct ablkcipher_request *req;
 515 +       unsigned long flags;
 516 +
 517 +       spin_lock_irqsave(&dev->queue_lock, flags);
 518 +
 519 +       backlog = crypto_get_backlog(&dev->queue);
 520 +       async_req = crypto_dequeue_request(&dev->queue);
 521 +
 522 +       spin_unlock_irqrestore(&dev->queue_lock, flags);
 523 +
 524 +       if (!async_req)
 525 +               goto ret_nothing_done;
 526 +
 527 +       if (backlog)
 528 +               backlog->complete(backlog, -EINPROGRESS);
 529 +
 530 +       req = ablkcipher_request_cast(async_req);
 531 +       tfm = crypto_ablkcipher_reqtfm(req);
 532 +       rctx = ablkcipher_request_ctx(req);
 533 +       ctx = crypto_ablkcipher_ctx(tfm);
 534 +
 535 +       if (!req->src || !req->dst)
 536 +               goto ret_nothing_done;
 537 +
 538 +       ctx->flags |= rctx->mode;
 539 +       ctx->req = req;
 540 +
 541 +       dcp_crypt(dev, ctx);
 542 +
 543 +       return;
 544 +
 545 +ret_nothing_done:
 546 +       clear_bit(DCP_FLAG_BUSY, &dev->flags);
 547 +}
 548 +
 549 +
 550 +static int dcp_cra_init(struct crypto_tfm *tfm)
 551 +{
 552 +       const char *name = tfm->__crt_alg->cra_name;
 553 +       struct dcp_op *ctx = crypto_tfm_ctx(tfm);
 554 +
 555 +       tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_dev_req_ctx);
 556 +
 557 +       ctx->fallback = crypto_alloc_ablkcipher(name, 0,
 558 +                               CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
 559 +
 560 +       if (IS_ERR(ctx->fallback)) {
 561 +               dev_err(global_dev->dev, "Error allocating fallback algo %s\n",
 562 +                       name);
 563 +               return PTR_ERR(ctx->fallback);
 564 +       }
 565 +
 566 +       return 0;
 567 +}
 568 +
 569 +static void dcp_cra_exit(struct crypto_tfm *tfm)
 570 +{
 571 +       struct dcp_op *ctx = crypto_tfm_ctx(tfm);
 572 +
 573 +       if (ctx->fallback)
 574 +               crypto_free_ablkcipher(ctx->fallback);
 575 +
 576 +       ctx->fallback = NULL;
 577 +}
 578 +
 579 +/* async interface */
 580 +static int dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 581 +               unsigned int len)
 582 +{
 583 +       struct dcp_op *ctx = crypto_ablkcipher_ctx(tfm);
 584 +       unsigned int ret = 0;
 585 +       ctx->keylen = len;
 586 +       ctx->flags = 0;
 587 +       if (len == AES_KEYSIZE_128) {
 588 +               if (memcmp(ctx->key, key, AES_KEYSIZE_128)) {
 589 +                       memcpy(ctx->key, key, len);
 590 +                       ctx->flags |= DCP_NEW_KEY;
 591 +               }
 592 +               return 0;
 593 +       }
 594 +
 595 +       ctx->fallback->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
 596 +       ctx->fallback->base.crt_flags |=
 597 +               (tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
 598 +
 599 +       ret = crypto_ablkcipher_setkey(ctx->fallback, key, len);
 600 +       if (ret) {
 601 +               struct crypto_tfm *tfm_aux = crypto_ablkcipher_tfm(tfm);
 602 +
 603 +               tfm_aux->crt_flags &= ~CRYPTO_TFM_RES_MASK;
 604 +               tfm_aux->crt_flags |=
 605 +                       (ctx->fallback->base.crt_flags & CRYPTO_TFM_RES_MASK);
 606 +       }
 607 +       return ret;
 608 +}
 609 +
 610 +static int dcp_aes_cbc_crypt(struct ablkcipher_request *req, int mode)
 611 +{
 612 +       struct dcp_dev_req_ctx *rctx = ablkcipher_request_ctx(req);
 613 +       struct dcp_dev *dev = global_dev;
 614 +       unsigned long flags;
 615 +       int err = 0;
 616 +
 617 +       if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE))
 618 +               return -EINVAL;
 619 +
 620 +       rctx->mode = mode;
 621 +
 622 +       spin_lock_irqsave(&dev->queue_lock, flags);
 623 +       err = ablkcipher_enqueue_request(&dev->queue, req);
 624 +       spin_unlock_irqrestore(&dev->queue_lock, flags);
 625 +
 626 +       flags = test_and_set_bit(DCP_FLAG_BUSY, &dev->flags);
 627 +
 628 +       if (!(flags & DCP_FLAG_BUSY))
 629 +               tasklet_schedule(&dev->queue_task);
 630 +
 631 +       return err;
 632 +}
 633 +
 634 +static int dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
 635 +{
 636 +       struct crypto_tfm *tfm =
 637 +               crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
 638 +       struct dcp_op *ctx = crypto_ablkcipher_ctx(
 639 +               crypto_ablkcipher_reqtfm(req));
 640 +
 641 +       if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
 642 +               int err = 0;
 643 +               ablkcipher_request_set_tfm(req, ctx->fallback);
 644 +               err = crypto_ablkcipher_encrypt(req);
 645 +               ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm));
 646 +               return err;
 647 +       }
 648 +
 649 +       return dcp_aes_cbc_crypt(req, DCP_AES | DCP_ENC | DCP_CBC);
 650 +}
 651 +
 652 +static int dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
 653 +{
 654 +       struct crypto_tfm *tfm =
 655 +               crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
 656 +       struct dcp_op *ctx = crypto_ablkcipher_ctx(
 657 +               crypto_ablkcipher_reqtfm(req));
 658 +
 659 +       if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
 660 +               int err = 0;
 661 +               ablkcipher_request_set_tfm(req, ctx->fallback);
 662 +               err = crypto_ablkcipher_decrypt(req);
 663 +               ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm));
 664 +               return err;
 665 +       }
 666 +       return dcp_aes_cbc_crypt(req, DCP_AES | DCP_DEC | DCP_CBC);
 667 +}
 668 +
 669 +static struct crypto_alg algs[] = {
 670 +       {
 671 +               .cra_name = "cbc(aes)",
 672 +               .cra_driver_name = "dcp-cbc-aes",
 673 +               .cra_alignmask = 3,
 674 +               .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |
 675 +                         CRYPTO_ALG_NEED_FALLBACK,
 676 +               .cra_blocksize = AES_KEYSIZE_128,
 677 +               .cra_type = &crypto_ablkcipher_type,
 678 +               .cra_priority = 300,
 679 +               .cra_u.ablkcipher = {
 680 +                       .min_keysize =  AES_KEYSIZE_128,
 681 +                       .max_keysize = AES_KEYSIZE_128,
 682 +                       .setkey = dcp_aes_setkey,
 683 +                       .encrypt = dcp_aes_cbc_encrypt,
 684 +                       .decrypt = dcp_aes_cbc_decrypt,
 685 +                       .ivsize = AES_KEYSIZE_128,
 686 +               }
 687 +
 688 +       },
 689 +};
 690 +
 691 +/* DCP bootstream verification interface: uses OTP key for crypto */
 692 +static int dcp_bootstream_open(struct inode *inode, struct file *file)
 693 +{
 694 +       file->private_data = container_of((file->private_data),
 695 +                       struct dcp_dev, dcp_bootstream_misc);
 696 +       return 0;
 697 +}
 698 +
 699 +static long dcp_bootstream_ioctl(struct file *file,
 700 +                                        unsigned int cmd, unsigned long arg)
 701 +{
 702 +       struct dcp_dev *dev = (struct dcp_dev *) file->private_data;
 703 +       void __user *argp = (void __user *)arg;
 704 +       int ret;
 705 +
 706 +       if (dev == NULL)
 707 +               return -EBADF;
 708 +
 709 +       if (cmd != DBS_ENC && cmd != DBS_DEC)
 710 +               return -EINVAL;
 711 +
 712 +       if (copy_from_user(dev->payload_base, argp, 16))
 713 +               return -EFAULT;
 714 +
 715 +       if (test_and_set_bit(DCP_FLAG_BUSY, &dev->flags))
 716 +               return -EAGAIN;
 717 +
 718 +       dev->ctx = kzalloc(sizeof(struct dcp_op), GFP_KERNEL);
 719 +       if (!dev->ctx) {
 720 +               dev_err(dev->dev,
 721 +                       "cannot allocate context for OTP crypto");
 722 +               clear_bit(DCP_FLAG_BUSY, &dev->flags);
 723 +               return -ENOMEM;
 724 +       }
 725 +
 726 +       dev->ctx->flags = DCP_AES | DCP_ECB | DCP_OTP_KEY | DCP_CBC_INIT;
 727 +       dev->ctx->flags |= (cmd == DBS_ENC) ? DCP_ENC : DCP_DEC;
 728 +       dev->hw_pkg[0]->src = dev->payload_base_dma;
 729 +       dev->hw_pkg[0]->dst = dev->payload_base_dma;
 730 +       dev->hw_pkg[0]->size = 16;
 731 +
 732 +       dcp_op_start(dev, 0);
 733 +
 734 +       while (test_bit(DCP_FLAG_BUSY, &dev->flags))
 735 +               cpu_relax();
 736 +
 737 +       ret = dev->ctx->stat;
 738 +       if (!ret && copy_to_user(argp, dev->payload_base, 16))
 739 +               ret =  -EFAULT;
 740 +
 741 +       kfree(dev->ctx);
 742 +
 743 +       return ret;
 744 +}
 745 +
 746 +static const struct file_operations dcp_bootstream_fops = {
 747 +       .owner =                THIS_MODULE,
 748 +       .unlocked_ioctl =       dcp_bootstream_ioctl,
 749 +       .open =                 dcp_bootstream_open,
 750 +};
 751 +
 752 +static int dcp_probe(struct platform_device *pdev)
 753 +{
 754 +       struct dcp_dev *dev = NULL;
 755 +       struct resource *r;
 756 +       int i, ret, j;
 757 +
 758 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 759 +       if (dev == NULL) {
 760 +               dev_err(&pdev->dev, "Failed to allocate structure\n");
 761 +               ret = -ENOMEM;
 762 +               goto err;
 763 +       }
 764 +       global_dev = dev;
 765 +       dev->dev = &pdev->dev;
 766 +
 767 +       platform_set_drvdata(pdev, dev);
 768 +
 769 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 770 +       if (!r) {
 771 +               dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n");
 772 +               ret = -ENXIO;
 773 +               goto err_dev;
 774 +       }
 775 +       dev->dcp_regs_base = ioremap(r->start, resource_size(r));
 776 +
 777 +
 778 +       dcp_set(dev, DCP_CTRL_SFRST, DCP_REG_CTRL);
 779 +       udelay(10);
 780 +       dcp_clear(dev, DCP_CTRL_SFRST | DCP_CTRL_CLKGATE, DCP_REG_CTRL);
 781 +
 782 +       dcp_write(dev, DCP_CTRL_GATHER_RES_WRITE |
 783 +               DCP_CTRL_ENABLE_CONTEXT_CACHE | DCP_CTRL_CH_IRQ_E_1,
 784 +               DCP_REG_CTRL);
 785 +
 786 +       dcp_write(dev, DCP_CHAN_CTRL_ENABLE_1, DCP_REG_CHAN_CTRL);
 787 +
 788 +       for (i = 0; i < 4; i++)
 789 +               dcp_clear(dev, -1, dcp_chan_reg(DCP_REG_CHAN_STAT, i));
 790 +
 791 +       dcp_clear(dev, -1, DCP_REG_STAT);
 792 +
 793 +
 794 +       r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 795 +       if (!r) {
 796 +               dev_err(&pdev->dev, "can't get IRQ resource (0)\n");
 797 +               ret = -EIO;
 798 +               goto err_unmap_mem;
 799 +       }
 800 +       dev->dcp_vmi_irq = r->start;
 801 +       ret = request_irq(dev->dcp_vmi_irq, dcp_vmi_irq, 0, "dcp", dev);
 802 +       if (ret != 0) {
 803 +               dev_err(&pdev->dev, "can't request_irq (0)\n");
 804 +               ret = -EIO;
 805 +               goto err_unmap_mem;
 806 +       }
 807 +
 808 +       r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 809 +       if (!r) {
 810 +               dev_err(&pdev->dev, "can't get IRQ resource (1)\n");
 811 +               ret = -EIO;
 812 +               goto err_free_irq0;
 813 +       }
 814 +       dev->dcp_irq = r->start;
 815 +       ret = request_irq(dev->dcp_irq, dcp_irq, 0, "dcp", dev);
 816 +       if (ret != 0) {
 817 +               dev_err(&pdev->dev, "can't request_irq (1)\n");
 818 +               ret = -EIO;
 819 +               goto err_free_irq0;
 820 +       }
 821 +
 822 +       dev->hw_pkg[0] = dma_alloc_coherent(&pdev->dev,
 823 +                       DCP_MAX_PKG * sizeof(struct dcp_hw_packet),
 824 +                       &dev->hw_phys_pkg,
 825 +                       GFP_KERNEL);
 826 +       if (!dev->hw_pkg[0]) {
 827 +               dev_err(&pdev->dev, "Could not allocate hw descriptors\n");
 828 +               ret = -ENOMEM;
 829 +               goto err_free_irq1;
 830 +       }
 831 +
 832 +       for (i = 1; i < DCP_MAX_PKG; i++) {
 833 +               dev->hw_pkg[i - 1]->next = dev->hw_phys_pkg
 834 +                               + i * sizeof(struct dcp_hw_packet);
 835 +               dev->hw_pkg[i] = dev->hw_pkg[i - 1] + 1;
 836 +       }
 837 +       dev->hw_pkg[i - 1]->next = dev->hw_phys_pkg;
 838 +
 839 +
 840 +       dev->payload_base = dma_alloc_coherent(&pdev->dev, 2 * AES_KEYSIZE_128,
 841 +                       &dev->payload_base_dma, GFP_KERNEL);
 842 +       if (!dev->payload_base) {
 843 +               dev_err(&pdev->dev, "Could not allocate memory for key\n");
 844 +               ret = -ENOMEM;
 845 +               goto err_free_hw_packet;
 846 +       }
 847 +       tasklet_init(&dev->queue_task, dcp_queue_task,
 848 +               (unsigned long) dev);
 849 +       tasklet_init(&dev->done_task, dcp_done_task,
 850 +               (unsigned long) dev);
 851 +       spin_lock_init(&dev->queue_lock);
 852 +
 853 +       crypto_init_queue(&dev->queue, 10);
 854 +
 855 +       init_timer(&dev->watchdog);
 856 +       dev->watchdog.function = &dcp_watchdog;
 857 +       dev->watchdog.data = (unsigned long)dev;
 858 +
 859 +       dev->dcp_bootstream_misc.minor = MISC_DYNAMIC_MINOR,
 860 +       dev->dcp_bootstream_misc.name = "dcpboot",
 861 +       dev->dcp_bootstream_misc.fops = &dcp_bootstream_fops,
 862 +       ret = misc_register(&dev->dcp_bootstream_misc);
 863 +       if (ret != 0) {
 864 +               dev_err(dev->dev, "Unable to register misc device\n");
 865 +               goto err_free_key_iv;
 866 +       }
 867 +
 868 +       for (i = 0; i < ARRAY_SIZE(algs); i++) {
 869 +               algs[i].cra_priority = 300;
 870 +               algs[i].cra_ctxsize = sizeof(struct dcp_op);
 871 +               algs[i].cra_module = THIS_MODULE;
 872 +               algs[i].cra_init = dcp_cra_init;
 873 +               algs[i].cra_exit = dcp_cra_exit;
 874 +               if (crypto_register_alg(&algs[i])) {
 875 +                       dev_err(&pdev->dev, "register algorithm failed\n");
 876 +                       ret = -ENOMEM;
 877 +                       goto err_unregister;
 878 +               }
 879 +       }
 880 +       dev_notice(&pdev->dev, "DCP crypto enabled.!\n");
 881 +
 882 +       return 0;
 883 +
 884 +err_unregister:
 885 +       for (j = 0; j < i; j++)
 886 +               crypto_unregister_alg(&algs[j]);
 887 +err_free_key_iv:
 888 +       dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base,
 889 +                       dev->payload_base_dma);
 890 +err_free_hw_packet:
 891 +       dma_free_coherent(&pdev->dev, DCP_MAX_PKG *
 892 +               sizeof(struct dcp_hw_packet), dev->hw_pkg[0],
 893 +               dev->hw_phys_pkg);
 894 +err_free_irq1:
 895 +       free_irq(dev->dcp_irq, dev);
 896 +err_free_irq0:
 897 +       free_irq(dev->dcp_vmi_irq, dev);
 898 +err_unmap_mem:
 899 +       iounmap((void *) dev->dcp_regs_base);
 900 +err_dev:
 901 +       kfree(dev);
 902 +err:
 903 +       return ret;
 904 +}
 905 +
 906 +static int dcp_remove(struct platform_device *pdev)
 907 +{
 908 +       struct dcp_dev *dev;
 909 +       int j;
 910 +       dev = platform_get_drvdata(pdev);
 911 +       platform_set_drvdata(pdev, NULL);
 912 +
 913 +       dma_free_coherent(&pdev->dev,
 914 +                       DCP_MAX_PKG * sizeof(struct dcp_hw_packet),
 915 +                       dev->hw_pkg[0], dev->hw_phys_pkg);
 916 +
 917 +       dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base,
 918 +                       dev->payload_base_dma);
 919 +
 920 +       free_irq(dev->dcp_irq, dev);
 921 +       free_irq(dev->dcp_vmi_irq, dev);
 922 +
 923 +       tasklet_kill(&dev->done_task);
 924 +       tasklet_kill(&dev->queue_task);
 925 +
 926 +       iounmap((void *) dev->dcp_regs_base);
 927 +
 928 +       for (j = 0; j < ARRAY_SIZE(algs); j++)
 929 +               crypto_unregister_alg(&algs[j]);
 930 +
 931 +       misc_deregister(&dev->dcp_bootstream_misc);
 932 +
 933 +       kfree(dev);
 934 +       return 0;
 935 +}
 936 +
 937 +static struct of_device_id fs_dcp_of_match[] = {
 938 +       {       .compatible = "fsl-dcp"},
 939 +       {},
 940 +};
 941 +
 942 +static struct platform_driver fs_dcp_driver = {
 943 +       .probe = dcp_probe,
 944 +       .remove = dcp_remove,
 945 +       .driver = {
 946 +               .name = "fsl-dcp",
 947 +               .owner = THIS_MODULE,
 948 +               .of_match_table = fs_dcp_of_match
 949 +       }
 950 +};
 951 +
 952 +module_platform_driver(fs_dcp_driver);
 953 +
 954 +
 955 +MODULE_AUTHOR("Tobias Rauter <tobias.rau...@gmail.com>");
 956 +MODULE_DESCRIPTION("Freescale DCP Crypto Driver");
 957 +MODULE_LICENSE("GPL");