target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch

   1 From fce8591f73c6a30c231f220d1092362aae0b985c Mon Sep 17 00:00:00 2001
   2 From: Pratyush Anand <pratyush.anand@st.com>
   3 Date: Wed, 11 Dec 2013 15:08:33 +0530
   4 Subject: [PATCH] PCI: designware: Fix I/O transfers by using CPU (not realio)
   5  address
   6
   7 pp->io_base, which is the input of the outbound IO address translation
   8 unit, should be the CPU address.  It was incorrectly programmed to the
   9 realio address.
  10
  11 We should pass global_io_offset rather than sys->io_offset to
  12 pci_ioremap_io(), so we map the new window into the first available spot in
  13 the Linux view of the I/O space.
  14
  15 We must also pass CPU address instead of realio address to pci_ioremap_io().
  16
  17 This patch fixes above issue.  It has been tested with Lecroy PTC in AIC
  18 mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
  19
  20 Tested-by: Mohit Kumar <mohit.kumar@st.com>
  21 Tested-by: Tim Harvey <tharvey@gateworks.com>
  22 Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
  23 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  24 Reviewed-by: Marek Vasut <marex@denx.de
  25 Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
  26 Acked-by: Arnd Bergmann <arnd@arndb.de>
  27 Acked-by: Jingoo Han <jg1.han@samsung.com>
  28 Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
  29 ---
  30  drivers/pci/host/pcie-designware.c | 5 ++---
  31  1 file changed, 2 insertions(+), 3 deletions(-)
  32
  33 --- a/drivers/pci/host/pcie-designware.c
  34 +++ b/drivers/pci/host/pcie-designware.c
  35 @@ -394,6 +394,7 @@ int __init dw_pcie_host_init(struct pcie
  36                                            + global_io_offset);
  37                         pp->config.io_size = resource_size(&pp->io);
  38                         pp->config.io_bus_addr = range.pci_addr;
  39 +                       pp->io_base = range.cpu_addr;
  40                 }
  41                 if (restype == IORESOURCE_MEM) {
  42                         of_pci_range_to_resource(&range, np, &pp->mem);
  43 @@ -419,7 +420,6 @@ int __init dw_pcie_host_init(struct pcie
  44
  45         pp->cfg0_base = pp->cfg.start;
  46         pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
  47 -       pp->io_base = pp->io.start;
  48         pp->mem_base = pp->mem.start;
  49
  50         pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
  51 @@ -585,7 +585,6 @@ static int dw_pcie_wr_other_conf(struct
  52         return ret;
  53  }
  54
  55 -
  56  static int dw_pcie_valid_config(struct pcie_port *pp,
  57                                 struct pci_bus *bus, int dev)
  58  {
  59 @@ -679,7 +678,7 @@ static int dw_pcie_setup(int nr, struct
  60
  61         if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
  62                 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
  63 -               pci_ioremap_io(sys->io_offset, pp->io.start);
  64 +               pci_ioremap_io(global_io_offset, pp->io_base);
  65                 global_io_offset += SZ_64K;
  66                 pci_add_resource_offset(&sys->resources, &pp->io,
  67                                         sys->io_offset);