imx6: kernel: add GW16083 Ethernet Expansion Mezzanine support
[openwrt/svn-archive/archive.git] / target / linux / imx6 / patches-3.14 / 204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch
1 Author: Tim Harvey <tharvey@gateworks.com>
2 Date: Thu May 15 12:36:23 2014 -0700
3
4 net: igb: register mii_bus for SerDes w/ external phy
5
6 If an i210 is configured for 1000BASE-BX link_mode and has an external phy
7 specified, then register an mii bus using the external phy address as
8 a mask.
9
10 An i210 hooked to an external standard phy will be configured with a link_mo
11 of SGMII in which case phy ops will be configured and used internall in the
12 igb driver for link status. However, in certain cases one might be using a
13 backplane SerDes connection to something that talks on the mdio bus but is
14 not a standard phy, such as a switch. In this case by registering an mdio
15 bus a phy driver can manage the device.
16
17 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
18
19 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c
20 +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
21 @@ -606,13 +606,25 @@ static s32 igb_get_invariants_82575(stru
22 switch (link_mode) {
23 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
24 hw->phy.media_type = e1000_media_type_internal_serdes;
25 + if (igb_sgmii_uses_mdio_82575(hw)) {
26 + u32 mdicnfg = rd32(E1000_MDICNFG);
27 + mdicnfg &= E1000_MDICNFG_PHY_MASK;
28 + hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
29 + hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
30 + hw->phy.addr);
31 + } else {
32 + hw_dbg("1000BASE_KX");
33 + }
34 break;
35 case E1000_CTRL_EXT_LINK_MODE_SGMII:
36 /* Get phy control interface type set (MDIO vs. I2C)*/
37 if (igb_sgmii_uses_mdio_82575(hw)) {
38 hw->phy.media_type = e1000_media_type_copper;
39 dev_spec->sgmii_active = true;
40 + hw_dbg("SGMII with external MDIO PHY");
41 break;
42 + } else {
43 + hw_dbg("SGMII with external I2C PHY");
44 }
45 /* fall through for I2C based SGMII */
46 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
47 @@ -629,8 +641,11 @@ static s32 igb_get_invariants_82575(stru
48 hw->phy.media_type = e1000_media_type_copper;
49 dev_spec->sgmii_active = true;
50 }
51 + hw_dbg("SERDES with external SFP");
52
53 break;
54 + } else {
55 + hw_dbg("SERDES");
56 }
57
58 /* do not change link mode for 100BaseFX */
59 --- a/drivers/net/ethernet/intel/igb/e1000_hw.h
60 +++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
61 @@ -32,6 +32,7 @@
62 #include <linux/delay.h>
63 #include <linux/io.h>
64 #include <linux/netdevice.h>
65 +#include <linux/phy.h>
66
67 #include "e1000_regs.h"
68 #include "e1000_defines.h"
69 @@ -553,6 +554,12 @@ struct e1000_hw {
70 struct e1000_mbx_info mbx;
71 struct e1000_host_mng_dhcp_cookie mng_cookie;
72
73 +#ifdef CONFIG_PHYLIB
74 + /* Phylib and MDIO interface */
75 + struct mii_bus *mii_bus;
76 + struct phy_device *phy_dev;
77 + phy_interface_t phy_interface;
78 +#endif
79 union {
80 struct e1000_dev_spec_82575 _82575;
81 } dev_spec;
82 --- a/drivers/net/ethernet/intel/igb/igb_main.c
83 +++ b/drivers/net/ethernet/intel/igb/igb_main.c
84 @@ -45,6 +45,7 @@
85 #include <linux/if_vlan.h>
86 #include <linux/pci.h>
87 #include <linux/pci-aspm.h>
88 +#include <linux/phy.h>
89 #include <linux/delay.h>
90 #include <linux/interrupt.h>
91 #include <linux/ip.h>
92 @@ -2183,6 +2184,126 @@ static s32 igb_init_i2c(struct igb_adapt
93 return status;
94 }
95
96 +
97 +#ifdef CONFIG_PHYLIB
98 +/*
99 + * MMIO/PHYdev support
100 + */
101 +
102 +static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103 +{
104 + struct e1000_hw *hw = bus->priv;
105 + u16 out;
106 + int err;
107 +
108 + err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
109 + if (err)
110 + return err;
111 + return out;
112 +}
113 +
114 +static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
115 + u16 val)
116 +{
117 + struct e1000_hw *hw = bus->priv;
118 +
119 + return igb_write_reg_gs40g(hw, mii_id, regnum, val);
120 +}
121 +
122 +static int igb_enet_mdio_reset(struct mii_bus *bus)
123 +{
124 + udelay(300);
125 + return 0;
126 +}
127 +
128 +static void igb_enet_mii_link(struct net_device *netdev)
129 +{
130 +}
131 +
132 +/* Probe the mdio bus for phys and connect them */
133 +static int igb_enet_mii_probe(struct net_device *netdev)
134 +{
135 + struct igb_adapter *adapter = netdev_priv(netdev);
136 + struct e1000_hw *hw = &adapter->hw;
137 + struct phy_device *phy_dev = NULL;
138 + int phy_id;
139 +
140 + /* check for attached phy */
141 + for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
142 + if (hw->mii_bus->phy_map[phy_id]) {
143 + phy_dev = hw->mii_bus->phy_map[phy_id];
144 + break;
145 + }
146 + }
147 + if (!phy_dev) {
148 + netdev_err(netdev, "no PHY found\n");
149 + return -ENODEV;
150 + }
151 +
152 + hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
153 + phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
154 + igb_enet_mii_link, hw->phy_interface);
155 + if (IS_ERR(phy_dev)) {
156 + netdev_err(netdev, "could not attach to PHY\n");
157 + return PTR_ERR(phy_dev);
158 + }
159 +
160 + hw->phy_dev = phy_dev;
161 + netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
162 + hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
163 +
164 + return 0;
165 +}
166 +
167 +/* Create and register mdio bus */
168 +static int igb_enet_mii_init(struct pci_dev *pdev)
169 +{
170 + struct mii_bus *mii_bus;
171 + struct net_device *netdev = pci_get_drvdata(pdev);
172 + struct igb_adapter *adapter = netdev_priv(netdev);
173 + struct e1000_hw *hw = &adapter->hw;
174 + int err;
175 +
176 + mii_bus = mdiobus_alloc();
177 + if (mii_bus == NULL) {
178 + err = -ENOMEM;
179 + goto err_out;
180 + }
181 +
182 + mii_bus->name = "igb_enet_mii_bus";
183 + mii_bus->read = igb_enet_mdio_read;
184 + mii_bus->write = igb_enet_mdio_write;
185 + mii_bus->reset = igb_enet_mdio_reset;
186 + snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
187 + pci_name(pdev), hw->device_id + 1);
188 + mii_bus->priv = hw;
189 + mii_bus->parent = &pdev->dev;
190 + mii_bus->phy_mask = ~(1 << hw->phy.addr);
191 +
192 + err = mdiobus_register(mii_bus);
193 + if (err) {
194 + printk(KERN_ERR "failed to register mii_bus: %d\n", err);
195 + goto err_out_free_mdiobus;
196 + }
197 + hw->mii_bus = mii_bus;
198 +
199 + return 0;
200 +
201 +err_out_free_mdiobus:
202 + mdiobus_free(mii_bus);
203 +err_out:
204 + return err;
205 +}
206 +
207 +static void igb_enet_mii_remove(struct e1000_hw *hw)
208 +{
209 + if (hw->mii_bus) {
210 + mdiobus_unregister(hw->mii_bus);
211 + mdiobus_free(hw->mii_bus);
212 + }
213 +}
214 +#endif /* CONFIG_PHYLIB */
215 +
216 /**
217 * igb_probe - Device Initialization Routine
218 * @pdev: PCI device information struct
219 @@ -2585,6 +2706,13 @@ static int igb_probe(struct pci_dev *pde
220 }
221
222 pm_runtime_put_noidle(&pdev->dev);
223 +
224 +#ifdef CONFIG_PHYLIB
225 + /* create and register the mdio bus if using ext phy */
226 + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
227 + igb_enet_mii_init(pdev);
228 +#endif
229 +
230 return 0;
231
232 err_register:
233 @@ -2728,6 +2856,10 @@ static void igb_remove(struct pci_dev *p
234 struct e1000_hw *hw = &adapter->hw;
235
236 pm_runtime_get_noresume(&pdev->dev);
237 +#ifdef CONFIG_PHYLIB
238 + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
239 + igb_enet_mii_remove(hw);
240 +#endif
241 #ifdef CONFIG_IGB_HWMON
242 igb_sysfs_exit(adapter);
243 #endif
244 @@ -3032,6 +3164,12 @@ static int __igb_open(struct net_device
245 if (!resuming)
246 pm_runtime_put(&pdev->dev);
247
248 +#ifdef CONFIG_PHYLIB
249 + /* Probe and connect to PHY if using ext phy */
250 + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
251 + igb_enet_mii_probe(netdev);
252 +#endif
253 +
254 /* start the watchdog. */
255 hw->mac.get_link_status = 1;
256 schedule_work(&adapter->watchdog_task);
257 @@ -7087,21 +7225,41 @@ void igb_alloc_rx_buffers(struct igb_rin
258 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
259 {
260 struct igb_adapter *adapter = netdev_priv(netdev);
261 + struct e1000_hw *hw = &adapter->hw;
262 struct mii_ioctl_data *data = if_mii(ifr);
263
264 - if (adapter->hw.phy.media_type != e1000_media_type_copper)
265 + if (adapter->hw.phy.media_type != e1000_media_type_copper &&
266 + !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
267 return -EOPNOTSUPP;
268
269 switch (cmd) {
270 case SIOCGMIIPHY:
271 - data->phy_id = adapter->hw.phy.addr;
272 + data->phy_id = hw->phy.addr;
273 break;
274 case SIOCGMIIREG:
275 - if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
276 - &data->val_out))
277 - return -EIO;
278 + if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
279 + if (igb_read_reg_gs40g(hw, data->phy_id,
280 + data->reg_num & 0x1F,
281 + &data->val_out))
282 + return -EIO;
283 + } else {
284 + if (igb_read_phy_reg(hw, data->reg_num & 0x1F,
285 + &data->val_out))
286 + return -EIO;
287 + }
288 break;
289 case SIOCSMIIREG:
290 + if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
291 + if (igb_write_reg_gs40g(hw, data->phy_id,
292 + data->reg_num & 0x1F,
293 + data->val_in))
294 + return -EIO;
295 + } else {
296 + if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
297 + data->val_in))
298 + return -EIO;
299 + }
300 + break;
301 default:
302 return -EOPNOTSUPP;
303 }