ipq806x: add platform usb support
[openwrt/svn-archive/archive.git] / target / linux / ipq806x / patches-3.18 / 102-soc-qcom-gsbi-Add-support-for-ADM-CRCI-muxing.patch
1 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
2 index 4ce24d4..186e5f4 100644
3 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
4 +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
5 @@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of
6 the 4 GSBI IOs.
7
8 Required properties:
9 -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
10 +- compatible: Should contain "qcom,gsbi-v1.0.0"
11 +- cell-index: Should contain the GSBI index
12 - reg: Address range for GSBI registers
13 - clocks: required clock
14 - clock-names: must contain "iface" entry
15 @@ -16,6 +17,8 @@ Required properties:
16 Optional properties:
17 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
18 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
19 +- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
20 + dma.
21
22 Required properties if child node exists:
23 - #address-cells: Must be 1
24 @@ -39,6 +42,7 @@ Example for APQ8064:
25
26 gsbi4@16300000 {
27 compatible = "qcom,gsbi-v1.0.0";
28 + cell-index = <4>;
29 reg = <0x16300000 0x100>;
30 clocks = <&gcc GSBI4_H_CLK>;
31 clock-names = "iface";
32 @@ -48,6 +52,8 @@ Example for APQ8064:
33 qcom,mode = <GSBI_PROT_I2C_UART>;
34 qcom,crci = <GSBI_CRCI_QUP>;
35
36 + syscon-tcsr = <&tcsr>;
37 +
38 /* child nodes go under here */
39
40 i2c_qup4: i2c@16380000 {
41 @@ -76,3 +82,9 @@ Example for APQ8064:
42 };
43 };
44
45 + tcsr: syscon@1a400000 {
46 + compatible = "qcom,apq8064-tcsr", "syscon";
47 + reg = <0x1a400000 0x100>;
48 + };
49 +
50 +
51 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
52 index 7bd2c94..460b2db 100644
53 --- a/drivers/soc/qcom/Kconfig
54 +++ b/drivers/soc/qcom/Kconfig
55 @@ -4,6 +4,7 @@
56 config QCOM_GSBI
57 tristate "QCOM General Serial Bus Interface"
58 depends on ARCH_QCOM
59 + select MFD_SYSCON
60 help
61 Say y here to enable GSBI support. The GSBI provides control
62 functions for connecting the underlying serial UART, SPI, and I2C
63 diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
64 index 729425d..09c669e 100644
65 --- a/drivers/soc/qcom/qcom_gsbi.c
66 +++ b/drivers/soc/qcom/qcom_gsbi.c
67 @@ -18,22 +18,129 @@
68 #include <linux/of.h>
69 #include <linux/of_platform.h>
70 #include <linux/platform_device.h>
71 +#include <linux/regmap.h>
72 +#include <linux/mfd/syscon.h>
73 +#include <dt-bindings/soc/qcom,gsbi.h>
74
75 #define GSBI_CTRL_REG 0x0000
76 #define GSBI_PROTOCOL_SHIFT 4
77 +#define MAX_GSBI 12
78 +
79 +#define TCSR_ADM_CRCI_BASE 0x70
80 +
81 +struct crci_config {
82 + u32 num_rows;
83 + const u32 (*array)[MAX_GSBI];
84 +};
85 +
86 +static const u32 crci_ipq8064[][MAX_GSBI] = {
87 + {
88 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
89 + 0x000300, 0x000c00, 0x003000, 0x00c000,
90 + 0x030000, 0x0c0000, 0x300000, 0xc00000
91 + },
92 + {
93 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
94 + 0x000300, 0x000c00, 0x003000, 0x00c000,
95 + 0x030000, 0x0c0000, 0x300000, 0xc00000
96 + },
97 +};
98 +
99 +static const struct crci_config config_ipq8064 = {
100 + .num_rows = ARRAY_SIZE(crci_ipq8064),
101 + .array = crci_ipq8064,
102 +};
103 +
104 +static const unsigned int crci_apq8064[][MAX_GSBI] = {
105 + {
106 + 0x001800, 0x006000, 0x000030, 0x0000c0,
107 + 0x000300, 0x000400, 0x000000, 0x000000,
108 + 0x000000, 0x000000, 0x000000, 0x000000
109 + },
110 + {
111 + 0x000000, 0x000000, 0x000000, 0x000000,
112 + 0x000000, 0x000020, 0x0000c0, 0x000000,
113 + 0x000000, 0x000000, 0x000000, 0x000000
114 + },
115 +};
116 +
117 +static const struct crci_config config_apq8064 = {
118 + .num_rows = ARRAY_SIZE(crci_apq8064),
119 + .array = crci_apq8064,
120 +};
121 +
122 +static const unsigned int crci_msm8960[][MAX_GSBI] = {
123 + {
124 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
125 + 0x000300, 0x000400, 0x000000, 0x000000,
126 + 0x000000, 0x000000, 0x000000, 0x000000
127 + },
128 + {
129 + 0x000000, 0x000000, 0x000000, 0x000000,
130 + 0x000000, 0x000020, 0x0000c0, 0x000300,
131 + 0x001800, 0x006000, 0x000000, 0x000000
132 + },
133 +};
134 +
135 +static const struct crci_config config_msm8960 = {
136 + .num_rows = ARRAY_SIZE(crci_msm8960),
137 + .array = crci_msm8960,
138 +};
139 +
140 +static const unsigned int crci_msm8660[][MAX_GSBI] = {
141 + { /* ADM 0 - B */
142 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
143 + 0x000300, 0x000c00, 0x003000, 0x00c000,
144 + 0x030000, 0x0c0000, 0x300000, 0xc00000
145 + },
146 + { /* ADM 0 - B */
147 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
148 + 0x000300, 0x000c00, 0x003000, 0x00c000,
149 + 0x030000, 0x0c0000, 0x300000, 0xc00000
150 + },
151 + { /* ADM 1 - A */
152 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
153 + 0x000300, 0x000c00, 0x003000, 0x00c000,
154 + 0x030000, 0x0c0000, 0x300000, 0xc00000
155 + },
156 + { /* ADM 1 - B */
157 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
158 + 0x000300, 0x000c00, 0x003000, 0x00c000,
159 + 0x030000, 0x0c0000, 0x300000, 0xc00000
160 + },
161 +};
162 +
163 +static const struct crci_config config_msm8660 = {
164 + .num_rows = ARRAY_SIZE(crci_msm8660),
165 + .array = crci_msm8660,
166 +};
167
168 struct gsbi_info {
169 struct clk *hclk;
170 u32 mode;
171 u32 crci;
172 + struct regmap *tcsr;
173 +};
174 +
175 +static const struct of_device_id tcsr_dt_match[] = {
176 + { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
177 + { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
178 + { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
179 + { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
180 + { },
181 };
182
183 static int gsbi_probe(struct platform_device *pdev)
184 {
185 struct device_node *node = pdev->dev.of_node;
186 + struct device_node *tcsr_node;
187 + const struct of_device_id *match;
188 struct resource *res;
189 void __iomem *base;
190 struct gsbi_info *gsbi;
191 + int i;
192 + u32 mask, gsbi_num;
193 + const struct crci_config *config = NULL;
194
195 gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
196
197 @@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_device *pdev)
198 if (IS_ERR(base))
199 return PTR_ERR(base);
200
201 + /* get the tcsr node and setup the config and regmap */
202 + gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
203 +
204 + if (!IS_ERR(gsbi->tcsr)) {
205 + tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
206 + if (tcsr_node) {
207 + match = of_match_node(tcsr_dt_match, tcsr_node);
208 + if (match)
209 + config = match->data;
210 + else
211 + dev_warn(&pdev->dev, "no matching TCSR\n");
212 +
213 + of_node_put(tcsr_node);
214 + }
215 + }
216 +
217 + if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
218 + dev_err(&pdev->dev, "missing cell-index\n");
219 + return -EINVAL;
220 + }
221 +
222 + if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
223 + dev_err(&pdev->dev, "invalid cell-index\n");
224 + return -EINVAL;
225 + }
226 +
227 if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
228 dev_err(&pdev->dev, "missing mode configuration\n");
229 return -EINVAL;
230 @@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_device *pdev)
231 writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
232 base + GSBI_CTRL_REG);
233
234 + /*
235 + * modify tcsr to reflect mode and ADM CRCI mux
236 + * Each gsbi contains a pair of bits, one for RX and one for TX
237 + * SPI mode requires both bits cleared, otherwise they are set
238 + */
239 + if (config) {
240 + for (i = 0; i < config->num_rows; i++) {
241 + mask = config->array[i][gsbi_num - 1];
242 +
243 + if (gsbi->mode == GSBI_PROT_SPI)
244 + regmap_update_bits(gsbi->tcsr,
245 + TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
246 + else
247 + regmap_update_bits(gsbi->tcsr,
248 + TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
249 +
250 + }
251 + }
252 +
253 /* make sure the gsbi control write is not reordered */
254 wmb();
255
256 --
257 1.9.1
258