ipq806x: update bleeding-edge kernel from 4.0 to 4.1
[openwrt/svn-archive/archive.git] / target / linux / ipq806x / patches-4.1 / 708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
1 From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Mon, 11 May 2015 12:29:18 -0700
4 Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
5
6 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
7 ---
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
10 arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
11 3 files changed, 160 insertions(+)
12
13 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
14 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 @@ -64,6 +64,16 @@
16 bias-disable;
17 };
18 };
19 +
20 + rgmii2_pins: rgmii2_pins {
21 + mux {
22 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
23 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
24 + function = "rgmii2";
25 + drive-strength = <8>;
26 + bias-disable;
27 + };
28 + };
29 };
30
31 gsbi@16300000 {
32 @@ -177,5 +187,26 @@
33 reg = <4>;
34 };
35 };
36 +
37 + gmac1: ethernet@37200000 {
38 + status = "ok";
39 + phy-mode = "rgmii";
40 + phy-handle = <&phy4>;
41 + qcom,id = <1>;
42 +
43 + pinctrl-0 = <&rgmii2_pins>;
44 + pinctrl-names = "default";
45 + };
46 +
47 + gmac2: ethernet@37400000 {
48 + status = "ok";
49 + phy-mode = "sgmii";
50 + qcom,id = <2>;
51 +
52 + fixed-link {
53 + speed = <1000>;
54 + full-duplex;
55 + };
56 + };
57 };
58 };
59 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
60 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
61 @@ -72,6 +72,14 @@
62 bias-disable;
63 };
64 };
65 +
66 + rgmii0_pins: rgmii0_pins {
67 + mux {
68 + pins = "gpio2", "gpio66";
69 + drive-strength = <8>;
70 + bias-disable;
71 + };
72 + };
73 };
74
75 gsbi2: gsbi@12480000 {
76 @@ -222,5 +230,40 @@
77 reg = <7>;
78 };
79 };
80 +
81 + gmac0: ethernet@37000000 {
82 + status = "ok";
83 + phy-mode = "rgmii";
84 + qcom,id = <0>;
85 + phy-handle = <&phy4>;
86 +
87 + pinctrl-0 = <&rgmii0_pins>;
88 + pinctrl-names = "default";
89 + };
90 +
91 + gmac1: ethernet@37200000 {
92 + status = "ok";
93 + phy-mode = "sgmii";
94 + qcom,id = <1>;
95 +
96 + fixed-link {
97 + speed = <1000>;
98 + full-duplex;
99 + };
100 + };
101 +
102 + gmac2: ethernet@37400000 {
103 + status = "ok";
104 + phy-mode = "sgmii";
105 + qcom,id = <2>;
106 + phy-handle = <&phy6>;
107 + };
108 +
109 + gmac3: ethernet@37600000 {
110 + status = "ok";
111 + phy-mode = "sgmii";
112 + qcom,id = <3>;
113 + phy-handle = <&phy7>;
114 + };
115 };
116 };
117 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
118 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
119 @@ -578,5 +578,91 @@
120 status = "disabled";
121 };
122
123 + nss_common: syscon@03000000 {
124 + compatible = "syscon";
125 + reg = <0x03000000 0x0000FFFF>;
126 + };
127 +
128 + qsgmii_csr: syscon@1bb00000 {
129 + compatible = "syscon";
130 + reg = <0x1bb00000 0x000001FF>;
131 + };
132 +
133 + gmac0: ethernet@37000000 {
134 + device_type = "network";
135 + compatible = "qcom,ipq806x-gmac";
136 + reg = <0x37000000 0x200000>;
137 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
138 + interrupt-names = "macirq";
139 +
140 + qcom,nss-common = <&nss_common>;
141 + qcom,qsgmii-csr = <&qsgmii_csr>;
142 +
143 + clocks = <&gcc GMAC_CORE1_CLK>;
144 + clock-names = "stmmaceth";
145 +
146 + resets = <&gcc GMAC_CORE1_RESET>;
147 + reset-names = "stmmaceth";
148 +
149 + status = "disabled";
150 + };
151 +
152 + gmac1: ethernet@37200000 {
153 + device_type = "network";
154 + compatible = "qcom,ipq806x-gmac";
155 + reg = <0x37200000 0x200000>;
156 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
157 + interrupt-names = "macirq";
158 +
159 + qcom,nss-common = <&nss_common>;
160 + qcom,qsgmii-csr = <&qsgmii_csr>;
161 +
162 + clocks = <&gcc GMAC_CORE2_CLK>;
163 + clock-names = "stmmaceth";
164 +
165 + resets = <&gcc GMAC_CORE2_RESET>;
166 + reset-names = "stmmaceth";
167 +
168 + status = "disabled";
169 + };
170 +
171 + gmac2: ethernet@37400000 {
172 + device_type = "network";
173 + compatible = "qcom,ipq806x-gmac";
174 + reg = <0x37400000 0x200000>;
175 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
176 + interrupt-names = "macirq";
177 +
178 + qcom,nss-common = <&nss_common>;
179 + qcom,qsgmii-csr = <&qsgmii_csr>;
180 +
181 + clocks = <&gcc GMAC_CORE3_CLK>;
182 + clock-names = "stmmaceth";
183 +
184 + resets = <&gcc GMAC_CORE3_RESET>;
185 + reset-names = "stmmaceth";
186 +
187 + status = "disabled";
188 + };
189 +
190 + gmac3: ethernet@37600000 {
191 + device_type = "network";
192 + compatible = "qcom,ipq806x-gmac";
193 + reg = <0x37600000 0x200000>;
194 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
195 + interrupt-names = "macirq";
196 +
197 + qcom,nss-common = <&nss_common>;
198 + qcom,qsgmii-csr = <&qsgmii_csr>;
199 +
200 + clocks = <&gcc GMAC_CORE4_CLK>;
201 + clock-names = "stmmaceth";
202 +
203 + resets = <&gcc GMAC_CORE4_RESET>;
204 + reset-names = "stmmaceth";
205 +
206 + status = "disabled";
207 + };
208 +
209 };
210 };