target/linux/ipq806x/patches/0001-ARM-dts-msm-split-out-msm8660-and-msm8960-soc-into-d.patch

   1 From 3cdba35369b404875849008ea97cf1705e6060ed Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Thu, 23 Jan 2014 14:09:54 -0600
   4 Subject: [PATCH 001/182] ARM: dts: msm: split out msm8660 and msm8960 soc
   5  into dts include
   6
   7 Pull the SoC device tree bits into their own files so other boards based
   8 on these SoCs can include them and reduce duplication across a number of
   9 boards.
  10
  11 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  12 ---
  13  arch/arm/boot/dts/qcom-msm8660-surf.dts |   59 +-------------------------
  14  arch/arm/boot/dts/qcom-msm8660.dtsi     |   63 ++++++++++++++++++++++++++++
  15  arch/arm/boot/dts/qcom-msm8960-cdp.dts  |   66 +----------------------------
  16  arch/arm/boot/dts/qcom-msm8960.dtsi     |   70 +++++++++++++++++++++++++++++++
  17  4 files changed, 135 insertions(+), 123 deletions(-)
  18  create mode 100644 arch/arm/boot/dts/qcom-msm8660.dtsi
  19  create mode 100644 arch/arm/boot/dts/qcom-msm8960.dtsi
  20
  21 diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  22 index 68a72f5..169bad9 100644
  23 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
  24 +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  25 @@ -1,63 +1,6 @@
  26 -/dts-v1/;
  27 -
  28 -/include/ "skeleton.dtsi"
  29 -
  30 -#include <dt-bindings/clock/qcom,gcc-msm8660.h>
  31 +#include "qcom-msm8660.dtsi"
  32
  33  / {
  34         model = "Qualcomm MSM8660 SURF";
  35         compatible = "qcom,msm8660-surf", "qcom,msm8660";
  36 -       interrupt-parent = <&intc>;
  37 -
  38 -       intc: interrupt-controller@2080000 {
  39 -               compatible = "qcom,msm-8660-qgic";
  40 -               interrupt-controller;
  41 -               #interrupt-cells = <3>;
  42 -               reg = < 0x02080000 0x1000 >,
  43 -                     < 0x02081000 0x1000 >;
  44 -       };
  45 -
  46 -       timer@2000000 {
  47 -               compatible = "qcom,scss-timer", "qcom,msm-timer";
  48 -               interrupts = <1 0 0x301>,
  49 -                            <1 1 0x301>,
  50 -                            <1 2 0x301>;
  51 -               reg = <0x02000000 0x100>;
  52 -               clock-frequency = <27000000>,
  53 -                                 <32768>;
  54 -               cpu-offset = <0x40000>;
  55 -       };
  56 -
  57 -       msmgpio: gpio@800000 {
  58 -               compatible = "qcom,msm-gpio";
  59 -               reg = <0x00800000 0x4000>;
  60 -               gpio-controller;
  61 -               #gpio-cells = <2>;
  62 -               ngpio = <173>;
  63 -               interrupts = <0 16 0x4>;
  64 -               interrupt-controller;
  65 -               #interrupt-cells = <2>;
  66 -       };
  67 -
  68 -       gcc: clock-controller@900000 {
  69 -               compatible = "qcom,gcc-msm8660";
  70 -               #clock-cells = <1>;
  71 -               #reset-cells = <1>;
  72 -               reg = <0x900000 0x4000>;
  73 -       };
  74 -
  75 -       serial@19c40000 {
  76 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  77 -               reg = <0x19c40000 0x1000>,
  78 -                     <0x19c00000 0x1000>;
  79 -               interrupts = <0 195 0x0>;
  80 -               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
  81 -               clock-names = "core", "iface";
  82 -       };
  83 -
  84 -       qcom,ssbi@500000 {
  85 -               compatible = "qcom,ssbi";
  86 -               reg = <0x500000 0x1000>;
  87 -               qcom,controller-type = "pmic-arbiter";
  88 -       };
  89  };
  90 diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
  91 new file mode 100644
  92 index 0000000..69d6c4e
  93 --- /dev/null
  94 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  95 @@ -0,0 +1,63 @@
  96 +/dts-v1/;
  97 +
  98 +/include/ "skeleton.dtsi"
  99 +
 100 +#include <dt-bindings/clock/qcom,gcc-msm8660.h>
 101 +
 102 +/ {
 103 +       model = "Qualcomm MSM8660";
 104 +       compatible = "qcom,msm8660";
 105 +       interrupt-parent = <&intc>;
 106 +
 107 +       intc: interrupt-controller@2080000 {
 108 +               compatible = "qcom,msm-8660-qgic";
 109 +               interrupt-controller;
 110 +               #interrupt-cells = <3>;
 111 +               reg = < 0x02080000 0x1000 >,
 112 +                     < 0x02081000 0x1000 >;
 113 +       };
 114 +
 115 +       timer@2000000 {
 116 +               compatible = "qcom,scss-timer", "qcom,msm-timer";
 117 +               interrupts = <1 0 0x301>,
 118 +                            <1 1 0x301>,
 119 +                            <1 2 0x301>;
 120 +               reg = <0x02000000 0x100>;
 121 +               clock-frequency = <27000000>,
 122 +                                 <32768>;
 123 +               cpu-offset = <0x40000>;
 124 +       };
 125 +
 126 +       msmgpio: gpio@800000 {
 127 +               compatible = "qcom,msm-gpio";
 128 +               reg = <0x00800000 0x4000>;
 129 +               gpio-controller;
 130 +               #gpio-cells = <2>;
 131 +               ngpio = <173>;
 132 +               interrupts = <0 16 0x4>;
 133 +               interrupt-controller;
 134 +               #interrupt-cells = <2>;
 135 +       };
 136 +
 137 +       gcc: clock-controller@900000 {
 138 +               compatible = "qcom,gcc-msm8660";
 139 +               #clock-cells = <1>;
 140 +               #reset-cells = <1>;
 141 +               reg = <0x900000 0x4000>;
 142 +       };
 143 +
 144 +       serial@19c40000 {
 145 +               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 146 +               reg = <0x19c40000 0x1000>,
 147 +                     <0x19c00000 0x1000>;
 148 +               interrupts = <0 195 0x0>;
 149 +               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 150 +               clock-names = "core", "iface";
 151 +       };
 152 +
 153 +       qcom,ssbi@500000 {
 154 +               compatible = "qcom,ssbi";
 155 +               reg = <0x500000 0x1000>;
 156 +               qcom,controller-type = "pmic-arbiter";
 157 +       };
 158 +};
 159 diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 160 index 7c30de4..a58fb88 100644
 161 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 162 +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 163 @@ -1,70 +1,6 @@
 164 -/dts-v1/;
 165 -
 166 -/include/ "skeleton.dtsi"
 167 -
 168 -#include <dt-bindings/clock/qcom,gcc-msm8960.h>
 169 +#include "qcom-msm8960.dtsi"
 170
 171  / {
 172         model = "Qualcomm MSM8960 CDP";
 173         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
 174 -       interrupt-parent = <&intc>;
 175 -
 176 -       intc: interrupt-controller@2000000 {
 177 -               compatible = "qcom,msm-qgic2";
 178 -               interrupt-controller;
 179 -               #interrupt-cells = <3>;
 180 -               reg = < 0x02000000 0x1000 >,
 181 -                     < 0x02002000 0x1000 >;
 182 -       };
 183 -
 184 -       timer@200a000 {
 185 -               compatible = "qcom,kpss-timer", "qcom,msm-timer";
 186 -               interrupts = <1 1 0x301>,
 187 -                            <1 2 0x301>,
 188 -                            <1 3 0x301>;
 189 -               reg = <0x0200a000 0x100>;
 190 -               clock-frequency = <27000000>,
 191 -                                 <32768>;
 192 -               cpu-offset = <0x80000>;
 193 -       };
 194 -
 195 -       msmgpio: gpio@800000 {
 196 -               compatible = "qcom,msm-gpio";
 197 -               gpio-controller;
 198 -               #gpio-cells = <2>;
 199 -               ngpio = <150>;
 200 -               interrupts = <0 16 0x4>;
 201 -               interrupt-controller;
 202 -               #interrupt-cells = <2>;
 203 -               reg = <0x800000 0x4000>;
 204 -       };
 205 -
 206 -       gcc: clock-controller@900000 {
 207 -               compatible = "qcom,gcc-msm8960";
 208 -               #clock-cells = <1>;
 209 -               #reset-cells = <1>;
 210 -               reg = <0x900000 0x4000>;
 211 -       };
 212 -
 213 -       clock-controller@4000000 {
 214 -               compatible = "qcom,mmcc-msm8960";
 215 -               reg = <0x4000000 0x1000>;
 216 -               #clock-cells = <1>;
 217 -               #reset-cells = <1>;
 218 -       };
 219 -
 220 -       serial@16440000 {
 221 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 222 -               reg = <0x16440000 0x1000>,
 223 -                     <0x16400000 0x1000>;
 224 -               interrupts = <0 154 0x0>;
 225 -               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 226 -               clock-names = "core", "iface";
 227 -       };
 228 -
 229 -       qcom,ssbi@500000 {
 230 -               compatible = "qcom,ssbi";
 231 -               reg = <0x500000 0x1000>;
 232 -               qcom,controller-type = "pmic-arbiter";
 233 -       };
 234  };
 235 diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
 236 new file mode 100644
 237 index 0000000..ff00282
 238 --- /dev/null
 239 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
 240 @@ -0,0 +1,70 @@
 241 +/dts-v1/;
 242 +
 243 +/include/ "skeleton.dtsi"
 244 +
 245 +#include <dt-bindings/clock/qcom,gcc-msm8960.h>
 246 +
 247 +/ {
 248 +       model = "Qualcomm MSM8960";
 249 +       compatible = "qcom,msm8960";
 250 +       interrupt-parent = <&intc>;
 251 +
 252 +       intc: interrupt-controller@2000000 {
 253 +               compatible = "qcom,msm-qgic2";
 254 +               interrupt-controller;
 255 +               #interrupt-cells = <3>;
 256 +               reg = < 0x02000000 0x1000 >,
 257 +                     < 0x02002000 0x1000 >;
 258 +       };
 259 +
 260 +       timer@200a000 {
 261 +               compatible = "qcom,kpss-timer", "qcom,msm-timer";
 262 +               interrupts = <1 1 0x301>,
 263 +                            <1 2 0x301>,
 264 +                            <1 3 0x301>;
 265 +               reg = <0x0200a000 0x100>;
 266 +               clock-frequency = <27000000>,
 267 +                                 <32768>;
 268 +               cpu-offset = <0x80000>;
 269 +       };
 270 +
 271 +       msmgpio: gpio@800000 {
 272 +               compatible = "qcom,msm-gpio";
 273 +               gpio-controller;
 274 +               #gpio-cells = <2>;
 275 +               ngpio = <150>;
 276 +               interrupts = <0 16 0x4>;
 277 +               interrupt-controller;
 278 +               #interrupt-cells = <2>;
 279 +               reg = <0x800000 0x4000>;
 280 +       };
 281 +
 282 +       gcc: clock-controller@900000 {
 283 +               compatible = "qcom,gcc-msm8960";
 284 +               #clock-cells = <1>;
 285 +               #reset-cells = <1>;
 286 +               reg = <0x900000 0x4000>;
 287 +       };
 288 +
 289 +       clock-controller@4000000 {
 290 +               compatible = "qcom,mmcc-msm8960";
 291 +               reg = <0x4000000 0x1000>;
 292 +               #clock-cells = <1>;
 293 +               #reset-cells = <1>;
 294 +       };
 295 +
 296 +       serial@16440000 {
 297 +               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 298 +               reg = <0x16440000 0x1000>,
 299 +                     <0x16400000 0x1000>;
 300 +               interrupts = <0 154 0x0>;
 301 +               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 302 +               clock-names = "core", "iface";
 303 +       };
 304 +
 305 +       qcom,ssbi@500000 {
 306 +               compatible = "qcom,ssbi";
 307 +               reg = <0x500000 0x1000>;
 308 +               qcom,controller-type = "pmic-arbiter";
 309 +       };
 310 +};
 311 --
 312 1.7.10.4
 313