ipq806x: Add support for IPQ806x chip family
[openwrt/svn-archive/archive.git] / target / linux / ipq806x / patches / 0084-soc-qcom-Add-GSBI-driver.patch
1 From a2f0fc20ea49e5dbbdbb21444683ea760fbdd38f Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 24 Apr 2014 11:31:21 -0500
4 Subject: [PATCH 084/182] soc: qcom: Add GSBI driver
5
6 The GSBI (General Serial Bus Interface) driver controls the overarching
7 configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
8 earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
9 functionality in various combinations.
10
11 Signed-off-by: Andy Gross <agross@codeaurora.org>
12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
13 ---
14 drivers/soc/Kconfig | 2 +
15 drivers/soc/Makefile | 5 +++
16 drivers/soc/qcom/Kconfig | 11 ++++++
17 drivers/soc/qcom/Makefile | 1 +
18 drivers/soc/qcom/qcom_gsbi.c | 84 ++++++++++++++++++++++++++++++++++++++++++
19 5 files changed, 103 insertions(+)
20 create mode 100644 drivers/soc/Makefile
21 create mode 100644 drivers/soc/qcom/Kconfig
22 create mode 100644 drivers/soc/qcom/Makefile
23 create mode 100644 drivers/soc/qcom/qcom_gsbi.c
24
25 diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
26 index 339baa8..c854385 100644
27 --- a/drivers/soc/Kconfig
28 +++ b/drivers/soc/Kconfig
29 @@ -1,3 +1,5 @@
30 menu "SOC (System On Chip) specific Drivers"
31
32 +source "drivers/soc/qcom/Kconfig"
33 +
34 endmenu
35 diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
36 new file mode 100644
37 index 0000000..0f7c447
38 --- /dev/null
39 +++ b/drivers/soc/Makefile
40 @@ -0,0 +1,5 @@
41 +#
42 +# Makefile for the Linux Kernel SOC specific device drivers.
43 +#
44 +
45 +obj-$(CONFIG_ARCH_QCOM) += qcom/
46 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
47 new file mode 100644
48 index 0000000..7bd2c94
49 --- /dev/null
50 +++ b/drivers/soc/qcom/Kconfig
51 @@ -0,0 +1,11 @@
52 +#
53 +# QCOM Soc drivers
54 +#
55 +config QCOM_GSBI
56 + tristate "QCOM General Serial Bus Interface"
57 + depends on ARCH_QCOM
58 + help
59 + Say y here to enable GSBI support. The GSBI provides control
60 + functions for connecting the underlying serial UART, SPI, and I2C
61 + devices to the output pins.
62 +
63 diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
64 new file mode 100644
65 index 0000000..4389012
66 --- /dev/null
67 +++ b/drivers/soc/qcom/Makefile
68 @@ -0,0 +1 @@
69 +obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
70 diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
71 new file mode 100644
72 index 0000000..061dd06
73 --- /dev/null
74 +++ b/drivers/soc/qcom/qcom_gsbi.c
75 @@ -0,0 +1,84 @@
76 +/*
77 + * Copyright (c) 2014, The Linux foundation. All rights reserved.
78 + *
79 + * This program is free software; you can redistribute it and/or modify
80 + * it under the terms of the GNU General Public License rev 2 and
81 + * only rev 2 as published by the free Software foundation.
82 + *
83 + * This program is distributed in the hope that it will be useful,
84 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
85 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
86 + * GNU General Public License for more details.
87 + */
88 +
89 +#include <linux/clk.h>
90 +#include <linux/err.h>
91 +#include <linux/io.h>
92 +#include <linux/module.h>
93 +#include <linux/of.h>
94 +#include <linux/of_platform.h>
95 +#include <linux/platform_device.h>
96 +
97 +#define GSBI_CTRL_REG 0x0000
98 +#define GSBI_PROTOCOL_SHIFT 4
99 +
100 +static int gsbi_probe(struct platform_device *pdev)
101 +{
102 + struct device_node *node = pdev->dev.of_node;
103 + struct resource *res;
104 + void __iomem *base;
105 + struct clk *hclk;
106 + u32 mode, crci = 0;
107 +
108 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
109 + base = devm_ioremap_resource(&pdev->dev, res);
110 + if (IS_ERR(base))
111 + return PTR_ERR(base);
112 +
113 + if (of_property_read_u32(node, "qcom,mode", &mode)) {
114 + dev_err(&pdev->dev, "missing mode configuration\n");
115 + return -EINVAL;
116 + }
117 +
118 + /* not required, so default to 0 if not present */
119 + of_property_read_u32(node, "qcom,crci", &crci);
120 +
121 + dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n", mode, crci);
122 +
123 + hclk = devm_clk_get(&pdev->dev, "iface");
124 + if (IS_ERR(hclk))
125 + return PTR_ERR(hclk);
126 +
127 + clk_prepare_enable(hclk);
128 +
129 + writel_relaxed((mode << GSBI_PROTOCOL_SHIFT) | crci,
130 + base + GSBI_CTRL_REG);
131 +
132 + /* make sure the gsbi control write is not reordered */
133 + wmb();
134 +
135 + clk_disable_unprepare(hclk);
136 +
137 + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
138 +}
139 +
140 +static const struct of_device_id gsbi_dt_match[] = {
141 + { .compatible = "qcom,gsbi-v1.0.0", },
142 +};
143 +
144 +MODULE_DEVICE_TABLE(of, gsbi_dt_match);
145 +
146 +static struct platform_driver gsbi_driver = {
147 + .driver = {
148 + .name = "gsbi",
149 + .owner = THIS_MODULE,
150 + .of_match_table = gsbi_dt_match,
151 + },
152 + .probe = gsbi_probe,
153 +};
154 +
155 +module_platform_driver(gsbi_driver);
156 +
157 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
158 +MODULE_DESCRIPTION("QCOM GSBI driver");
159 +MODULE_LICENSE("GPL v2");
160 --
161 1.7.10.4
162