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ipq806x: Add support for IPQ806x chip family
[openwrt/svn-archive/archive.git] / target / linux / ipq806x / patches / 0125-clk-qcom-Add-support-for-IPQ8064-s-global-clock-cont.patch
1 From 2e6dfaa714ba4bd70fa5dda07c525b6c15e44552 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Thu, 3 Apr 2014 13:47:07 -0500
4 Subject: [PATCH 125/182] clk: qcom: Add support for IPQ8064's global clock
5 controller (GCC)
6
7 Add a driver for the global clock controller found on IPQ8064 based
8 platforms. This should allow most non-multimedia device drivers to probe
9 and control their clocks.
10
11 This is currently missing clocks for USB HSIC and networking devices.
12
13 Signed-off-by: Kumar Gala <galak@codeaurora.org>
14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 ---
16 .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
17 drivers/clk/qcom/Kconfig | 8 +
18 drivers/clk/qcom/Makefile | 1 +
19 drivers/clk/qcom/gcc-ipq806x.c | 2424 ++++++++++++++++++++
20 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 293 +++
21 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 132 ++
22 6 files changed, 2859 insertions(+)
23 create mode 100644 drivers/clk/qcom/gcc-ipq806x.c
24 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq806x.h
25 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq806x.h
26
27 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
28 index 9cfcb4f..0171509 100644
29 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
30 +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
31 @@ -5,6 +5,7 @@ Required properties :
32 - compatible : shall contain only one of the following:
33
34 "qcom,gcc-apq8064"
35 + "qcom,gcc-ipq8064"
36 "qcom,gcc-msm8660"
37 "qcom,gcc-msm8960"
38 "qcom,gcc-msm8974"
39 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
40 index 7f696b7..cfaa54c 100644
41 --- a/drivers/clk/qcom/Kconfig
42 +++ b/drivers/clk/qcom/Kconfig
43 @@ -4,6 +4,14 @@ config COMMON_CLK_QCOM
44 select REGMAP_MMIO
45 select RESET_CONTROLLER
46
47 +config IPQ_GCC_806X
48 + tristate "IPQ806x Global Clock Controller"
49 + depends on COMMON_CLK_QCOM
50 + help
51 + Support for the global clock controller on ipq806x devices.
52 + Say Y if you want to use peripheral devices such as UART, SPI,
53 + i2c, USB, SD/eMMC, etc.
54 +
55 config MSM_GCC_8660
56 tristate "MSM8660 Global Clock Controller"
57 depends on COMMON_CLK_QCOM
58 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
59 index 689e05b..df2a1b3 100644
60 --- a/drivers/clk/qcom/Makefile
61 +++ b/drivers/clk/qcom/Makefile
62 @@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
63 clk-qcom-y += clk-branch.o
64 clk-qcom-y += reset.o
65
66 +obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
67 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
68 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
69 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
70 diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
71 new file mode 100644
72 index 0000000..278c5fe
73 --- /dev/null
74 +++ b/drivers/clk/qcom/gcc-ipq806x.c
75 @@ -0,0 +1,2424 @@
76 +/*
77 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
78 + *
79 + * This software is licensed under the terms of the GNU General Public
80 + * License version 2, as published by the Free Software Foundation, and
81 + * may be copied, distributed, and modified under those terms.
82 + *
83 + * This program is distributed in the hope that it will be useful,
84 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
85 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86 + * GNU General Public License for more details.
87 + */
88 +
89 +#include <linux/kernel.h>
90 +#include <linux/bitops.h>
91 +#include <linux/err.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/module.h>
94 +#include <linux/of.h>
95 +#include <linux/of_device.h>
96 +#include <linux/clk-provider.h>
97 +#include <linux/regmap.h>
98 +#include <linux/reset-controller.h>
99 +
100 +#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
101 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
102 +
103 +#include "common.h"
104 +#include "clk-regmap.h"
105 +#include "clk-pll.h"
106 +#include "clk-rcg.h"
107 +#include "clk-branch.h"
108 +#include "reset.h"
109 +
110 +static struct clk_pll pll3 = {
111 + .l_reg = 0x3164,
112 + .m_reg = 0x3168,
113 + .n_reg = 0x316c,
114 + .config_reg = 0x3174,
115 + .mode_reg = 0x3160,
116 + .status_reg = 0x3178,
117 + .status_bit = 16,
118 + .clkr.hw.init = &(struct clk_init_data){
119 + .name = "pll3",
120 + .parent_names = (const char *[]){ "pxo" },
121 + .num_parents = 1,
122 + .ops = &clk_pll_ops,
123 + },
124 +};
125 +
126 +static struct clk_pll pll8 = {
127 + .l_reg = 0x3144,
128 + .m_reg = 0x3148,
129 + .n_reg = 0x314c,
130 + .config_reg = 0x3154,
131 + .mode_reg = 0x3140,
132 + .status_reg = 0x3158,
133 + .status_bit = 16,
134 + .clkr.hw.init = &(struct clk_init_data){
135 + .name = "pll8",
136 + .parent_names = (const char *[]){ "pxo" },
137 + .num_parents = 1,
138 + .ops = &clk_pll_ops,
139 + },
140 +};
141 +
142 +static struct clk_regmap pll8_vote = {
143 + .enable_reg = 0x34c0,
144 + .enable_mask = BIT(8),
145 + .hw.init = &(struct clk_init_data){
146 + .name = "pll8_vote",
147 + .parent_names = (const char *[]){ "pll8" },
148 + .num_parents = 1,
149 + .ops = &clk_pll_vote_ops,
150 + },
151 +};
152 +
153 +static struct clk_pll pll14 = {
154 + .l_reg = 0x31c4,
155 + .m_reg = 0x31c8,
156 + .n_reg = 0x31cc,
157 + .config_reg = 0x31d4,
158 + .mode_reg = 0x31c0,
159 + .status_reg = 0x31d8,
160 + .status_bit = 16,
161 + .clkr.hw.init = &(struct clk_init_data){
162 + .name = "pll14",
163 + .parent_names = (const char *[]){ "pxo" },
164 + .num_parents = 1,
165 + .ops = &clk_pll_ops,
166 + },
167 +};
168 +
169 +static struct clk_regmap pll14_vote = {
170 + .enable_reg = 0x34c0,
171 + .enable_mask = BIT(14),
172 + .hw.init = &(struct clk_init_data){
173 + .name = "pll14_vote",
174 + .parent_names = (const char *[]){ "pll14" },
175 + .num_parents = 1,
176 + .ops = &clk_pll_vote_ops,
177 + },
178 +};
179 +
180 +#define P_PXO 0
181 +#define P_PLL8 1
182 +#define P_PLL3 1
183 +#define P_PLL0 2
184 +#define P_CXO 2
185 +
186 +static const u8 gcc_pxo_pll8_map[] = {
187 + [P_PXO] = 0,
188 + [P_PLL8] = 3,
189 +};
190 +
191 +static const char *gcc_pxo_pll8[] = {
192 + "pxo",
193 + "pll8_vote",
194 +};
195 +
196 +static const u8 gcc_pxo_pll8_cxo_map[] = {
197 + [P_PXO] = 0,
198 + [P_PLL8] = 3,
199 + [P_CXO] = 5,
200 +};
201 +
202 +static const char *gcc_pxo_pll8_cxo[] = {
203 + "pxo",
204 + "pll8_vote",
205 + "cxo",
206 +};
207 +
208 +static const u8 gcc_pxo_pll3_map[] = {
209 + [P_PXO] = 0,
210 + [P_PLL3] = 1,
211 +};
212 +
213 +static const u8 gcc_pxo_pll3_sata_map[] = {
214 + [P_PXO] = 0,
215 + [P_PLL3] = 6,
216 +};
217 +
218 +static const char *gcc_pxo_pll3[] = {
219 + "pxo",
220 + "pll3",
221 +};
222 +
223 +static const u8 gcc_pxo_pll8_pll0[] = {
224 + [P_PXO] = 0,
225 + [P_PLL8] = 3,
226 + [P_PLL0] = 2,
227 +};
228 +
229 +static const char *gcc_pxo_pll8_pll0_map[] = {
230 + "pxo",
231 + "pll8_vote",
232 + "pll0",
233 +};
234 +
235 +static struct freq_tbl clk_tbl_gsbi_uart[] = {
236 + { 1843200, P_PLL8, 2, 6, 625 },
237 + { 3686400, P_PLL8, 2, 12, 625 },
238 + { 7372800, P_PLL8, 2, 24, 625 },
239 + { 14745600, P_PLL8, 2, 48, 625 },
240 + { 16000000, P_PLL8, 4, 1, 6 },
241 + { 24000000, P_PLL8, 4, 1, 4 },
242 + { 32000000, P_PLL8, 4, 1, 3 },
243 + { 40000000, P_PLL8, 1, 5, 48 },
244 + { 46400000, P_PLL8, 1, 29, 240 },
245 + { 48000000, P_PLL8, 4, 1, 2 },
246 + { 51200000, P_PLL8, 1, 2, 15 },
247 + { 56000000, P_PLL8, 1, 7, 48 },
248 + { 58982400, P_PLL8, 1, 96, 625 },
249 + { 64000000, P_PLL8, 2, 1, 3 },
250 + { }
251 +};
252 +
253 +static struct clk_rcg gsbi1_uart_src = {
254 + .ns_reg = 0x29d4,
255 + .md_reg = 0x29d0,
256 + .mn = {
257 + .mnctr_en_bit = 8,
258 + .mnctr_reset_bit = 7,
259 + .mnctr_mode_shift = 5,
260 + .n_val_shift = 16,
261 + .m_val_shift = 16,
262 + .width = 16,
263 + },
264 + .p = {
265 + .pre_div_shift = 3,
266 + .pre_div_width = 2,
267 + },
268 + .s = {
269 + .src_sel_shift = 0,
270 + .parent_map = gcc_pxo_pll8_map,
271 + },
272 + .freq_tbl = clk_tbl_gsbi_uart,
273 + .clkr = {
274 + .enable_reg = 0x29d4,
275 + .enable_mask = BIT(11),
276 + .hw.init = &(struct clk_init_data){
277 + .name = "gsbi1_uart_src",
278 + .parent_names = gcc_pxo_pll8,
279 + .num_parents = 2,
280 + .ops = &clk_rcg_ops,
281 + .flags = CLK_SET_PARENT_GATE,
282 + },
283 + },
284 +};
285 +
286 +static struct clk_branch gsbi1_uart_clk = {
287 + .halt_reg = 0x2fcc,
288 + .halt_bit = 12,
289 + .clkr = {
290 + .enable_reg = 0x29d4,
291 + .enable_mask = BIT(9),
292 + .hw.init = &(struct clk_init_data){
293 + .name = "gsbi1_uart_clk",
294 + .parent_names = (const char *[]){
295 + "gsbi1_uart_src",
296 + },
297 + .num_parents = 1,
298 + .ops = &clk_branch_ops,
299 + .flags = CLK_SET_RATE_PARENT,
300 + },
301 + },
302 +};
303 +
304 +static struct clk_rcg gsbi2_uart_src = {
305 + .ns_reg = 0x29f4,
306 + .md_reg = 0x29f0,
307 + .mn = {
308 + .mnctr_en_bit = 8,
309 + .mnctr_reset_bit = 7,
310 + .mnctr_mode_shift = 5,
311 + .n_val_shift = 16,
312 + .m_val_shift = 16,
313 + .width = 16,
314 + },
315 + .p = {
316 + .pre_div_shift = 3,
317 + .pre_div_width = 2,
318 + },
319 + .s = {
320 + .src_sel_shift = 0,
321 + .parent_map = gcc_pxo_pll8_map,
322 + },
323 + .freq_tbl = clk_tbl_gsbi_uart,
324 + .clkr = {
325 + .enable_reg = 0x29f4,
326 + .enable_mask = BIT(11),
327 + .hw.init = &(struct clk_init_data){
328 + .name = "gsbi2_uart_src",
329 + .parent_names = gcc_pxo_pll8,
330 + .num_parents = 2,
331 + .ops = &clk_rcg_ops,
332 + .flags = CLK_SET_PARENT_GATE,
333 + },
334 + },
335 +};
336 +
337 +static struct clk_branch gsbi2_uart_clk = {
338 + .halt_reg = 0x2fcc,
339 + .halt_bit = 8,
340 + .clkr = {
341 + .enable_reg = 0x29f4,
342 + .enable_mask = BIT(9),
343 + .hw.init = &(struct clk_init_data){
344 + .name = "gsbi2_uart_clk",
345 + .parent_names = (const char *[]){
346 + "gsbi2_uart_src",
347 + },
348 + .num_parents = 1,
349 + .ops = &clk_branch_ops,
350 + .flags = CLK_SET_RATE_PARENT,
351 + },
352 + },
353 +};
354 +
355 +static struct clk_rcg gsbi4_uart_src = {
356 + .ns_reg = 0x2a34,
357 + .md_reg = 0x2a30,
358 + .mn = {
359 + .mnctr_en_bit = 8,
360 + .mnctr_reset_bit = 7,
361 + .mnctr_mode_shift = 5,
362 + .n_val_shift = 16,
363 + .m_val_shift = 16,
364 + .width = 16,
365 + },
366 + .p = {
367 + .pre_div_shift = 3,
368 + .pre_div_width = 2,
369 + },
370 + .s = {
371 + .src_sel_shift = 0,
372 + .parent_map = gcc_pxo_pll8_map,
373 + },
374 + .freq_tbl = clk_tbl_gsbi_uart,
375 + .clkr = {
376 + .enable_reg = 0x2a34,
377 + .enable_mask = BIT(11),
378 + .hw.init = &(struct clk_init_data){
379 + .name = "gsbi4_uart_src",
380 + .parent_names = gcc_pxo_pll8,
381 + .num_parents = 2,
382 + .ops = &clk_rcg_ops,
383 + .flags = CLK_SET_PARENT_GATE,
384 + },
385 + },
386 +};
387 +
388 +static struct clk_branch gsbi4_uart_clk = {
389 + .halt_reg = 0x2fd0,
390 + .halt_bit = 26,
391 + .clkr = {
392 + .enable_reg = 0x2a34,
393 + .enable_mask = BIT(9),
394 + .hw.init = &(struct clk_init_data){
395 + .name = "gsbi4_uart_clk",
396 + .parent_names = (const char *[]){
397 + "gsbi4_uart_src",
398 + },
399 + .num_parents = 1,
400 + .ops = &clk_branch_ops,
401 + .flags = CLK_SET_RATE_PARENT,
402 + },
403 + },
404 +};
405 +
406 +static struct clk_rcg gsbi5_uart_src = {
407 + .ns_reg = 0x2a54,
408 + .md_reg = 0x2a50,
409 + .mn = {
410 + .mnctr_en_bit = 8,
411 + .mnctr_reset_bit = 7,
412 + .mnctr_mode_shift = 5,
413 + .n_val_shift = 16,
414 + .m_val_shift = 16,
415 + .width = 16,
416 + },
417 + .p = {
418 + .pre_div_shift = 3,
419 + .pre_div_width = 2,
420 + },
421 + .s = {
422 + .src_sel_shift = 0,
423 + .parent_map = gcc_pxo_pll8_map,
424 + },
425 + .freq_tbl = clk_tbl_gsbi_uart,
426 + .clkr = {
427 + .enable_reg = 0x2a54,
428 + .enable_mask = BIT(11),
429 + .hw.init = &(struct clk_init_data){
430 + .name = "gsbi5_uart_src",
431 + .parent_names = gcc_pxo_pll8,
432 + .num_parents = 2,
433 + .ops = &clk_rcg_ops,
434 + .flags = CLK_SET_PARENT_GATE,
435 + },
436 + },
437 +};
438 +
439 +static struct clk_branch gsbi5_uart_clk = {
440 + .halt_reg = 0x2fd0,
441 + .halt_bit = 22,
442 + .clkr = {
443 + .enable_reg = 0x2a54,
444 + .enable_mask = BIT(9),
445 + .hw.init = &(struct clk_init_data){
446 + .name = "gsbi5_uart_clk",
447 + .parent_names = (const char *[]){
448 + "gsbi5_uart_src",
449 + },
450 + .num_parents = 1,
451 + .ops = &clk_branch_ops,
452 + .flags = CLK_SET_RATE_PARENT,
453 + },
454 + },
455 +};
456 +
457 +static struct clk_rcg gsbi6_uart_src = {
458 + .ns_reg = 0x2a74,
459 + .md_reg = 0x2a70,
460 + .mn = {
461 + .mnctr_en_bit = 8,
462 + .mnctr_reset_bit = 7,
463 + .mnctr_mode_shift = 5,
464 + .n_val_shift = 16,
465 + .m_val_shift = 16,
466 + .width = 16,
467 + },
468 + .p = {
469 + .pre_div_shift = 3,
470 + .pre_div_width = 2,
471 + },
472 + .s = {
473 + .src_sel_shift = 0,
474 + .parent_map = gcc_pxo_pll8_map,
475 + },
476 + .freq_tbl = clk_tbl_gsbi_uart,
477 + .clkr = {
478 + .enable_reg = 0x2a74,
479 + .enable_mask = BIT(11),
480 + .hw.init = &(struct clk_init_data){
481 + .name = "gsbi6_uart_src",
482 + .parent_names = gcc_pxo_pll8,
483 + .num_parents = 2,
484 + .ops = &clk_rcg_ops,
485 + .flags = CLK_SET_PARENT_GATE,
486 + },
487 + },
488 +};
489 +
490 +static struct clk_branch gsbi6_uart_clk = {
491 + .halt_reg = 0x2fd0,
492 + .halt_bit = 18,
493 + .clkr = {
494 + .enable_reg = 0x2a74,
495 + .enable_mask = BIT(9),
496 + .hw.init = &(struct clk_init_data){
497 + .name = "gsbi6_uart_clk",
498 + .parent_names = (const char *[]){
499 + "gsbi6_uart_src",
500 + },
501 + .num_parents = 1,
502 + .ops = &clk_branch_ops,
503 + .flags = CLK_SET_RATE_PARENT,
504 + },
505 + },
506 +};
507 +
508 +static struct clk_rcg gsbi7_uart_src = {
509 + .ns_reg = 0x2a94,
510 + .md_reg = 0x2a90,
511 + .mn = {
512 + .mnctr_en_bit = 8,
513 + .mnctr_reset_bit = 7,
514 + .mnctr_mode_shift = 5,
515 + .n_val_shift = 16,
516 + .m_val_shift = 16,
517 + .width = 16,
518 + },
519 + .p = {
520 + .pre_div_shift = 3,
521 + .pre_div_width = 2,
522 + },
523 + .s = {
524 + .src_sel_shift = 0,
525 + .parent_map = gcc_pxo_pll8_map,
526 + },
527 + .freq_tbl = clk_tbl_gsbi_uart,
528 + .clkr = {
529 + .enable_reg = 0x2a94,
530 + .enable_mask = BIT(11),
531 + .hw.init = &(struct clk_init_data){
532 + .name = "gsbi7_uart_src",
533 + .parent_names = gcc_pxo_pll8,
534 + .num_parents = 2,
535 + .ops = &clk_rcg_ops,
536 + .flags = CLK_SET_PARENT_GATE,
537 + },
538 + },
539 +};
540 +
541 +static struct clk_branch gsbi7_uart_clk = {
542 + .halt_reg = 0x2fd0,
543 + .halt_bit = 14,
544 + .clkr = {
545 + .enable_reg = 0x2a94,
546 + .enable_mask = BIT(9),
547 + .hw.init = &(struct clk_init_data){
548 + .name = "gsbi7_uart_clk",
549 + .parent_names = (const char *[]){
550 + "gsbi7_uart_src",
551 + },
552 + .num_parents = 1,
553 + .ops = &clk_branch_ops,
554 + .flags = CLK_SET_RATE_PARENT,
555 + },
556 + },
557 +};
558 +
559 +static struct freq_tbl clk_tbl_gsbi_qup[] = {
560 + { 1100000, P_PXO, 1, 2, 49 },
561 + { 5400000, P_PXO, 1, 1, 5 },
562 + { 10800000, P_PXO, 1, 2, 5 },
563 + { 15060000, P_PLL8, 1, 2, 51 },
564 + { 24000000, P_PLL8, 4, 1, 4 },
565 + { 25600000, P_PLL8, 1, 1, 15 },
566 + { 27000000, P_PXO, 1, 0, 0 },
567 + { 48000000, P_PLL8, 4, 1, 2 },
568 + { 51200000, P_PLL8, 1, 2, 15 },
569 + { }
570 +};
571 +
572 +static struct clk_rcg gsbi1_qup_src = {
573 + .ns_reg = 0x29cc,
574 + .md_reg = 0x29c8,
575 + .mn = {
576 + .mnctr_en_bit = 8,
577 + .mnctr_reset_bit = 7,
578 + .mnctr_mode_shift = 5,
579 + .n_val_shift = 16,
580 + .m_val_shift = 16,
581 + .width = 8,
582 + },
583 + .p = {
584 + .pre_div_shift = 3,
585 + .pre_div_width = 2,
586 + },
587 + .s = {
588 + .src_sel_shift = 0,
589 + .parent_map = gcc_pxo_pll8_map,
590 + },
591 + .freq_tbl = clk_tbl_gsbi_qup,
592 + .clkr = {
593 + .enable_reg = 0x29cc,
594 + .enable_mask = BIT(11),
595 + .hw.init = &(struct clk_init_data){
596 + .name = "gsbi1_qup_src",
597 + .parent_names = gcc_pxo_pll8,
598 + .num_parents = 2,
599 + .ops = &clk_rcg_ops,
600 + .flags = CLK_SET_PARENT_GATE,
601 + },
602 + },
603 +};
604 +
605 +static struct clk_branch gsbi1_qup_clk = {
606 + .halt_reg = 0x2fcc,
607 + .halt_bit = 11,
608 + .clkr = {
609 + .enable_reg = 0x29cc,
610 + .enable_mask = BIT(9),
611 + .hw.init = &(struct clk_init_data){
612 + .name = "gsbi1_qup_clk",
613 + .parent_names = (const char *[]){ "gsbi1_qup_src" },
614 + .num_parents = 1,
615 + .ops = &clk_branch_ops,
616 + .flags = CLK_SET_RATE_PARENT,
617 + },
618 + },
619 +};
620 +
621 +static struct clk_rcg gsbi2_qup_src = {
622 + .ns_reg = 0x29ec,
623 + .md_reg = 0x29e8,
624 + .mn = {
625 + .mnctr_en_bit = 8,
626 + .mnctr_reset_bit = 7,
627 + .mnctr_mode_shift = 5,
628 + .n_val_shift = 16,
629 + .m_val_shift = 16,
630 + .width = 8,
631 + },
632 + .p = {
633 + .pre_div_shift = 3,
634 + .pre_div_width = 2,
635 + },
636 + .s = {
637 + .src_sel_shift = 0,
638 + .parent_map = gcc_pxo_pll8_map,
639 + },
640 + .freq_tbl = clk_tbl_gsbi_qup,
641 + .clkr = {
642 + .enable_reg = 0x29ec,
643 + .enable_mask = BIT(11),
644 + .hw.init = &(struct clk_init_data){
645 + .name = "gsbi2_qup_src",
646 + .parent_names = gcc_pxo_pll8,
647 + .num_parents = 2,
648 + .ops = &clk_rcg_ops,
649 + .flags = CLK_SET_PARENT_GATE,
650 + },
651 + },
652 +};
653 +
654 +static struct clk_branch gsbi2_qup_clk = {
655 + .halt_reg = 0x2fcc,
656 + .halt_bit = 6,
657 + .clkr = {
658 + .enable_reg = 0x29ec,
659 + .enable_mask = BIT(9),
660 + .hw.init = &(struct clk_init_data){
661 + .name = "gsbi2_qup_clk",
662 + .parent_names = (const char *[]){ "gsbi2_qup_src" },
663 + .num_parents = 1,
664 + .ops = &clk_branch_ops,
665 + .flags = CLK_SET_RATE_PARENT,
666 + },
667 + },
668 +};
669 +
670 +static struct clk_rcg gsbi4_qup_src = {
671 + .ns_reg = 0x2a2c,
672 + .md_reg = 0x2a28,
673 + .mn = {
674 + .mnctr_en_bit = 8,
675 + .mnctr_reset_bit = 7,
676 + .mnctr_mode_shift = 5,
677 + .n_val_shift = 16,
678 + .m_val_shift = 16,
679 + .width = 8,
680 + },
681 + .p = {
682 + .pre_div_shift = 3,
683 + .pre_div_width = 2,
684 + },
685 + .s = {
686 + .src_sel_shift = 0,
687 + .parent_map = gcc_pxo_pll8_map,
688 + },
689 + .freq_tbl = clk_tbl_gsbi_qup,
690 + .clkr = {
691 + .enable_reg = 0x2a2c,
692 + .enable_mask = BIT(11),
693 + .hw.init = &(struct clk_init_data){
694 + .name = "gsbi4_qup_src",
695 + .parent_names = gcc_pxo_pll8,
696 + .num_parents = 2,
697 + .ops = &clk_rcg_ops,
698 + .flags = CLK_SET_PARENT_GATE,
699 + },
700 + },
701 +};
702 +
703 +static struct clk_branch gsbi4_qup_clk = {
704 + .halt_reg = 0x2fd0,
705 + .halt_bit = 24,
706 + .clkr = {
707 + .enable_reg = 0x2a2c,
708 + .enable_mask = BIT(9),
709 + .hw.init = &(struct clk_init_data){
710 + .name = "gsbi4_qup_clk",
711 + .parent_names = (const char *[]){ "gsbi4_qup_src" },
712 + .num_parents = 1,
713 + .ops = &clk_branch_ops,
714 + .flags = CLK_SET_RATE_PARENT,
715 + },
716 + },
717 +};
718 +
719 +static struct clk_rcg gsbi5_qup_src = {
720 + .ns_reg = 0x2a4c,
721 + .md_reg = 0x2a48,
722 + .mn = {
723 + .mnctr_en_bit = 8,
724 + .mnctr_reset_bit = 7,
725 + .mnctr_mode_shift = 5,
726 + .n_val_shift = 16,
727 + .m_val_shift = 16,
728 + .width = 8,
729 + },
730 + .p = {
731 + .pre_div_shift = 3,
732 + .pre_div_width = 2,
733 + },
734 + .s = {
735 + .src_sel_shift = 0,
736 + .parent_map = gcc_pxo_pll8_map,
737 + },
738 + .freq_tbl = clk_tbl_gsbi_qup,
739 + .clkr = {
740 + .enable_reg = 0x2a4c,
741 + .enable_mask = BIT(11),
742 + .hw.init = &(struct clk_init_data){
743 + .name = "gsbi5_qup_src",
744 + .parent_names = gcc_pxo_pll8,
745 + .num_parents = 2,
746 + .ops = &clk_rcg_ops,
747 + .flags = CLK_SET_PARENT_GATE,
748 + },
749 + },
750 +};
751 +
752 +static struct clk_branch gsbi5_qup_clk = {
753 + .halt_reg = 0x2fd0,
754 + .halt_bit = 20,
755 + .clkr = {
756 + .enable_reg = 0x2a4c,
757 + .enable_mask = BIT(9),
758 + .hw.init = &(struct clk_init_data){
759 + .name = "gsbi5_qup_clk",
760 + .parent_names = (const char *[]){ "gsbi5_qup_src" },
761 + .num_parents = 1,
762 + .ops = &clk_branch_ops,
763 + .flags = CLK_SET_RATE_PARENT,
764 + },
765 + },
766 +};
767 +
768 +static struct clk_rcg gsbi6_qup_src = {
769 + .ns_reg = 0x2a6c,
770 + .md_reg = 0x2a68,
771 + .mn = {
772 + .mnctr_en_bit = 8,
773 + .mnctr_reset_bit = 7,
774 + .mnctr_mode_shift = 5,
775 + .n_val_shift = 16,
776 + .m_val_shift = 16,
777 + .width = 8,
778 + },
779 + .p = {
780 + .pre_div_shift = 3,
781 + .pre_div_width = 2,
782 + },
783 + .s = {
784 + .src_sel_shift = 0,
785 + .parent_map = gcc_pxo_pll8_map,
786 + },
787 + .freq_tbl = clk_tbl_gsbi_qup,
788 + .clkr = {
789 + .enable_reg = 0x2a6c,
790 + .enable_mask = BIT(11),
791 + .hw.init = &(struct clk_init_data){
792 + .name = "gsbi6_qup_src",
793 + .parent_names = gcc_pxo_pll8,
794 + .num_parents = 2,
795 + .ops = &clk_rcg_ops,
796 + .flags = CLK_SET_PARENT_GATE,
797 + },
798 + },
799 +};
800 +
801 +static struct clk_branch gsbi6_qup_clk = {
802 + .halt_reg = 0x2fd0,
803 + .halt_bit = 16,
804 + .clkr = {
805 + .enable_reg = 0x2a6c,
806 + .enable_mask = BIT(9),
807 + .hw.init = &(struct clk_init_data){
808 + .name = "gsbi6_qup_clk",
809 + .parent_names = (const char *[]){ "gsbi6_qup_src" },
810 + .num_parents = 1,
811 + .ops = &clk_branch_ops,
812 + .flags = CLK_SET_RATE_PARENT,
813 + },
814 + },
815 +};
816 +
817 +static struct clk_rcg gsbi7_qup_src = {
818 + .ns_reg = 0x2a8c,
819 + .md_reg = 0x2a88,
820 + .mn = {
821 + .mnctr_en_bit = 8,
822 + .mnctr_reset_bit = 7,
823 + .mnctr_mode_shift = 5,
824 + .n_val_shift = 16,
825 + .m_val_shift = 16,
826 + .width = 8,
827 + },
828 + .p = {
829 + .pre_div_shift = 3,
830 + .pre_div_width = 2,
831 + },
832 + .s = {
833 + .src_sel_shift = 0,
834 + .parent_map = gcc_pxo_pll8_map,
835 + },
836 + .freq_tbl = clk_tbl_gsbi_qup,
837 + .clkr = {
838 + .enable_reg = 0x2a8c,
839 + .enable_mask = BIT(11),
840 + .hw.init = &(struct clk_init_data){
841 + .name = "gsbi7_qup_src",
842 + .parent_names = gcc_pxo_pll8,
843 + .num_parents = 2,
844 + .ops = &clk_rcg_ops,
845 + .flags = CLK_SET_PARENT_GATE,
846 + },
847 + },
848 +};
849 +
850 +static struct clk_branch gsbi7_qup_clk = {
851 + .halt_reg = 0x2fd0,
852 + .halt_bit = 12,
853 + .clkr = {
854 + .enable_reg = 0x2a8c,
855 + .enable_mask = BIT(9),
856 + .hw.init = &(struct clk_init_data){
857 + .name = "gsbi7_qup_clk",
858 + .parent_names = (const char *[]){ "gsbi7_qup_src" },
859 + .num_parents = 1,
860 + .ops = &clk_branch_ops,
861 + .flags = CLK_SET_RATE_PARENT,
862 + },
863 + },
864 +};
865 +
866 +static struct clk_branch gsbi1_h_clk = {
867 + .hwcg_reg = 0x29c0,
868 + .hwcg_bit = 6,
869 + .halt_reg = 0x2fcc,
870 + .halt_bit = 13,
871 + .clkr = {
872 + .enable_reg = 0x29c0,
873 + .enable_mask = BIT(4),
874 + .hw.init = &(struct clk_init_data){
875 + .name = "gsbi1_h_clk",
876 + .ops = &clk_branch_ops,
877 + .flags = CLK_IS_ROOT,
878 + },
879 + },
880 +};
881 +
882 +static struct clk_branch gsbi2_h_clk = {
883 + .hwcg_reg = 0x29e0,
884 + .hwcg_bit = 6,
885 + .halt_reg = 0x2fcc,
886 + .halt_bit = 9,
887 + .clkr = {
888 + .enable_reg = 0x29e0,
889 + .enable_mask = BIT(4),
890 + .hw.init = &(struct clk_init_data){
891 + .name = "gsbi2_h_clk",
892 + .ops = &clk_branch_ops,
893 + .flags = CLK_IS_ROOT,
894 + },
895 + },
896 +};
897 +
898 +static struct clk_branch gsbi4_h_clk = {
899 + .hwcg_reg = 0x2a20,
900 + .hwcg_bit = 6,
901 + .halt_reg = 0x2fd0,
902 + .halt_bit = 27,
903 + .clkr = {
904 + .enable_reg = 0x2a20,
905 + .enable_mask = BIT(4),
906 + .hw.init = &(struct clk_init_data){
907 + .name = "gsbi4_h_clk",
908 + .ops = &clk_branch_ops,
909 + .flags = CLK_IS_ROOT,
910 + },
911 + },
912 +};
913 +
914 +static struct clk_branch gsbi5_h_clk = {
915 + .hwcg_reg = 0x2a40,
916 + .hwcg_bit = 6,
917 + .halt_reg = 0x2fd0,
918 + .halt_bit = 23,
919 + .clkr = {
920 + .enable_reg = 0x2a40,
921 + .enable_mask = BIT(4),
922 + .hw.init = &(struct clk_init_data){
923 + .name = "gsbi5_h_clk",
924 + .ops = &clk_branch_ops,
925 + .flags = CLK_IS_ROOT,
926 + },
927 + },
928 +};
929 +
930 +static struct clk_branch gsbi6_h_clk = {
931 + .hwcg_reg = 0x2a60,
932 + .hwcg_bit = 6,
933 + .halt_reg = 0x2fd0,
934 + .halt_bit = 19,
935 + .clkr = {
936 + .enable_reg = 0x2a60,
937 + .enable_mask = BIT(4),
938 + .hw.init = &(struct clk_init_data){
939 + .name = "gsbi6_h_clk",
940 + .ops = &clk_branch_ops,
941 + .flags = CLK_IS_ROOT,
942 + },
943 + },
944 +};
945 +
946 +static struct clk_branch gsbi7_h_clk = {
947 + .hwcg_reg = 0x2a80,
948 + .hwcg_bit = 6,
949 + .halt_reg = 0x2fd0,
950 + .halt_bit = 15,
951 + .clkr = {
952 + .enable_reg = 0x2a80,
953 + .enable_mask = BIT(4),
954 + .hw.init = &(struct clk_init_data){
955 + .name = "gsbi7_h_clk",
956 + .ops = &clk_branch_ops,
957 + .flags = CLK_IS_ROOT,
958 + },
959 + },
960 +};
961 +
962 +static const struct freq_tbl clk_tbl_gp[] = {
963 + { 12500000, P_PXO, 2, 0, 0 },
964 + { 25000000, P_PXO, 1, 0, 0 },
965 + { 64000000, P_PLL8, 2, 1, 3 },
966 + { 76800000, P_PLL8, 1, 1, 5 },
967 + { 96000000, P_PLL8, 4, 0, 0 },
968 + { 128000000, P_PLL8, 3, 0, 0 },
969 + { 192000000, P_PLL8, 2, 0, 0 },
970 + { }
971 +};
972 +
973 +static struct clk_rcg gp0_src = {
974 + .ns_reg = 0x2d24,
975 + .md_reg = 0x2d00,
976 + .mn = {
977 + .mnctr_en_bit = 8,
978 + .mnctr_reset_bit = 7,
979 + .mnctr_mode_shift = 5,
980 + .n_val_shift = 16,
981 + .m_val_shift = 16,
982 + .width = 8,
983 + },
984 + .p = {
985 + .pre_div_shift = 3,
986 + .pre_div_width = 2,
987 + },
988 + .s = {
989 + .src_sel_shift = 0,
990 + .parent_map = gcc_pxo_pll8_cxo_map,
991 + },
992 + .freq_tbl = clk_tbl_gp,
993 + .clkr = {
994 + .enable_reg = 0x2d24,
995 + .enable_mask = BIT(11),
996 + .hw.init = &(struct clk_init_data){
997 + .name = "gp0_src",
998 + .parent_names = gcc_pxo_pll8_cxo,
999 + .num_parents = 3,
1000 + .ops = &clk_rcg_ops,
1001 + .flags = CLK_SET_PARENT_GATE,
1002 + },
1003 + }
1004 +};
1005 +
1006 +static struct clk_branch gp0_clk = {
1007 + .halt_reg = 0x2fd8,
1008 + .halt_bit = 7,
1009 + .clkr = {
1010 + .enable_reg = 0x2d24,
1011 + .enable_mask = BIT(9),
1012 + .hw.init = &(struct clk_init_data){
1013 + .name = "gp0_clk",
1014 + .parent_names = (const char *[]){ "gp0_src" },
1015 + .num_parents = 1,
1016 + .ops = &clk_branch_ops,
1017 + .flags = CLK_SET_RATE_PARENT,
1018 + },
1019 + },
1020 +};
1021 +
1022 +static struct clk_rcg gp1_src = {
1023 + .ns_reg = 0x2d44,
1024 + .md_reg = 0x2d40,
1025 + .mn = {
1026 + .mnctr_en_bit = 8,
1027 + .mnctr_reset_bit = 7,
1028 + .mnctr_mode_shift = 5,
1029 + .n_val_shift = 16,
1030 + .m_val_shift = 16,
1031 + .width = 8,
1032 + },
1033 + .p = {
1034 + .pre_div_shift = 3,
1035 + .pre_div_width = 2,
1036 + },
1037 + .s = {
1038 + .src_sel_shift = 0,
1039 + .parent_map = gcc_pxo_pll8_cxo_map,
1040 + },
1041 + .freq_tbl = clk_tbl_gp,
1042 + .clkr = {
1043 + .enable_reg = 0x2d44,
1044 + .enable_mask = BIT(11),
1045 + .hw.init = &(struct clk_init_data){
1046 + .name = "gp1_src",
1047 + .parent_names = gcc_pxo_pll8_cxo,
1048 + .num_parents = 3,
1049 + .ops = &clk_rcg_ops,
1050 + .flags = CLK_SET_RATE_GATE,
1051 + },
1052 + }
1053 +};
1054 +
1055 +static struct clk_branch gp1_clk = {
1056 + .halt_reg = 0x2fd8,
1057 + .halt_bit = 6,
1058 + .clkr = {
1059 + .enable_reg = 0x2d44,
1060 + .enable_mask = BIT(9),
1061 + .hw.init = &(struct clk_init_data){
1062 + .name = "gp1_clk",
1063 + .parent_names = (const char *[]){ "gp1_src" },
1064 + .num_parents = 1,
1065 + .ops = &clk_branch_ops,
1066 + .flags = CLK_SET_RATE_PARENT,
1067 + },
1068 + },
1069 +};
1070 +
1071 +static struct clk_rcg gp2_src = {
1072 + .ns_reg = 0x2d64,
1073 + .md_reg = 0x2d60,
1074 + .mn = {
1075 + .mnctr_en_bit = 8,
1076 + .mnctr_reset_bit = 7,
1077 + .mnctr_mode_shift = 5,
1078 + .n_val_shift = 16,
1079 + .m_val_shift = 16,
1080 + .width = 8,
1081 + },
1082 + .p = {
1083 + .pre_div_shift = 3,
1084 + .pre_div_width = 2,
1085 + },
1086 + .s = {
1087 + .src_sel_shift = 0,
1088 + .parent_map = gcc_pxo_pll8_cxo_map,
1089 + },
1090 + .freq_tbl = clk_tbl_gp,
1091 + .clkr = {
1092 + .enable_reg = 0x2d64,
1093 + .enable_mask = BIT(11),
1094 + .hw.init = &(struct clk_init_data){
1095 + .name = "gp2_src",
1096 + .parent_names = gcc_pxo_pll8_cxo,
1097 + .num_parents = 3,
1098 + .ops = &clk_rcg_ops,
1099 + .flags = CLK_SET_RATE_GATE,
1100 + },
1101 + }
1102 +};
1103 +
1104 +static struct clk_branch gp2_clk = {
1105 + .halt_reg = 0x2fd8,
1106 + .halt_bit = 5,
1107 + .clkr = {
1108 + .enable_reg = 0x2d64,
1109 + .enable_mask = BIT(9),
1110 + .hw.init = &(struct clk_init_data){
1111 + .name = "gp2_clk",
1112 + .parent_names = (const char *[]){ "gp2_src" },
1113 + .num_parents = 1,
1114 + .ops = &clk_branch_ops,
1115 + .flags = CLK_SET_RATE_PARENT,
1116 + },
1117 + },
1118 +};
1119 +
1120 +static struct clk_branch pmem_clk = {
1121 + .hwcg_reg = 0x25a0,
1122 + .hwcg_bit = 6,
1123 + .halt_reg = 0x2fc8,
1124 + .halt_bit = 20,
1125 + .clkr = {
1126 + .enable_reg = 0x25a0,
1127 + .enable_mask = BIT(4),
1128 + .hw.init = &(struct clk_init_data){
1129 + .name = "pmem_clk",
1130 + .ops = &clk_branch_ops,
1131 + .flags = CLK_IS_ROOT,
1132 + },
1133 + },
1134 +};
1135 +
1136 +static struct clk_rcg prng_src = {
1137 + .ns_reg = 0x2e80,
1138 + .p = {
1139 + .pre_div_shift = 3,
1140 + .pre_div_width = 4,
1141 + },
1142 + .s = {
1143 + .src_sel_shift = 0,
1144 + .parent_map = gcc_pxo_pll8_map,
1145 + },
1146 + .clkr = {
1147 + .hw.init = &(struct clk_init_data){
1148 + .name = "prng_src",
1149 + .parent_names = gcc_pxo_pll8,
1150 + .num_parents = 2,
1151 + .ops = &clk_rcg_ops,
1152 + },
1153 + },
1154 +};
1155 +
1156 +static struct clk_branch prng_clk = {
1157 + .halt_reg = 0x2fd8,
1158 + .halt_check = BRANCH_HALT_VOTED,
1159 + .halt_bit = 10,
1160 + .clkr = {
1161 + .enable_reg = 0x3080,
1162 + .enable_mask = BIT(10),
1163 + .hw.init = &(struct clk_init_data){
1164 + .name = "prng_clk",
1165 + .parent_names = (const char *[]){ "prng_src" },
1166 + .num_parents = 1,
1167 + .ops = &clk_branch_ops,
1168 + },
1169 + },
1170 +};
1171 +
1172 +static const struct freq_tbl clk_tbl_sdc[] = {
1173 + { 144000, P_PXO, 5, 18,625 },
1174 + { 400000, P_PLL8, 4, 1, 240 },
1175 + { 16000000, P_PLL8, 4, 1, 6 },
1176 + { 17070000, P_PLL8, 1, 2, 45 },
1177 + { 20210000, P_PLL8, 1, 1, 19 },
1178 + { 24000000, P_PLL8, 4, 1, 4 },
1179 + { 48000000, P_PLL8, 4, 1, 2 },
1180 + { 64000000, P_PLL8, 3, 1, 2 },
1181 + { 96000000, P_PLL8, 4, 0, 0 },
1182 + { 192000000, P_PLL8, 2, 0, 0 },
1183 + { }
1184 +};
1185 +
1186 +static struct clk_rcg sdc1_src = {
1187 + .ns_reg = 0x282c,
1188 + .md_reg = 0x2828,
1189 + .mn = {
1190 + .mnctr_en_bit = 8,
1191 + .mnctr_reset_bit = 7,
1192 + .mnctr_mode_shift = 5,
1193 + .n_val_shift = 16,
1194 + .m_val_shift = 16,
1195 + .width = 8,
1196 + },
1197 + .p = {
1198 + .pre_div_shift = 3,
1199 + .pre_div_width = 2,
1200 + },
1201 + .s = {
1202 + .src_sel_shift = 0,
1203 + .parent_map = gcc_pxo_pll8_map,
1204 + },
1205 + .freq_tbl = clk_tbl_sdc,
1206 + .clkr = {
1207 + .enable_reg = 0x282c,
1208 + .enable_mask = BIT(11),
1209 + .hw.init = &(struct clk_init_data){
1210 + .name = "sdc1_src",
1211 + .parent_names = gcc_pxo_pll8,
1212 + .num_parents = 2,
1213 + .ops = &clk_rcg_ops,
1214 + .flags = CLK_SET_RATE_GATE,
1215 + },
1216 + }
1217 +};
1218 +
1219 +static struct clk_branch sdc1_clk = {
1220 + .halt_reg = 0x2fc8,
1221 + .halt_bit = 6,
1222 + .clkr = {
1223 + .enable_reg = 0x282c,
1224 + .enable_mask = BIT(9),
1225 + .hw.init = &(struct clk_init_data){
1226 + .name = "sdc1_clk",
1227 + .parent_names = (const char *[]){ "sdc1_src" },
1228 + .num_parents = 1,
1229 + .ops = &clk_branch_ops,
1230 + .flags = CLK_SET_RATE_PARENT,
1231 + },
1232 + },
1233 +};
1234 +
1235 +static struct clk_rcg sdc3_src = {
1236 + .ns_reg = 0x286c,
1237 + .md_reg = 0x2868,
1238 + .mn = {
1239 + .mnctr_en_bit = 8,
1240 + .mnctr_reset_bit = 7,
1241 + .mnctr_mode_shift = 5,
1242 + .n_val_shift = 16,
1243 + .m_val_shift = 16,
1244 + .width = 8,
1245 + },
1246 + .p = {
1247 + .pre_div_shift = 3,
1248 + .pre_div_width = 2,
1249 + },
1250 + .s = {
1251 + .src_sel_shift = 0,
1252 + .parent_map = gcc_pxo_pll8_map,
1253 + },
1254 + .freq_tbl = clk_tbl_sdc,
1255 + .clkr = {
1256 + .enable_reg = 0x286c,
1257 + .enable_mask = BIT(11),
1258 + .hw.init = &(struct clk_init_data){
1259 + .name = "sdc3_src",
1260 + .parent_names = gcc_pxo_pll8,
1261 + .num_parents = 2,
1262 + .ops = &clk_rcg_ops,
1263 + .flags = CLK_SET_RATE_GATE,
1264 + },
1265 + }
1266 +};
1267 +
1268 +static struct clk_branch sdc3_clk = {
1269 + .halt_reg = 0x2fc8,
1270 + .halt_bit = 4,
1271 + .clkr = {
1272 + .enable_reg = 0x286c,
1273 + .enable_mask = BIT(9),
1274 + .hw.init = &(struct clk_init_data){
1275 + .name = "sdc3_clk",
1276 + .parent_names = (const char *[]){ "sdc3_src" },
1277 + .num_parents = 1,
1278 + .ops = &clk_branch_ops,
1279 + .flags = CLK_SET_RATE_PARENT,
1280 + },
1281 + },
1282 +};
1283 +
1284 +static struct clk_branch sdc1_h_clk = {
1285 + .hwcg_reg = 0x2820,
1286 + .hwcg_bit = 6,
1287 + .halt_reg = 0x2fc8,
1288 + .halt_bit = 11,
1289 + .clkr = {
1290 + .enable_reg = 0x2820,
1291 + .enable_mask = BIT(4),
1292 + .hw.init = &(struct clk_init_data){
1293 + .name = "sdc1_h_clk",
1294 + .ops = &clk_branch_ops,
1295 + .flags = CLK_IS_ROOT,
1296 + },
1297 + },
1298 +};
1299 +
1300 +static struct clk_branch sdc3_h_clk = {
1301 + .hwcg_reg = 0x2860,
1302 + .hwcg_bit = 6,
1303 + .halt_reg = 0x2fc8,
1304 + .halt_bit = 9,
1305 + .clkr = {
1306 + .enable_reg = 0x2860,
1307 + .enable_mask = BIT(4),
1308 + .hw.init = &(struct clk_init_data){
1309 + .name = "sdc3_h_clk",
1310 + .ops = &clk_branch_ops,
1311 + .flags = CLK_IS_ROOT,
1312 + },
1313 + },
1314 +};
1315 +
1316 +static const struct freq_tbl clk_tbl_tsif_ref[] = {
1317 + { 105000, P_PXO, 1, 1, 256 },
1318 + { }
1319 +};
1320 +
1321 +static struct clk_rcg tsif_ref_src = {
1322 + .ns_reg = 0x2710,
1323 + .md_reg = 0x270c,
1324 + .mn = {
1325 + .mnctr_en_bit = 8,
1326 + .mnctr_reset_bit = 7,
1327 + .mnctr_mode_shift = 5,
1328 + .n_val_shift = 16,
1329 + .m_val_shift = 16,
1330 + .width = 16,
1331 + },
1332 + .p = {
1333 + .pre_div_shift = 3,
1334 + .pre_div_width = 2,
1335 + },
1336 + .s = {
1337 + .src_sel_shift = 0,
1338 + .parent_map = gcc_pxo_pll8_map,
1339 + },
1340 + .freq_tbl = clk_tbl_tsif_ref,
1341 + .clkr = {
1342 + .enable_reg = 0x2710,
1343 + .enable_mask = BIT(11),
1344 + .hw.init = &(struct clk_init_data){
1345 + .name = "tsif_ref_src",
1346 + .parent_names = gcc_pxo_pll8,
1347 + .num_parents = 2,
1348 + .ops = &clk_rcg_ops,
1349 + .flags = CLK_SET_RATE_GATE,
1350 + },
1351 + }
1352 +};
1353 +
1354 +static struct clk_branch tsif_ref_clk = {
1355 + .halt_reg = 0x2fd4,
1356 + .halt_bit = 5,
1357 + .clkr = {
1358 + .enable_reg = 0x2710,
1359 + .enable_mask = BIT(9),
1360 + .hw.init = &(struct clk_init_data){
1361 + .name = "tsif_ref_clk",
1362 + .parent_names = (const char *[]){ "tsif_ref_src" },
1363 + .num_parents = 1,
1364 + .ops = &clk_branch_ops,
1365 + .flags = CLK_SET_RATE_PARENT,
1366 + },
1367 + },
1368 +};
1369 +
1370 +static struct clk_branch tsif_h_clk = {
1371 + .hwcg_reg = 0x2700,
1372 + .hwcg_bit = 6,
1373 + .halt_reg = 0x2fd4,
1374 + .halt_bit = 7,
1375 + .clkr = {
1376 + .enable_reg = 0x2700,
1377 + .enable_mask = BIT(4),
1378 + .hw.init = &(struct clk_init_data){
1379 + .name = "tsif_h_clk",
1380 + .ops = &clk_branch_ops,
1381 + .flags = CLK_IS_ROOT,
1382 + },
1383 + },
1384 +};
1385 +
1386 +static struct clk_branch dma_bam_h_clk = {
1387 + .hwcg_reg = 0x25c0,
1388 + .hwcg_bit = 6,
1389 + .halt_reg = 0x2fc8,
1390 + .halt_bit = 12,
1391 + .clkr = {
1392 + .enable_reg = 0x25c0,
1393 + .enable_mask = BIT(4),
1394 + .hw.init = &(struct clk_init_data){
1395 + .name = "dma_bam_h_clk",
1396 + .ops = &clk_branch_ops,
1397 + .flags = CLK_IS_ROOT,
1398 + },
1399 + },
1400 +};
1401 +
1402 +static struct clk_branch adm0_clk = {
1403 + .halt_reg = 0x2fdc,
1404 + .halt_check = BRANCH_HALT_VOTED,
1405 + .halt_bit = 12,
1406 + .clkr = {
1407 + .enable_reg = 0x3080,
1408 + .enable_mask = BIT(2),
1409 + .hw.init = &(struct clk_init_data){
1410 + .name = "adm0_clk",
1411 + .ops = &clk_branch_ops,
1412 + .flags = CLK_IS_ROOT,
1413 + },
1414 + },
1415 +};
1416 +
1417 +static struct clk_branch adm0_pbus_clk = {
1418 + .hwcg_reg = 0x2208,
1419 + .hwcg_bit = 6,
1420 + .halt_reg = 0x2fdc,
1421 + .halt_check = BRANCH_HALT_VOTED,
1422 + .halt_bit = 11,
1423 + .clkr = {
1424 + .enable_reg = 0x3080,
1425 + .enable_mask = BIT(3),
1426 + .hw.init = &(struct clk_init_data){
1427 + .name = "adm0_pbus_clk",
1428 + .ops = &clk_branch_ops,
1429 + .flags = CLK_IS_ROOT,
1430 + },
1431 + },
1432 +};
1433 +
1434 +static struct clk_branch pmic_arb0_h_clk = {
1435 + .halt_reg = 0x2fd8,
1436 + .halt_check = BRANCH_HALT_VOTED,
1437 + .halt_bit = 22,
1438 + .clkr = {
1439 + .enable_reg = 0x3080,
1440 + .enable_mask = BIT(8),
1441 + .hw.init = &(struct clk_init_data){
1442 + .name = "pmic_arb0_h_clk",
1443 + .ops = &clk_branch_ops,
1444 + .flags = CLK_IS_ROOT,
1445 + },
1446 + },
1447 +};
1448 +
1449 +static struct clk_branch pmic_arb1_h_clk = {
1450 + .halt_reg = 0x2fd8,
1451 + .halt_check = BRANCH_HALT_VOTED,
1452 + .halt_bit = 21,
1453 + .clkr = {
1454 + .enable_reg = 0x3080,
1455 + .enable_mask = BIT(9),
1456 + .hw.init = &(struct clk_init_data){
1457 + .name = "pmic_arb1_h_clk",
1458 + .ops = &clk_branch_ops,
1459 + .flags = CLK_IS_ROOT,
1460 + },
1461 + },
1462 +};
1463 +
1464 +static struct clk_branch pmic_ssbi2_clk = {
1465 + .halt_reg = 0x2fd8,
1466 + .halt_check = BRANCH_HALT_VOTED,
1467 + .halt_bit = 23,
1468 + .clkr = {
1469 + .enable_reg = 0x3080,
1470 + .enable_mask = BIT(7),
1471 + .hw.init = &(struct clk_init_data){
1472 + .name = "pmic_ssbi2_clk",
1473 + .ops = &clk_branch_ops,
1474 + .flags = CLK_IS_ROOT,
1475 + },
1476 + },
1477 +};
1478 +
1479 +static struct clk_branch rpm_msg_ram_h_clk = {
1480 + .hwcg_reg = 0x27e0,
1481 + .hwcg_bit = 6,
1482 + .halt_reg = 0x2fd8,
1483 + .halt_check = BRANCH_HALT_VOTED,
1484 + .halt_bit = 12,
1485 + .clkr = {
1486 + .enable_reg = 0x3080,
1487 + .enable_mask = BIT(6),
1488 + .hw.init = &(struct clk_init_data){
1489 + .name = "rpm_msg_ram_h_clk",
1490 + .ops = &clk_branch_ops,
1491 + .flags = CLK_IS_ROOT,
1492 + },
1493 + },
1494 +};
1495 +
1496 +static const struct freq_tbl clk_tbl_pcie_ref[] = {
1497 + { 100000000, P_PLL3, 12, 0, 0 },
1498 + { }
1499 +};
1500 +
1501 +static struct clk_rcg pcie_ref_src = {
1502 + .ns_reg = 0x3860,
1503 + .p = {
1504 + .pre_div_shift = 3,
1505 + .pre_div_width = 4,
1506 + },
1507 + .s = {
1508 + .src_sel_shift = 0,
1509 + .parent_map = gcc_pxo_pll3_map,
1510 + },
1511 + .freq_tbl = clk_tbl_pcie_ref,
1512 + .clkr = {
1513 + .enable_reg = 0x3860,
1514 + .enable_mask = BIT(11),
1515 + .hw.init = &(struct clk_init_data){
1516 + .name = "pcie_ref_src",
1517 + .parent_names = gcc_pxo_pll3,
1518 + .num_parents = 2,
1519 + .ops = &clk_rcg_ops,
1520 + .flags = CLK_SET_RATE_GATE,
1521 + },
1522 + },
1523 +};
1524 +
1525 +static struct clk_branch pcie_ref_src_clk = {
1526 + .halt_reg = 0x2fdc,
1527 + .halt_bit = 30,
1528 + .clkr = {
1529 + .enable_reg = 0x3860,
1530 + .enable_mask = BIT(9),
1531 + .hw.init = &(struct clk_init_data){
1532 + .name = "pcie_ref_src_clk",
1533 + .parent_names = (const char *[]){ "pcie_ref_src" },
1534 + .num_parents = 1,
1535 + .ops = &clk_branch_ops,
1536 + .flags = CLK_SET_RATE_PARENT,
1537 + },
1538 + },
1539 +};
1540 +
1541 +static struct clk_branch pcie_a_clk = {
1542 + .halt_reg = 0x2fc0,
1543 + .halt_bit = 13,
1544 + .clkr = {
1545 + .enable_reg = 0x22c0,
1546 + .enable_mask = BIT(4),
1547 + .hw.init = &(struct clk_init_data){
1548 + .name = "pcie_a_clk",
1549 + .ops = &clk_branch_ops,
1550 + .flags = CLK_IS_ROOT,
1551 + },
1552 + },
1553 +};
1554 +
1555 +static struct clk_branch pcie_aux_clk = {
1556 + .halt_reg = 0x2fdc,
1557 + .halt_bit = 31,
1558 + .clkr = {
1559 + .enable_reg = 0x22c8,
1560 + .enable_mask = BIT(4),
1561 + .hw.init = &(struct clk_init_data){
1562 + .name = "pcie_aux_clk",
1563 + .ops = &clk_branch_ops,
1564 + .flags = CLK_IS_ROOT,
1565 + },
1566 + },
1567 +};
1568 +
1569 +static struct clk_branch pcie_h_clk = {
1570 + .halt_reg = 0x2fd4,
1571 + .halt_bit = 8,
1572 + .clkr = {
1573 + .enable_reg = 0x22cc,
1574 + .enable_mask = BIT(4),
1575 + .hw.init = &(struct clk_init_data){
1576 + .name = "pcie_h_clk",
1577 + .ops = &clk_branch_ops,
1578 + .flags = CLK_IS_ROOT,
1579 + },
1580 + },
1581 +};
1582 +
1583 +static struct clk_branch pcie_phy_clk = {
1584 + .halt_reg = 0x2fdc,
1585 + .halt_bit = 29,
1586 + .clkr = {
1587 + .enable_reg = 0x22d0,
1588 + .enable_mask = BIT(4),
1589 + .hw.init = &(struct clk_init_data){
1590 + .name = "pcie_phy_clk",
1591 + .ops = &clk_branch_ops,
1592 + .flags = CLK_IS_ROOT,
1593 + },
1594 + },
1595 +};
1596 +
1597 +static struct clk_rcg pcie1_ref_src = {
1598 + .ns_reg = 0x3aa0,
1599 + .p = {
1600 + .pre_div_shift = 3,
1601 + .pre_div_width = 4,
1602 + },
1603 + .s = {
1604 + .src_sel_shift = 0,
1605 + .parent_map = gcc_pxo_pll3_map,
1606 + },
1607 + .freq_tbl = clk_tbl_pcie_ref,
1608 + .clkr = {
1609 + .enable_reg = 0x3aa0,
1610 + .enable_mask = BIT(11),
1611 + .hw.init = &(struct clk_init_data){
1612 + .name = "pcie1_ref_src",
1613 + .parent_names = gcc_pxo_pll3,
1614 + .num_parents = 2,
1615 + .ops = &clk_rcg_ops,
1616 + .flags = CLK_SET_RATE_GATE,
1617 + },
1618 + },
1619 +};
1620 +
1621 +static struct clk_branch pcie1_ref_src_clk = {
1622 + .halt_reg = 0x2fdc,
1623 + .halt_bit = 27,
1624 + .clkr = {
1625 + .enable_reg = 0x3aa0,
1626 + .enable_mask = BIT(9),
1627 + .hw.init = &(struct clk_init_data){
1628 + .name = "pcie1_ref_src_clk",
1629 + .parent_names = (const char *[]){ "pcie1_ref_src" },
1630 + .num_parents = 1,
1631 + .ops = &clk_branch_ops,
1632 + .flags = CLK_SET_RATE_PARENT,
1633 + },
1634 + },
1635 +};
1636 +
1637 +static struct clk_branch pcie1_a_clk = {
1638 + .halt_reg = 0x2fc0,
1639 + .halt_bit = 10,
1640 + .clkr = {
1641 + .enable_reg = 0x3a80,
1642 + .enable_mask = BIT(4),
1643 + .hw.init = &(struct clk_init_data){
1644 + .name = "pcie1_a_clk",
1645 + .ops = &clk_branch_ops,
1646 + .flags = CLK_IS_ROOT,
1647 + },
1648 + },
1649 +};
1650 +
1651 +static struct clk_branch pcie1_aux_clk = {
1652 + .halt_reg = 0x2fdc,
1653 + .halt_bit = 28,
1654 + .clkr = {
1655 + .enable_reg = 0x3a88,
1656 + .enable_mask = BIT(4),
1657 + .hw.init = &(struct clk_init_data){
1658 + .name = "pcie1_aux_clk",
1659 + .ops = &clk_branch_ops,
1660 + .flags = CLK_IS_ROOT,
1661 + },
1662 + },
1663 +};
1664 +
1665 +static struct clk_branch pcie1_h_clk = {
1666 + .halt_reg = 0x2fd4,
1667 + .halt_bit = 9,
1668 + .clkr = {
1669 + .enable_reg = 0x3a8c,
1670 + .enable_mask = BIT(4),
1671 + .hw.init = &(struct clk_init_data){
1672 + .name = "pcie1_h_clk",
1673 + .ops = &clk_branch_ops,
1674 + .flags = CLK_IS_ROOT,
1675 + },
1676 + },
1677 +};
1678 +
1679 +static struct clk_branch pcie1_phy_clk = {
1680 + .halt_reg = 0x2fdc,
1681 + .halt_bit = 26,
1682 + .clkr = {
1683 + .enable_reg = 0x3a90,
1684 + .enable_mask = BIT(4),
1685 + .hw.init = &(struct clk_init_data){
1686 + .name = "pcie1_phy_clk",
1687 + .ops = &clk_branch_ops,
1688 + .flags = CLK_IS_ROOT,
1689 + },
1690 + },
1691 +};
1692 +
1693 +static struct clk_rcg pcie2_ref_src = {
1694 + .ns_reg = 0x3ae0,
1695 + .p = {
1696 + .pre_div_shift = 3,
1697 + .pre_div_width = 4,
1698 + },
1699 + .s = {
1700 + .src_sel_shift = 0,
1701 + .parent_map = gcc_pxo_pll3_map,
1702 + },
1703 + .freq_tbl = clk_tbl_pcie_ref,
1704 + .clkr = {
1705 + .enable_reg = 0x3ae0,
1706 + .enable_mask = BIT(11),
1707 + .hw.init = &(struct clk_init_data){
1708 + .name = "pcie2_ref_src",
1709 + .parent_names = gcc_pxo_pll3,
1710 + .num_parents = 2,
1711 + .ops = &clk_rcg_ops,
1712 + .flags = CLK_SET_RATE_GATE,
1713 + },
1714 + },
1715 +};
1716 +
1717 +static struct clk_branch pcie2_ref_src_clk = {
1718 + .halt_reg = 0x2fdc,
1719 + .halt_bit = 24,
1720 + .clkr = {
1721 + .enable_reg = 0x3ae0,
1722 + .enable_mask = BIT(9),
1723 + .hw.init = &(struct clk_init_data){
1724 + .name = "pcie2_ref_src_clk",
1725 + .parent_names = (const char *[]){ "pcie2_ref_src" },
1726 + .num_parents = 1,
1727 + .ops = &clk_branch_ops,
1728 + .flags = CLK_SET_RATE_PARENT,
1729 + },
1730 + },
1731 +};
1732 +
1733 +static struct clk_branch pcie2_a_clk = {
1734 + .halt_reg = 0x2fc0,
1735 + .halt_bit = 9,
1736 + .clkr = {
1737 + .enable_reg = 0x3ac0,
1738 + .enable_mask = BIT(4),
1739 + .hw.init = &(struct clk_init_data){
1740 + .name = "pcie2_a_clk",
1741 + .ops = &clk_branch_ops,
1742 + .flags = CLK_IS_ROOT,
1743 + },
1744 + },
1745 +};
1746 +
1747 +static struct clk_branch pcie2_aux_clk = {
1748 + .halt_reg = 0x2fdc,
1749 + .halt_bit = 25,
1750 + .clkr = {
1751 + .enable_reg = 0x3ac8,
1752 + .enable_mask = BIT(4),
1753 + .hw.init = &(struct clk_init_data){
1754 + .name = "pcie2_aux_clk",
1755 + .ops = &clk_branch_ops,
1756 + .flags = CLK_IS_ROOT,
1757 + },
1758 + },
1759 +};
1760 +
1761 +static struct clk_branch pcie2_h_clk = {
1762 + .halt_reg = 0x2fd4,
1763 + .halt_bit = 10,
1764 + .clkr = {
1765 + .enable_reg = 0x3acc,
1766 + .enable_mask = BIT(4),
1767 + .hw.init = &(struct clk_init_data){
1768 + .name = "pcie2_h_clk",
1769 + .ops = &clk_branch_ops,
1770 + .flags = CLK_IS_ROOT,
1771 + },
1772 + },
1773 +};
1774 +
1775 +static struct clk_branch pcie2_phy_clk = {
1776 + .halt_reg = 0x2fdc,
1777 + .halt_bit = 23,
1778 + .clkr = {
1779 + .enable_reg = 0x3ad0,
1780 + .enable_mask = BIT(4),
1781 + .hw.init = &(struct clk_init_data){
1782 + .name = "pcie2_phy_clk",
1783 + .ops = &clk_branch_ops,
1784 + .flags = CLK_IS_ROOT,
1785 + },
1786 + },
1787 +};
1788 +
1789 +static const struct freq_tbl clk_tbl_sata_ref[] = {
1790 + { 100000000, P_PLL3, 12, 0, 0 },
1791 + { }
1792 +};
1793 +
1794 +static struct clk_rcg sata_ref_src = {
1795 + .ns_reg = 0x2c08,
1796 + .p = {
1797 + .pre_div_shift = 3,
1798 + .pre_div_width = 4,
1799 + },
1800 + .s = {
1801 + .src_sel_shift = 0,
1802 + .parent_map = gcc_pxo_pll3_sata_map,
1803 + },
1804 + .freq_tbl = clk_tbl_sata_ref,
1805 + .clkr = {
1806 + .enable_reg = 0x2c08,
1807 + .enable_mask = BIT(7),
1808 + .hw.init = &(struct clk_init_data){
1809 + .name = "sata_ref_src",
1810 + .parent_names = gcc_pxo_pll3,
1811 + .num_parents = 2,
1812 + .ops = &clk_rcg_ops,
1813 + .flags = CLK_SET_RATE_GATE,
1814 + },
1815 + },
1816 +};
1817 +
1818 +static struct clk_branch sata_rxoob_clk = {
1819 + .halt_reg = 0x2fdc,
1820 + .halt_bit = 20,
1821 + .clkr = {
1822 + .enable_reg = 0x2c0c,
1823 + .enable_mask = BIT(4),
1824 + .hw.init = &(struct clk_init_data){
1825 + .name = "sata_rxoob_clk",
1826 + .parent_names = (const char *[]){ "sata_ref_src" },
1827 + .num_parents = 1,
1828 + .ops = &clk_branch_ops,
1829 + .flags = CLK_SET_RATE_PARENT,
1830 + },
1831 + },
1832 +};
1833 +
1834 +static struct clk_branch sata_pmalive_clk = {
1835 + .halt_reg = 0x2fdc,
1836 + .halt_bit = 19,
1837 + .clkr = {
1838 + .enable_reg = 0x2c10,
1839 + .enable_mask = BIT(4),
1840 + .hw.init = &(struct clk_init_data){
1841 + .name = "sata_pmalive_clk",
1842 + .parent_names = (const char *[]){ "sata_ref_src" },
1843 + .num_parents = 1,
1844 + .ops = &clk_branch_ops,
1845 + .flags = CLK_SET_RATE_PARENT,
1846 + },
1847 + },
1848 +};
1849 +
1850 +static struct clk_branch sata_phy_ref_clk = {
1851 + .halt_reg = 0x2fdc,
1852 + .halt_bit = 18,
1853 + .clkr = {
1854 + .enable_reg = 0x2c14,
1855 + .enable_mask = BIT(4),
1856 + .hw.init = &(struct clk_init_data){
1857 + .name = "sata_phy_ref_clk",
1858 + .parent_names = (const char *[]){ "pxo" },
1859 + .num_parents = 1,
1860 + .ops = &clk_branch_ops,
1861 + },
1862 + },
1863 +};
1864 +
1865 +static struct clk_branch sata_a_clk = {
1866 + .halt_reg = 0x2fc0,
1867 + .halt_bit = 12,
1868 + .clkr = {
1869 + .enable_reg = 0x2c20,
1870 + .enable_mask = BIT(4),
1871 + .hw.init = &(struct clk_init_data){
1872 + .name = "sata_a_clk",
1873 + .ops = &clk_branch_ops,
1874 + .flags = CLK_IS_ROOT,
1875 + },
1876 + },
1877 +};
1878 +
1879 +static struct clk_branch sata_h_clk = {
1880 + .halt_reg = 0x2fdc,
1881 + .halt_bit = 21,
1882 + .clkr = {
1883 + .enable_reg = 0x2c00,
1884 + .enable_mask = BIT(4),
1885 + .hw.init = &(struct clk_init_data){
1886 + .name = "sata_h_clk",
1887 + .ops = &clk_branch_ops,
1888 + .flags = CLK_IS_ROOT,
1889 + },
1890 + },
1891 +};
1892 +
1893 +static struct clk_branch sfab_sata_s_h_clk = {
1894 + .halt_reg = 0x2fc4,
1895 + .halt_bit = 14,
1896 + .clkr = {
1897 + .enable_reg = 0x2480,
1898 + .enable_mask = BIT(4),
1899 + .hw.init = &(struct clk_init_data){
1900 + .name = "sfab_sata_s_h_clk",
1901 + .ops = &clk_branch_ops,
1902 + .flags = CLK_IS_ROOT,
1903 + },
1904 + },
1905 +};
1906 +
1907 +static struct clk_branch sata_phy_cfg_clk = {
1908 + .halt_reg = 0x2fcc,
1909 + .halt_bit = 14,
1910 + .clkr = {
1911 + .enable_reg = 0x2c40,
1912 + .enable_mask = BIT(4),
1913 + .hw.init = &(struct clk_init_data){
1914 + .name = "sata_phy_cfg_clk",
1915 + .ops = &clk_branch_ops,
1916 + .flags = CLK_IS_ROOT,
1917 + },
1918 + },
1919 +};
1920 +
1921 +static const struct freq_tbl clk_tbl_usb30_master[] = {
1922 + { 125000000, P_PLL0, 1, 5, 32 },
1923 + { }
1924 +};
1925 +
1926 +static struct clk_rcg usb30_master_clk_src = {
1927 + .ns_reg = 0x3b2c,
1928 + .md_reg = 0x3b28,
1929 + .mn = {
1930 + .mnctr_en_bit = 8,
1931 + .mnctr_reset_bit = 7,
1932 + .mnctr_mode_shift = 5,
1933 + .n_val_shift = 16,
1934 + .m_val_shift = 16,
1935 + .width = 8,
1936 + },
1937 + .p = {
1938 + .pre_div_shift = 3,
1939 + .pre_div_width = 2,
1940 + },
1941 + .s = {
1942 + .src_sel_shift = 0,
1943 + .parent_map = gcc_pxo_pll8_pll0,
1944 + },
1945 + .freq_tbl = clk_tbl_usb30_master,
1946 + .clkr = {
1947 + .enable_reg = 0x3b2c,
1948 + .enable_mask = BIT(11),
1949 + .hw.init = &(struct clk_init_data){
1950 + .name = "usb30_master_ref_src",
1951 + .parent_names = gcc_pxo_pll8_pll0_map,
1952 + .num_parents = 3,
1953 + .ops = &clk_rcg_ops,
1954 + .flags = CLK_SET_RATE_GATE,
1955 + },
1956 + },
1957 +};
1958 +
1959 +static struct clk_branch usb30_0_branch_clk = {
1960 + .halt_reg = 0x2fc4,
1961 + .halt_bit = 22,
1962 + .clkr = {
1963 + .enable_reg = 0x3b24,
1964 + .enable_mask = BIT(4),
1965 + .hw.init = &(struct clk_init_data){
1966 + .name = "usb30_0_branch_clk",
1967 + .parent_names = (const char *[]){ "usb30_master_ref_src", },
1968 + .num_parents = 1,
1969 + .ops = &clk_branch_ops,
1970 + .flags = CLK_SET_RATE_PARENT,
1971 + },
1972 + },
1973 +};
1974 +
1975 +static struct clk_branch usb30_1_branch_clk = {
1976 + .halt_reg = 0x2fc4,
1977 + .halt_bit = 17,
1978 + .clkr = {
1979 + .enable_reg = 0x3b34,
1980 + .enable_mask = BIT(4),
1981 + .hw.init = &(struct clk_init_data){
1982 + .name = "usb30_1_branch_clk",
1983 + .parent_names = (const char *[]){ "usb30_master_ref_src", },
1984 + .num_parents = 1,
1985 + .ops = &clk_branch_ops,
1986 + .flags = CLK_SET_RATE_PARENT,
1987 + },
1988 + },
1989 +};
1990 +
1991 +static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1992 + { 60000000, P_PLL0, 1, 1, 40 },
1993 + { }
1994 +};
1995 +
1996 +static struct clk_rcg usb30_utmi_clk = {
1997 + .ns_reg = 0x3b44,
1998 + .md_reg = 0x3b40,
1999 + .mn = {
2000 + .mnctr_en_bit = 8,
2001 + .mnctr_reset_bit = 7,
2002 + .mnctr_mode_shift = 5,
2003 + .n_val_shift = 16,
2004 + .m_val_shift = 16,
2005 + .width = 8,
2006 + },
2007 + .p = {
2008 + .pre_div_shift = 3,
2009 + .pre_div_width = 2,
2010 + },
2011 + .s = {
2012 + .src_sel_shift = 0,
2013 + .parent_map = gcc_pxo_pll8_pll0,
2014 + },
2015 + .freq_tbl = clk_tbl_usb30_utmi,
2016 + .clkr = {
2017 + .enable_reg = 0x3b44,
2018 + .enable_mask = BIT(11),
2019 + .hw.init = &(struct clk_init_data){
2020 + .name = "usb30_utmi_clk",
2021 + .parent_names = gcc_pxo_pll8_pll0_map,
2022 + .num_parents = 3,
2023 + .ops = &clk_rcg_ops,
2024 + .flags = CLK_SET_RATE_GATE,
2025 + },
2026 + },
2027 +};
2028 +
2029 +static struct clk_branch usb30_0_utmi_clk_ctl = {
2030 + .halt_reg = 0x2fc4,
2031 + .halt_bit = 21,
2032 + .clkr = {
2033 + .enable_reg = 0x3b48,
2034 + .enable_mask = BIT(4),
2035 + .hw.init = &(struct clk_init_data){
2036 + .name = "usb30_0_utmi_clk_ctl",
2037 + .parent_names = (const char *[]){ "usb30_utmi_clk", },
2038 + .num_parents = 1,
2039 + .ops = &clk_branch_ops,
2040 + .flags = CLK_SET_RATE_PARENT,
2041 + },
2042 + },
2043 +};
2044 +
2045 +static struct clk_branch usb30_1_utmi_clk_ctl = {
2046 + .halt_reg = 0x2fc4,
2047 + .halt_bit = 15,
2048 + .clkr = {
2049 + .enable_reg = 0x3b4c,
2050 + .enable_mask = BIT(4),
2051 + .hw.init = &(struct clk_init_data){
2052 + .name = "usb30_1_utmi_clk_ctl",
2053 + .parent_names = (const char *[]){ "usb30_utmi_clk", },
2054 + .num_parents = 1,
2055 + .ops = &clk_branch_ops,
2056 + .flags = CLK_SET_RATE_PARENT,
2057 + },
2058 + },
2059 +};
2060 +
2061 +static const struct freq_tbl clk_tbl_usb[] = {
2062 + { 60000000, P_PLL8, 1, 5, 32 },
2063 + { }
2064 +};
2065 +
2066 +static struct clk_rcg usb_hs1_xcvr_clk_src = {
2067 + .ns_reg = 0x290C,
2068 + .md_reg = 0x2908,
2069 + .mn = {
2070 + .mnctr_en_bit = 8,
2071 + .mnctr_reset_bit = 7,
2072 + .mnctr_mode_shift = 5,
2073 + .n_val_shift = 16,
2074 + .m_val_shift = 16,
2075 + .width = 8,
2076 + },
2077 + .p = {
2078 + .pre_div_shift = 3,
2079 + .pre_div_width = 2,
2080 + },
2081 + .s = {
2082 + .src_sel_shift = 0,
2083 + .parent_map = gcc_pxo_pll8_pll0,
2084 + },
2085 + .freq_tbl = clk_tbl_usb,
2086 + .clkr = {
2087 + .enable_reg = 0x2968,
2088 + .enable_mask = BIT(11),
2089 + .hw.init = &(struct clk_init_data){
2090 + .name = "usb_hs1_xcvr_src",
2091 + .parent_names = gcc_pxo_pll8_pll0_map,
2092 + .num_parents = 3,
2093 + .ops = &clk_rcg_ops,
2094 + .flags = CLK_SET_RATE_GATE,
2095 + },
2096 + },
2097 +};
2098 +
2099 +static struct clk_branch usb_hs1_xcvr_clk = {
2100 + .halt_reg = 0x2fcc,
2101 + .halt_bit = 17,
2102 + .clkr = {
2103 + .enable_reg = 0x290c,
2104 + .enable_mask = BIT(9),
2105 + .hw.init = &(struct clk_init_data){
2106 + .name = "usb_hs1_xcvr_clk",
2107 + .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2108 + .num_parents = 1,
2109 + .ops = &clk_branch_ops,
2110 + .flags = CLK_SET_RATE_PARENT,
2111 + },
2112 + },
2113 +};
2114 +
2115 +static struct clk_branch usb_hs1_h_clk = {
2116 + .hwcg_reg = 0x2900,
2117 + .hwcg_bit = 6,
2118 + .halt_reg = 0x2fc8,
2119 + .halt_bit = 1,
2120 + .clkr = {
2121 + .enable_reg = 0x2900,
2122 + .enable_mask = BIT(4),
2123 + .hw.init = &(struct clk_init_data){
2124 + .name = "usb_hs1_h_clk",
2125 + .ops = &clk_branch_ops,
2126 + .flags = CLK_IS_ROOT,
2127 + },
2128 + },
2129 +};
2130 +
2131 +static struct clk_rcg usb_fs1_xcvr_clk_src = {
2132 + .ns_reg = 0x2968,
2133 + .md_reg = 0x2964,
2134 + .mn = {
2135 + .mnctr_en_bit = 8,
2136 + .mnctr_reset_bit = 7,
2137 + .mnctr_mode_shift = 5,
2138 + .n_val_shift = 16,
2139 + .m_val_shift = 16,
2140 + .width = 8,
2141 + },
2142 + .p = {
2143 + .pre_div_shift = 3,
2144 + .pre_div_width = 2,
2145 + },
2146 + .s = {
2147 + .src_sel_shift = 0,
2148 + .parent_map = gcc_pxo_pll8_pll0,
2149 + },
2150 + .freq_tbl = clk_tbl_usb,
2151 + .clkr = {
2152 + .enable_reg = 0x2968,
2153 + .enable_mask = BIT(11),
2154 + .hw.init = &(struct clk_init_data){
2155 + .name = "usb_fs1_xcvr_src",
2156 + .parent_names = gcc_pxo_pll8_pll0_map,
2157 + .num_parents = 3,
2158 + .ops = &clk_rcg_ops,
2159 + .flags = CLK_SET_RATE_GATE,
2160 + },
2161 + },
2162 +};
2163 +
2164 +static struct clk_branch usb_fs1_xcvr_clk = {
2165 + .halt_reg = 0x2fcc,
2166 + .halt_bit = 17,
2167 + .clkr = {
2168 + .enable_reg = 0x2968,
2169 + .enable_mask = BIT(9),
2170 + .hw.init = &(struct clk_init_data){
2171 + .name = "usb_fs1_xcvr_clk",
2172 + .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2173 + .num_parents = 1,
2174 + .ops = &clk_branch_ops,
2175 + .flags = CLK_SET_RATE_PARENT,
2176 + },
2177 + },
2178 +};
2179 +
2180 +static struct clk_branch usb_fs1_sys_clk = {
2181 + .halt_reg = 0x2fcc,
2182 + .halt_bit = 18,
2183 + .clkr = {
2184 + .enable_reg = 0x296c,
2185 + .enable_mask = BIT(4),
2186 + .hw.init = &(struct clk_init_data){
2187 + .name = "usb_fs1_sys_clk",
2188 + .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2189 + .num_parents = 1,
2190 + .ops = &clk_branch_ops,
2191 + .flags = CLK_SET_RATE_PARENT,
2192 + },
2193 + },
2194 +};
2195 +
2196 +static struct clk_branch usb_fs1_h_clk = {
2197 + .halt_reg = 0x2fcc,
2198 + .halt_bit = 19,
2199 + .clkr = {
2200 + .enable_reg = 0x2960,
2201 + .enable_mask = BIT(4),
2202 + .hw.init = &(struct clk_init_data){
2203 + .name = "usb_fs1_h_clk",
2204 + .ops = &clk_branch_ops,
2205 + .flags = CLK_IS_ROOT,
2206 + },
2207 + },
2208 +};
2209 +
2210 +static struct clk_regmap *gcc_ipq806x_clks[] = {
2211 + [PLL3] = &pll3.clkr,
2212 + [PLL8] = &pll8.clkr,
2213 + [PLL8_VOTE] = &pll8_vote,
2214 + [PLL14] = &pll14.clkr,
2215 + [PLL14_VOTE] = &pll14_vote,
2216 + [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2217 + [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2218 + [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2219 + [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2220 + [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2221 + [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2222 + [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2223 + [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2224 + [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2225 + [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2226 + [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2227 + [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2228 + [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2229 + [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2230 + [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2231 + [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2232 + [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2233 + [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2234 + [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2235 + [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2236 + [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2237 + [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2238 + [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2239 + [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2240 + [GP0_SRC] = &gp0_src.clkr,
2241 + [GP0_CLK] = &gp0_clk.clkr,
2242 + [GP1_SRC] = &gp1_src.clkr,
2243 + [GP1_CLK] = &gp1_clk.clkr,
2244 + [GP2_SRC] = &gp2_src.clkr,
2245 + [GP2_CLK] = &gp2_clk.clkr,
2246 + [PMEM_A_CLK] = &pmem_clk.clkr,
2247 + [PRNG_SRC] = &prng_src.clkr,
2248 + [PRNG_CLK] = &prng_clk.clkr,
2249 + [SDC1_SRC] = &sdc1_src.clkr,
2250 + [SDC1_CLK] = &sdc1_clk.clkr,
2251 + [SDC3_SRC] = &sdc3_src.clkr,
2252 + [SDC3_CLK] = &sdc3_clk.clkr,
2253 + [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2254 + [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2255 + [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2256 + [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2257 + [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2258 + [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2259 + [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2260 + [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2261 + [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2262 + [TSIF_H_CLK] = &tsif_h_clk.clkr,
2263 + [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2264 + [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2265 + [ADM0_CLK] = &adm0_clk.clkr,
2266 + [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2267 + [PCIE_A_CLK] = &pcie_a_clk.clkr,
2268 + [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2269 + [PCIE_H_CLK] = &pcie_h_clk.clkr,
2270 + [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2271 + [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2272 + [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2273 + [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2274 + [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2275 + [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2276 + [SATA_H_CLK] = &sata_h_clk.clkr,
2277 + [SATA_CLK_SRC] = &sata_ref_src.clkr,
2278 + [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2279 + [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2280 + [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2281 + [SATA_A_CLK] = &sata_a_clk.clkr,
2282 + [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2283 + [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2284 + [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2285 + [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2286 + [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2287 + [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2288 + [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2289 + [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2290 + [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2291 + [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2292 + [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2293 + [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2294 + [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2295 + [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2296 + [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2297 + [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2298 + [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2299 + [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2300 + [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2301 + [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2302 + [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2303 + [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2304 + [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2305 + [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2306 + [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2307 + [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2308 + [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2309 + [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2310 +};
2311 +
2312 +static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2313 + [QDSS_STM_RESET] = { 0x2060, 6 },
2314 + [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2315 + [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2316 + [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2317 + [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2318 + [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2319 + [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2320 + [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2321 + [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2322 + [ADM0_C2_RESET] = { 0x220c, 4 },
2323 + [ADM0_C1_RESET] = { 0x220c, 3 },
2324 + [ADM0_C0_RESET] = { 0x220c, 2 },
2325 + [ADM0_PBUS_RESET] = { 0x220c, 1 },
2326 + [ADM0_RESET] = { 0x220c, 0 },
2327 + [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2328 + [QDSS_POR_RESET] = { 0x2260, 4 },
2329 + [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2330 + [QDSS_HRESET_RESET] = { 0x2260, 2 },
2331 + [QDSS_AXI_RESET] = { 0x2260, 1 },
2332 + [QDSS_DBG_RESET] = { 0x2260, 0 },
2333 + [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2334 + [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2335 + [PCIE_EXT_RESET] = { 0x22dc, 6 },
2336 + [PCIE_PHY_RESET] = { 0x22dc, 5 },
2337 + [PCIE_PCI_RESET] = { 0x22dc, 4 },
2338 + [PCIE_POR_RESET] = { 0x22dc, 3 },
2339 + [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2340 + [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2341 + [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2342 + [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2343 + [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2344 + [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2345 + [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2346 + [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2347 + [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2348 + [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2349 + [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2350 + [DFAB_ARB0_RESET] = { 0x2560, 7 },
2351 + [DFAB_ARB1_RESET] = { 0x2564, 7 },
2352 + [PPSS_PROC_RESET] = { 0x2594, 1 },
2353 + [PPSS_RESET] = { 0x2594, 0 },
2354 + [DMA_BAM_RESET] = { 0x25c0, 7 },
2355 + [SPS_TIC_H_RESET] = { 0x2600, 7 },
2356 + [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2357 + [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2358 + [TSIF_H_RESET] = { 0x2700, 7 },
2359 + [CE1_H_RESET] = { 0x2720, 7 },
2360 + [CE1_CORE_RESET] = { 0x2724, 7 },
2361 + [CE1_SLEEP_RESET] = { 0x2728, 7 },
2362 + [CE2_H_RESET] = { 0x2740, 7 },
2363 + [CE2_CORE_RESET] = { 0x2744, 7 },
2364 + [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2365 + [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2366 + [RPM_PROC_RESET] = { 0x27c0, 7 },
2367 + [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2368 + [SDC1_RESET] = { 0x2830, 0 },
2369 + [SDC2_RESET] = { 0x2850, 0 },
2370 + [SDC3_RESET] = { 0x2870, 0 },
2371 + [SDC4_RESET] = { 0x2890, 0 },
2372 + [USB_HS1_RESET] = { 0x2910, 0 },
2373 + [USB_HSIC_RESET] = { 0x2934, 0 },
2374 + [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2375 + [USB_FS1_RESET] = { 0x2974, 0 },
2376 + [GSBI1_RESET] = { 0x29dc, 0 },
2377 + [GSBI2_RESET] = { 0x29fc, 0 },
2378 + [GSBI3_RESET] = { 0x2a1c, 0 },
2379 + [GSBI4_RESET] = { 0x2a3c, 0 },
2380 + [GSBI5_RESET] = { 0x2a5c, 0 },
2381 + [GSBI6_RESET] = { 0x2a7c, 0 },
2382 + [GSBI7_RESET] = { 0x2a9c, 0 },
2383 + [SPDM_RESET] = { 0x2b6c, 0 },
2384 + [SEC_CTRL_RESET] = { 0x2b80, 7 },
2385 + [TLMM_H_RESET] = { 0x2ba0, 7 },
2386 + [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2387 + [SATA_RESET] = { 0x2c1c, 0 },
2388 + [TSSC_RESET] = { 0x2ca0, 7 },
2389 + [PDM_RESET] = { 0x2cc0, 12 },
2390 + [MPM_H_RESET] = { 0x2da0, 7 },
2391 + [MPM_RESET] = { 0x2da4, 0 },
2392 + [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2393 + [PRNG_RESET] = { 0x2e80, 12 },
2394 + [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2395 + [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2396 + [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2397 + [PCIE_1_M_RESET] = { 0x3a98, 1 },
2398 + [PCIE_1_S_RESET] = { 0x3a98, 0 },
2399 + [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2400 + [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2401 + [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2402 + [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2403 + [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2404 + [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2405 + [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2406 + [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2407 + [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2408 + [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2409 + [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2410 + [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2411 + [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2412 + [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2413 + [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2414 + [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2415 + [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2416 + [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2417 + [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2418 + [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2419 + [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2420 + [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2421 + [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2422 + [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2423 + [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2424 + [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2425 + [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2426 + [NSSFB0_RESET] = { 0x3b60, 6 },
2427 + [NSSFB1_RESET] = { 0x3b60, 7 },
2428 +};
2429 +
2430 +static const struct regmap_config gcc_ipq806x_regmap_config = {
2431 + .reg_bits = 32,
2432 + .reg_stride = 4,
2433 + .val_bits = 32,
2434 + .max_register = 0x3e40,
2435 + .fast_io = true,
2436 +};
2437 +
2438 +static const struct qcom_cc_desc gcc_ipq806x_desc = {
2439 + .config = &gcc_ipq806x_regmap_config,
2440 + .clks = gcc_ipq806x_clks,
2441 + .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2442 + .resets = gcc_ipq806x_resets,
2443 + .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2444 +};
2445 +
2446 +static const struct of_device_id gcc_ipq806x_match_table[] = {
2447 + { .compatible = "qcom,gcc-ipq8064" },
2448 + { }
2449 +};
2450 +MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2451 +
2452 +static int gcc_ipq806x_probe(struct platform_device *pdev)
2453 +{
2454 + struct clk *clk;
2455 + struct device *dev = &pdev->dev;
2456 +
2457 + /* Temporary until RPM clocks supported */
2458 + clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2459 + if (IS_ERR(clk))
2460 + return PTR_ERR(clk);
2461 +
2462 + clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2463 + if (IS_ERR(clk))
2464 + return PTR_ERR(clk);
2465 +
2466 + return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2467 +}
2468 +
2469 +static int gcc_ipq806x_remove(struct platform_device *pdev)
2470 +{
2471 + qcom_cc_remove(pdev);
2472 + return 0;
2473 +}
2474 +
2475 +static struct platform_driver gcc_ipq806x_driver = {
2476 + .probe = gcc_ipq806x_probe,
2477 + .remove = gcc_ipq806x_remove,
2478 + .driver = {
2479 + .name = "gcc-ipq806x",
2480 + .owner = THIS_MODULE,
2481 + .of_match_table = gcc_ipq806x_match_table,
2482 + },
2483 +};
2484 +
2485 +static int __init gcc_ipq806x_init(void)
2486 +{
2487 + return platform_driver_register(&gcc_ipq806x_driver);
2488 +}
2489 +core_initcall(gcc_ipq806x_init);
2490 +
2491 +static void __exit gcc_ipq806x_exit(void)
2492 +{
2493 + platform_driver_unregister(&gcc_ipq806x_driver);
2494 +}
2495 +module_exit(gcc_ipq806x_exit);
2496 +
2497 +MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2498 +MODULE_LICENSE("GPL v2");
2499 +MODULE_ALIAS("platform:gcc-ipq806x");
2500 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
2501 new file mode 100644
2502 index 0000000..3b0f8e7
2503 --- /dev/null
2504 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
2505 @@ -0,0 +1,293 @@
2506 +/*
2507 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
2508 + *
2509 + * This software is licensed under the terms of the GNU General Public
2510 + * License version 2, as published by the Free Software Foundation, and
2511 + * may be copied, distributed, and modified under those terms.
2512 + *
2513 + * This program is distributed in the hope that it will be useful,
2514 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2515 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2516 + * GNU General Public License for more details.
2517 + */
2518 +
2519 +#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
2520 +#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
2521 +
2522 +#define AFAB_CLK_SRC 0
2523 +#define QDSS_STM_CLK 1
2524 +#define SCSS_A_CLK 2
2525 +#define SCSS_H_CLK 3
2526 +#define AFAB_CORE_CLK 4
2527 +#define SCSS_XO_SRC_CLK 5
2528 +#define AFAB_EBI1_CH0_A_CLK 6
2529 +#define AFAB_EBI1_CH1_A_CLK 7
2530 +#define AFAB_AXI_S0_FCLK 8
2531 +#define AFAB_AXI_S1_FCLK 9
2532 +#define AFAB_AXI_S2_FCLK 10
2533 +#define AFAB_AXI_S3_FCLK 11
2534 +#define AFAB_AXI_S4_FCLK 12
2535 +#define SFAB_CORE_CLK 13
2536 +#define SFAB_AXI_S0_FCLK 14
2537 +#define SFAB_AXI_S1_FCLK 15
2538 +#define SFAB_AXI_S2_FCLK 16
2539 +#define SFAB_AXI_S3_FCLK 17
2540 +#define SFAB_AXI_S4_FCLK 18
2541 +#define SFAB_AXI_S5_FCLK 19
2542 +#define SFAB_AHB_S0_FCLK 20
2543 +#define SFAB_AHB_S1_FCLK 21
2544 +#define SFAB_AHB_S2_FCLK 22
2545 +#define SFAB_AHB_S3_FCLK 23
2546 +#define SFAB_AHB_S4_FCLK 24
2547 +#define SFAB_AHB_S5_FCLK 25
2548 +#define SFAB_AHB_S6_FCLK 26
2549 +#define SFAB_AHB_S7_FCLK 27
2550 +#define QDSS_AT_CLK_SRC 28
2551 +#define QDSS_AT_CLK 29
2552 +#define QDSS_TRACECLKIN_CLK_SRC 30
2553 +#define QDSS_TRACECLKIN_CLK 31
2554 +#define QDSS_TSCTR_CLK_SRC 32
2555 +#define QDSS_TSCTR_CLK 33
2556 +#define SFAB_ADM0_M0_A_CLK 34
2557 +#define SFAB_ADM0_M1_A_CLK 35
2558 +#define SFAB_ADM0_M2_H_CLK 36
2559 +#define ADM0_CLK 37
2560 +#define ADM0_PBUS_CLK 38
2561 +#define IMEM0_A_CLK 39
2562 +#define QDSS_H_CLK 40
2563 +#define PCIE_A_CLK 41
2564 +#define PCIE_AUX_CLK 42
2565 +#define PCIE_H_CLK 43
2566 +#define PCIE_PHY_CLK 44
2567 +#define SFAB_CLK_SRC 45
2568 +#define SFAB_LPASS_Q6_A_CLK 46
2569 +#define SFAB_AFAB_M_A_CLK 47
2570 +#define AFAB_SFAB_M0_A_CLK 48
2571 +#define AFAB_SFAB_M1_A_CLK 49
2572 +#define SFAB_SATA_S_H_CLK 50
2573 +#define DFAB_CLK_SRC 51
2574 +#define DFAB_CLK 52
2575 +#define SFAB_DFAB_M_A_CLK 53
2576 +#define DFAB_SFAB_M_A_CLK 54
2577 +#define DFAB_SWAY0_H_CLK 55
2578 +#define DFAB_SWAY1_H_CLK 56
2579 +#define DFAB_ARB0_H_CLK 57
2580 +#define DFAB_ARB1_H_CLK 58
2581 +#define PPSS_H_CLK 59
2582 +#define PPSS_PROC_CLK 60
2583 +#define PPSS_TIMER0_CLK 61
2584 +#define PPSS_TIMER1_CLK 62
2585 +#define PMEM_A_CLK 63
2586 +#define DMA_BAM_H_CLK 64
2587 +#define SIC_H_CLK 65
2588 +#define SPS_TIC_H_CLK 66
2589 +#define CFPB_2X_CLK_SRC 67
2590 +#define CFPB_CLK 68
2591 +#define CFPB0_H_CLK 69
2592 +#define CFPB1_H_CLK 70
2593 +#define CFPB2_H_CLK 71
2594 +#define SFAB_CFPB_M_H_CLK 72
2595 +#define CFPB_MASTER_H_CLK 73
2596 +#define SFAB_CFPB_S_H_CLK 74
2597 +#define CFPB_SPLITTER_H_CLK 75
2598 +#define TSIF_H_CLK 76
2599 +#define TSIF_INACTIVITY_TIMERS_CLK 77
2600 +#define TSIF_REF_SRC 78
2601 +#define TSIF_REF_CLK 79
2602 +#define CE1_H_CLK 80
2603 +#define CE1_CORE_CLK 81
2604 +#define CE1_SLEEP_CLK 82
2605 +#define CE2_H_CLK 83
2606 +#define CE2_CORE_CLK 84
2607 +#define SFPB_H_CLK_SRC 85
2608 +#define SFPB_H_CLK 86
2609 +#define SFAB_SFPB_M_H_CLK 87
2610 +#define SFAB_SFPB_S_H_CLK 88
2611 +#define RPM_PROC_CLK 89
2612 +#define RPM_BUS_H_CLK 90
2613 +#define RPM_SLEEP_CLK 91
2614 +#define RPM_TIMER_CLK 92
2615 +#define RPM_MSG_RAM_H_CLK 93
2616 +#define PMIC_ARB0_H_CLK 94
2617 +#define PMIC_ARB1_H_CLK 95
2618 +#define PMIC_SSBI2_SRC 96
2619 +#define PMIC_SSBI2_CLK 97
2620 +#define SDC1_H_CLK 98
2621 +#define SDC2_H_CLK 99
2622 +#define SDC3_H_CLK 100
2623 +#define SDC4_H_CLK 101
2624 +#define SDC1_SRC 102
2625 +#define SDC1_CLK 103
2626 +#define SDC2_SRC 104
2627 +#define SDC2_CLK 105
2628 +#define SDC3_SRC 106
2629 +#define SDC3_CLK 107
2630 +#define SDC4_SRC 108
2631 +#define SDC4_CLK 109
2632 +#define USB_HS1_H_CLK 110
2633 +#define USB_HS1_XCVR_SRC 111
2634 +#define USB_HS1_XCVR_CLK 112
2635 +#define USB_HSIC_H_CLK 113
2636 +#define USB_HSIC_XCVR_SRC 114
2637 +#define USB_HSIC_XCVR_CLK 115
2638 +#define USB_HSIC_SYSTEM_CLK_SRC 116
2639 +#define USB_HSIC_SYSTEM_CLK 117
2640 +#define CFPB0_C0_H_CLK 118
2641 +#define CFPB0_D0_H_CLK 119
2642 +#define CFPB0_C1_H_CLK 120
2643 +#define CFPB0_D1_H_CLK 121
2644 +#define USB_FS1_H_CLK 122
2645 +#define USB_FS1_XCVR_SRC 123
2646 +#define USB_FS1_XCVR_CLK 124
2647 +#define USB_FS1_SYSTEM_CLK 125
2648 +#define GSBI_COMMON_SIM_SRC 126
2649 +#define GSBI1_H_CLK 127
2650 +#define GSBI2_H_CLK 128
2651 +#define GSBI3_H_CLK 129
2652 +#define GSBI4_H_CLK 130
2653 +#define GSBI5_H_CLK 131
2654 +#define GSBI6_H_CLK 132
2655 +#define GSBI7_H_CLK 133
2656 +#define GSBI1_QUP_SRC 134
2657 +#define GSBI1_QUP_CLK 135
2658 +#define GSBI2_QUP_SRC 136
2659 +#define GSBI2_QUP_CLK 137
2660 +#define GSBI3_QUP_SRC 138
2661 +#define GSBI3_QUP_CLK 139
2662 +#define GSBI4_QUP_SRC 140
2663 +#define GSBI4_QUP_CLK 141
2664 +#define GSBI5_QUP_SRC 142
2665 +#define GSBI5_QUP_CLK 143
2666 +#define GSBI6_QUP_SRC 144
2667 +#define GSBI6_QUP_CLK 145
2668 +#define GSBI7_QUP_SRC 146
2669 +#define GSBI7_QUP_CLK 147
2670 +#define GSBI1_UART_SRC 148
2671 +#define GSBI1_UART_CLK 149
2672 +#define GSBI2_UART_SRC 150
2673 +#define GSBI2_UART_CLK 151
2674 +#define GSBI3_UART_SRC 152
2675 +#define GSBI3_UART_CLK 153
2676 +#define GSBI4_UART_SRC 154
2677 +#define GSBI4_UART_CLK 155
2678 +#define GSBI5_UART_SRC 156
2679 +#define GSBI5_UART_CLK 157
2680 +#define GSBI6_UART_SRC 158
2681 +#define GSBI6_UART_CLK 159
2682 +#define GSBI7_UART_SRC 160
2683 +#define GSBI7_UART_CLK 161
2684 +#define GSBI1_SIM_CLK 162
2685 +#define GSBI2_SIM_CLK 163
2686 +#define GSBI3_SIM_CLK 164
2687 +#define GSBI4_SIM_CLK 165
2688 +#define GSBI5_SIM_CLK 166
2689 +#define GSBI6_SIM_CLK 167
2690 +#define GSBI7_SIM_CLK 168
2691 +#define USB_HSIC_HSIC_CLK_SRC 169
2692 +#define USB_HSIC_HSIC_CLK 170
2693 +#define USB_HSIC_HSIO_CAL_CLK 171
2694 +#define SPDM_CFG_H_CLK 172
2695 +#define SPDM_MSTR_H_CLK 173
2696 +#define SPDM_FF_CLK_SRC 174
2697 +#define SPDM_FF_CLK 175
2698 +#define SEC_CTRL_CLK 176
2699 +#define SEC_CTRL_ACC_CLK_SRC 177
2700 +#define SEC_CTRL_ACC_CLK 178
2701 +#define TLMM_H_CLK 179
2702 +#define TLMM_CLK 180
2703 +#define SATA_H_CLK 181
2704 +#define SATA_CLK_SRC 182
2705 +#define SATA_RXOOB_CLK 183
2706 +#define SATA_PMALIVE_CLK 184
2707 +#define SATA_PHY_REF_CLK 185
2708 +#define SATA_A_CLK 186
2709 +#define SATA_PHY_CFG_CLK 187
2710 +#define TSSC_CLK_SRC 188
2711 +#define TSSC_CLK 189
2712 +#define PDM_SRC 190
2713 +#define PDM_CLK 191
2714 +#define GP0_SRC 192
2715 +#define GP0_CLK 193
2716 +#define GP1_SRC 194
2717 +#define GP1_CLK 195
2718 +#define GP2_SRC 196
2719 +#define GP2_CLK 197
2720 +#define MPM_CLK 198
2721 +#define EBI1_CLK_SRC 199
2722 +#define EBI1_CH0_CLK 200
2723 +#define EBI1_CH1_CLK 201
2724 +#define EBI1_2X_CLK 202
2725 +#define EBI1_CH0_DQ_CLK 203
2726 +#define EBI1_CH1_DQ_CLK 204
2727 +#define EBI1_CH0_CA_CLK 205
2728 +#define EBI1_CH1_CA_CLK 206
2729 +#define EBI1_XO_CLK 207
2730 +#define SFAB_SMPSS_S_H_CLK 208
2731 +#define PRNG_SRC 209
2732 +#define PRNG_CLK 210
2733 +#define PXO_SRC 211
2734 +#define SPDM_CY_PORT0_CLK 212
2735 +#define SPDM_CY_PORT1_CLK 213
2736 +#define SPDM_CY_PORT2_CLK 214
2737 +#define SPDM_CY_PORT3_CLK 215
2738 +#define SPDM_CY_PORT4_CLK 216
2739 +#define SPDM_CY_PORT5_CLK 217
2740 +#define SPDM_CY_PORT6_CLK 218
2741 +#define SPDM_CY_PORT7_CLK 219
2742 +#define PLL0 220
2743 +#define PLL0_VOTE 221
2744 +#define PLL3 222
2745 +#define PLL3_VOTE 223
2746 +#define PLL4 224
2747 +#define PLL4_VOTE 225
2748 +#define PLL8 226
2749 +#define PLL8_VOTE 227
2750 +#define PLL9 228
2751 +#define PLL10 229
2752 +#define PLL11 230
2753 +#define PLL12 231
2754 +#define PLL14 232
2755 +#define PLL14_VOTE 233
2756 +#define PLL18 234
2757 +#define CE5_SRC 235
2758 +#define CE5_H_CLK 236
2759 +#define CE5_CORE_CLK 237
2760 +#define CE3_SLEEP_CLK 238
2761 +#define SFAB_AHB_S8_FCLK 239
2762 +#define SPDM_CY_PORT8_CLK 246
2763 +#define PCIE_ALT_REF_SRC 247
2764 +#define PCIE_ALT_REF_CLK 248
2765 +#define PCIE_1_A_CLK 249
2766 +#define PCIE_1_AUX_CLK 250
2767 +#define PCIE_1_H_CLK 251
2768 +#define PCIE_1_PHY_CLK 252
2769 +#define PCIE_1_ALT_REF_SRC 253
2770 +#define PCIE_1_ALT_REF_CLK 254
2771 +#define PCIE_2_A_CLK 255
2772 +#define PCIE_2_AUX_CLK 256
2773 +#define PCIE_2_H_CLK 257
2774 +#define PCIE_2_PHY_CLK 258
2775 +#define PCIE_2_ALT_REF_SRC 259
2776 +#define PCIE_2_ALT_REF_CLK 260
2777 +#define EBI2_CLK 261
2778 +#define USB30_SLEEP_CLK 262
2779 +#define USB30_UTMI_SRC 263
2780 +#define USB30_0_UTMI_CLK 264
2781 +#define USB30_1_UTMI_CLK 264
2782 +#define USB30_MASTER_SRC 265
2783 +#define USB30_0_MASTER_CLK 266
2784 +#define USB30_1_MASTER_CLK 267
2785 +#define GMAC_CORE1_CLK_SRC 268
2786 +#define GMAC_CORE2_CLK_SRC 269
2787 +#define GMAC_CORE3_CLK_SRC 270
2788 +#define GMAC_CORE4_CLK_SRC 271
2789 +#define GMAC_CORE1_CLK 272
2790 +#define GMAC_CORE2_CLK 273
2791 +#define GMAC_CORE3_CLK 274
2792 +#define GMAC_CORE4_CLK 275
2793 +#define UBI32_CORE1_CLK_SRC 276
2794 +#define UBI32_CORE2_CLK_SRC 277
2795 +#define UBI32_CORE1_CLK 278
2796 +#define UBI32_CORE2_CLK 279
2797 +
2798 +#endif
2799 diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
2800 new file mode 100644
2801 index 0000000..0ad5ef9
2802 --- /dev/null
2803 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
2804 @@ -0,0 +1,132 @@
2805 +/*
2806 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
2807 + *
2808 + * This software is licensed under the terms of the GNU General Public
2809 + * License version 2, as published by the Free Software Foundation, and
2810 + * may be copied, distributed, and modified under those terms.
2811 + *
2812 + * This program is distributed in the hope that it will be useful,
2813 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2814 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2815 + * GNU General Public License for more details.
2816 + */
2817 +
2818 +#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
2819 +#define _DT_BINDINGS_RESET_IPQ_806X_H
2820 +
2821 +#define QDSS_STM_RESET 0
2822 +#define AFAB_SMPSS_S_RESET 1
2823 +#define AFAB_SMPSS_M1_RESET 2
2824 +#define AFAB_SMPSS_M0_RESET 3
2825 +#define AFAB_EBI1_CH0_RESET 4
2826 +#define AFAB_EBI1_CH1_RESET 5
2827 +#define SFAB_ADM0_M0_RESET 6
2828 +#define SFAB_ADM0_M1_RESET 7
2829 +#define SFAB_ADM0_M2_RESET 8
2830 +#define ADM0_C2_RESET 9
2831 +#define ADM0_C1_RESET 10
2832 +#define ADM0_C0_RESET 11
2833 +#define ADM0_PBUS_RESET 12
2834 +#define ADM0_RESET 13
2835 +#define QDSS_CLKS_SW_RESET 14
2836 +#define QDSS_POR_RESET 15
2837 +#define QDSS_TSCTR_RESET 16
2838 +#define QDSS_HRESET_RESET 17
2839 +#define QDSS_AXI_RESET 18
2840 +#define QDSS_DBG_RESET 19
2841 +#define SFAB_PCIE_M_RESET 20
2842 +#define SFAB_PCIE_S_RESET 21
2843 +#define PCIE_EXT_RESET 22
2844 +#define PCIE_PHY_RESET 23
2845 +#define PCIE_PCI_RESET 24
2846 +#define PCIE_POR_RESET 25
2847 +#define PCIE_HCLK_RESET 26
2848 +#define PCIE_ACLK_RESET 27
2849 +#define SFAB_LPASS_RESET 28
2850 +#define SFAB_AFAB_M_RESET 29
2851 +#define AFAB_SFAB_M0_RESET 30
2852 +#define AFAB_SFAB_M1_RESET 31
2853 +#define SFAB_SATA_S_RESET 32
2854 +#define SFAB_DFAB_M_RESET 33
2855 +#define DFAB_SFAB_M_RESET 34
2856 +#define DFAB_SWAY0_RESET 35
2857 +#define DFAB_SWAY1_RESET 36
2858 +#define DFAB_ARB0_RESET 37
2859 +#define DFAB_ARB1_RESET 38
2860 +#define PPSS_PROC_RESET 39
2861 +#define PPSS_RESET 40
2862 +#define DMA_BAM_RESET 41
2863 +#define SPS_TIC_H_RESET 42
2864 +#define SFAB_CFPB_M_RESET 43
2865 +#define SFAB_CFPB_S_RESET 44
2866 +#define TSIF_H_RESET 45
2867 +#define CE1_H_RESET 46
2868 +#define CE1_CORE_RESET 47
2869 +#define CE1_SLEEP_RESET 48
2870 +#define CE2_H_RESET 49
2871 +#define CE2_CORE_RESET 50
2872 +#define SFAB_SFPB_M_RESET 51
2873 +#define SFAB_SFPB_S_RESET 52
2874 +#define RPM_PROC_RESET 53
2875 +#define PMIC_SSBI2_RESET 54
2876 +#define SDC1_RESET 55
2877 +#define SDC2_RESET 56
2878 +#define SDC3_RESET 57
2879 +#define SDC4_RESET 58
2880 +#define USB_HS1_RESET 59
2881 +#define USB_HSIC_RESET 60
2882 +#define USB_FS1_XCVR_RESET 61
2883 +#define USB_FS1_RESET 62
2884 +#define GSBI1_RESET 63
2885 +#define GSBI2_RESET 64
2886 +#define GSBI3_RESET 65
2887 +#define GSBI4_RESET 66
2888 +#define GSBI5_RESET 67
2889 +#define GSBI6_RESET 68
2890 +#define GSBI7_RESET 69
2891 +#define SPDM_RESET 70
2892 +#define SEC_CTRL_RESET 71
2893 +#define TLMM_H_RESET 72
2894 +#define SFAB_SATA_M_RESET 73
2895 +#define SATA_RESET 74
2896 +#define TSSC_RESET 75
2897 +#define PDM_RESET 76
2898 +#define MPM_H_RESET 77
2899 +#define MPM_RESET 78
2900 +#define SFAB_SMPSS_S_RESET 79
2901 +#define PRNG_RESET 80
2902 +#define SFAB_CE3_M_RESET 81
2903 +#define SFAB_CE3_S_RESET 82
2904 +#define CE3_SLEEP_RESET 83
2905 +#define PCIE_1_M_RESET 84
2906 +#define PCIE_1_S_RESET 85
2907 +#define PCIE_1_EXT_RESET 86
2908 +#define PCIE_1_PHY_RESET 87
2909 +#define PCIE_1_PCI_RESET 88
2910 +#define PCIE_1_POR_RESET 89
2911 +#define PCIE_1_HCLK_RESET 90
2912 +#define PCIE_1_ACLK_RESET 91
2913 +#define PCIE_2_M_RESET 92
2914 +#define PCIE_2_S_RESET 93
2915 +#define PCIE_2_EXT_RESET 94
2916 +#define PCIE_2_PHY_RESET 95
2917 +#define PCIE_2_PCI_RESET 96
2918 +#define PCIE_2_POR_RESET 97
2919 +#define PCIE_2_HCLK_RESET 98
2920 +#define PCIE_2_ACLK_RESET 99
2921 +#define SFAB_USB30_S_RESET 100
2922 +#define SFAB_USB30_M_RESET 101
2923 +#define USB30_0_PORT2_HS_PHY_RESET 102
2924 +#define USB30_0_MASTER_RESET 103
2925 +#define USB30_0_SLEEP_RESET 104
2926 +#define USB30_0_UTMI_PHY_RESET 105
2927 +#define USB30_0_POWERON_RESET 106
2928 +#define USB30_0_PHY_RESET 107
2929 +#define USB30_1_MASTER_RESET 108
2930 +#define USB30_1_SLEEP_RESET 109
2931 +#define USB30_1_UTMI_PHY_RESET 110
2932 +#define USB30_1_POWERON_RESET 111
2933 +#define USB30_1_PHY_RESET 112
2934 +#define NSSFB0_RESET 113
2935 +#define NSSFB1_RESET 114
2936 +#endif
2937 --
2938 1.7.10.4
2939
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