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ixp4xx: add missing reboot handlers (fixes #11577, backport of r33672)
[openwrt/svn-archive/archive.git] / target / linux / ixp4xx / patches-3.3 / 190-cambria_support.patch
1 --- /dev/null
2 +++ b/arch/arm/mach-ixp4xx/cambria-pci.c
3 @@ -0,0 +1,79 @@
4 +/*
5 + * arch/arch/mach-ixp4xx/cambria-pci.c
6 + *
7 + * PCI setup routines for Gateworks Cambria series
8 + *
9 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 + *
11 + * based on coyote-pci.c:
12 + * Copyright (C) 2002 Jungo Software Technologies.
13 + * Copyright (C) 2003 MontaVista Softwrae, Inc.
14 + *
15 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
16 + *
17 + * This program is free software; you can redistribute it and/or modify
18 + * it under the terms of the GNU General Public License version 2 as
19 + * published by the Free Software Foundation.
20 + *
21 + */
22 +
23 +#include <linux/kernel.h>
24 +#include <linux/pci.h>
25 +#include <linux/init.h>
26 +#include <linux/irq.h>
27 +
28 +#include <asm/mach-types.h>
29 +#include <mach/hardware.h>
30 +#include <asm/irq.h>
31 +
32 +#include <asm/mach/pci.h>
33 +
34 +extern void ixp4xx_pci_preinit(void);
35 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
36 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
37 +
38 +void __init cambria_pci_preinit(void)
39 +{
40 + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
41 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
42 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
43 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
44 +
45 + ixp4xx_pci_preinit();
46 +}
47 +
48 +static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
49 +{
50 + if (slot == 1)
51 + return IRQ_IXP4XX_GPIO11;
52 + else if (slot == 2)
53 + return IRQ_IXP4XX_GPIO10;
54 + else if (slot == 3)
55 + return IRQ_IXP4XX_GPIO9;
56 + else if (slot == 4)
57 + return IRQ_IXP4XX_GPIO8;
58 + else if (slot == 6)
59 + return IRQ_IXP4XX_GPIO10;
60 + else if (slot == 15)
61 + return IRQ_IXP4XX_GPIO8;
62 +
63 + else return -1;
64 +}
65 +
66 +struct hw_pci cambria_pci __initdata = {
67 + .nr_controllers = 1,
68 + .preinit = cambria_pci_preinit,
69 + .swizzle = pci_std_swizzle,
70 + .setup = ixp4xx_setup,
71 + .scan = ixp4xx_scan_bus,
72 + .map_irq = cambria_map_irq,
73 +};
74 +
75 +int __init cambria_pci_init(void)
76 +{
77 + if (machine_is_cambria())
78 + pci_common_init(&cambria_pci);
79 + return 0;
80 +}
81 +
82 +subsys_initcall(cambria_pci_init);
83 --- /dev/null
84 +++ b/arch/arm/mach-ixp4xx/cambria-setup.c
85 @@ -0,0 +1,1006 @@
86 +/*
87 + * arch/arm/mach-ixp4xx/cambria-setup.c
88 + *
89 + * Board setup for the Gateworks Cambria series
90 + *
91 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
92 + * Copyright (C) 2012 Gateworks Corporation <support@gateworks.com>
93 + *
94 + * based on coyote-setup.c:
95 + * Copyright (C) 2003-2005 MontaVista Software, Inc.
96 + *
97 + * Author: Imre Kaloz <kaloz@openwrt.org>
98 + * Tim Harvey <tharvey@gateworks.com>
99 + */
100 +
101 +#include <linux/device.h>
102 +#include <linux/gpio_buttons.h>
103 +#include <linux/gpio.h>
104 +#include <linux/i2c.h>
105 +#include <linux/i2c-gpio.h>
106 +#include <linux/i2c/at24.h>
107 +#include <linux/i2c/gw_i2c_pld.h>
108 +#include <linux/i2c/pca953x.h>
109 +#include <linux/if_ether.h>
110 +#include <linux/init.h>
111 +#include <linux/input.h>
112 +#include <linux/kernel.h>
113 +#include <linux/leds.h>
114 +#include <linux/memory.h>
115 +#include <linux/netdevice.h>
116 +#include <linux/serial.h>
117 +#include <linux/serial_8250.h>
118 +#include <linux/slab.h>
119 +#include <linux/socket.h>
120 +#include <linux/types.h>
121 +#include <linux/tty.h>
122 +#include <linux/irq.h>
123 +
124 +#include <mach/hardware.h>
125 +#include <mach/gpio.h>
126 +#include <asm/irq.h>
127 +#include <asm/mach-types.h>
128 +#include <asm/mach/arch.h>
129 +#include <asm/mach/flash.h>
130 +#include <asm/setup.h>
131 +
132 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
133 +
134 +struct cambria_board_info {
135 + unsigned char *model;
136 + void (*setup)(void);
137 +};
138 +
139 +static struct cambria_board_info *cambria_info __initdata;
140 +
141 +static struct flash_platform_data cambria_flash_data = {
142 + .map_name = "cfi_probe",
143 + .width = 2,
144 +};
145 +
146 +static struct resource cambria_flash_resource = {
147 + .flags = IORESOURCE_MEM,
148 +};
149 +
150 +static struct platform_device cambria_flash = {
151 + .name = "IXP4XX-Flash",
152 + .id = 0,
153 + .dev = {
154 + .platform_data = &cambria_flash_data,
155 + },
156 + .num_resources = 1,
157 + .resource = &cambria_flash_resource,
158 +};
159 +
160 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
161 + .sda_pin = 7,
162 + .scl_pin = 6,
163 +};
164 +
165 +static struct platform_device cambria_i2c_gpio = {
166 + .name = "i2c-gpio",
167 + .id = 0,
168 + .dev = {
169 + .platform_data = &cambria_i2c_gpio_data,
170 + },
171 +};
172 +
173 +#ifdef SFP_SERIALID
174 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = {
175 + .sda_pin = 113,
176 + .scl_pin = 112,
177 + .sda_is_open_drain = 0,
178 + .scl_is_open_drain = 0,
179 +};
180 +
181 +static struct platform_device cambria_i2c_gpio_sfpa = {
182 + .name = "i2c-gpio",
183 + .id = 1,
184 + .dev = {
185 + .platform_data = &cambria_i2c_gpio_sfpa_data,
186 + },
187 +};
188 +
189 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = {
190 + .sda_pin = 115,
191 + .scl_pin = 114,
192 + .sda_is_open_drain = 0,
193 + .scl_is_open_drain = 0,
194 +};
195 +
196 +static struct platform_device cambria_i2c_gpio_sfpb = {
197 + .name = "i2c-gpio",
198 + .id = 2,
199 + .dev = {
200 + .platform_data = &cambria_i2c_gpio_sfpb_data,
201 + },
202 +};
203 +#endif // #ifdef SFP_SERIALID
204 +
205 +static struct eth_plat_info cambria_npec_data = {
206 + .phy = 1,
207 + .rxq = 4,
208 + .txreadyq = 21,
209 +};
210 +
211 +static struct eth_plat_info cambria_npea_data = {
212 + .phy = 2,
213 + .rxq = 2,
214 + .txreadyq = 19,
215 +};
216 +
217 +static struct platform_device cambria_npec_device = {
218 + .name = "ixp4xx_eth",
219 + .id = IXP4XX_ETH_NPEC,
220 + .dev.platform_data = &cambria_npec_data,
221 +};
222 +
223 +static struct platform_device cambria_npea_device = {
224 + .name = "ixp4xx_eth",
225 + .id = IXP4XX_ETH_NPEA,
226 + .dev.platform_data = &cambria_npea_data,
227 +};
228 +
229 +static struct resource cambria_uart_resource = {
230 + .start = IXP4XX_UART1_BASE_PHYS,
231 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
232 + .flags = IORESOURCE_MEM,
233 +};
234 +
235 +static struct plat_serial8250_port cambria_uart_data[] = {
236 + {
237 + .mapbase = IXP4XX_UART1_BASE_PHYS,
238 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
239 + .irq = IRQ_IXP4XX_UART1,
240 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
241 + .iotype = UPIO_MEM,
242 + .regshift = 2,
243 + .uartclk = IXP4XX_UART_XTAL,
244 + },
245 + { },
246 +};
247 +
248 +static struct platform_device cambria_uart = {
249 + .name = "serial8250",
250 + .id = PLAT8250_DEV_PLATFORM,
251 + .dev = {
252 + .platform_data = cambria_uart_data,
253 + },
254 + .num_resources = 1,
255 + .resource = &cambria_uart_resource,
256 +};
257 +
258 +static struct resource cambria_optional_uart_resources[] = {
259 + {
260 + .start = 0x52000000,
261 + .end = 0x52000fff,
262 + .flags = IORESOURCE_MEM
263 + },
264 + {
265 + .start = 0x53000000,
266 + .end = 0x53000fff,
267 + .flags = IORESOURCE_MEM
268 + },
269 + {
270 + .start = 0x52000000,
271 + .end = 0x52000fff,
272 + .flags = IORESOURCE_MEM
273 + },
274 + {
275 + .start = 0x52000000,
276 + .end = 0x52000fff,
277 + .flags = IORESOURCE_MEM
278 + },
279 + {
280 + .start = 0x52000000,
281 + .end = 0x52000fff,
282 + .flags = IORESOURCE_MEM
283 + },
284 + {
285 + .start = 0x52000000,
286 + .end = 0x52000fff,
287 + .flags = IORESOURCE_MEM
288 + },
289 + {
290 + .start = 0x52000000,
291 + .end = 0x52000fff,
292 + .flags = IORESOURCE_MEM
293 + },
294 + {
295 + .start = 0x53000000,
296 + .end = 0x53000fff,
297 + .flags = IORESOURCE_MEM
298 + }
299 +};
300 +
301 +static struct plat_serial8250_port cambria_optional_uart_data[] = {
302 + {
303 + .flags = UPF_BOOT_AUTOCONF,
304 + .iotype = UPIO_MEM_DELAY,
305 + .regshift = 0,
306 + .uartclk = 1843200,
307 + .rw_delay = 10,
308 + },
309 + {
310 + .flags = UPF_BOOT_AUTOCONF,
311 + .iotype = UPIO_MEM_DELAY,
312 + .regshift = 0,
313 + .uartclk = 1843200,
314 + .rw_delay = 10,
315 + },
316 + {
317 + .flags = UPF_BOOT_AUTOCONF,
318 + .iotype = UPIO_MEM,
319 + .regshift = 0,
320 + .uartclk = 18432000,
321 + },
322 + {
323 + .flags = UPF_BOOT_AUTOCONF,
324 + .iotype = UPIO_MEM,
325 + .regshift = 0,
326 + .uartclk = 18432000,
327 + },
328 + {
329 + .flags = UPF_BOOT_AUTOCONF,
330 + .iotype = UPIO_MEM,
331 + .regshift = 0,
332 + .uartclk = 18432000,
333 + },
334 + {
335 + .flags = UPF_BOOT_AUTOCONF,
336 + .iotype = UPIO_MEM,
337 + .regshift = 0,
338 + .uartclk = 18432000,
339 + },
340 + {
341 + .flags = UPF_BOOT_AUTOCONF,
342 + .iotype = UPIO_MEM,
343 + .regshift = 0,
344 + .uartclk = 18432000,
345 + },
346 + { },
347 +};
348 +
349 +static struct platform_device cambria_optional_uart = {
350 + .name = "serial8250",
351 + .id = PLAT8250_DEV_PLATFORM1,
352 + .dev.platform_data = cambria_optional_uart_data,
353 + .num_resources = 2,
354 + .resource = cambria_optional_uart_resources,
355 +};
356 +
357 +static struct resource cambria_pata_resources[] = {
358 + {
359 + .flags = IORESOURCE_MEM
360 + },
361 + {
362 + .flags = IORESOURCE_MEM,
363 + },
364 + {
365 + .name = "intrq",
366 + .start = IRQ_IXP4XX_GPIO12,
367 + .end = IRQ_IXP4XX_GPIO12,
368 + .flags = IORESOURCE_IRQ,
369 + },
370 +};
371 +
372 +static struct ixp4xx_pata_data cambria_pata_data = {
373 + .cs0_bits = 0xbfff3c03,
374 + .cs1_bits = 0xbfff3c03,
375 +};
376 +
377 +static struct platform_device cambria_pata = {
378 + .name = "pata_ixp4xx_cf",
379 + .id = 0,
380 + .dev.platform_data = &cambria_pata_data,
381 + .num_resources = ARRAY_SIZE(cambria_pata_resources),
382 + .resource = cambria_pata_resources,
383 +};
384 +
385 +static struct gpio_led cambria_gpio_leds[] = {
386 + {
387 + .name = "user",
388 + .gpio = 5,
389 + .active_low = 1,
390 + },
391 + {
392 + .name = "user2",
393 + .gpio = 0,
394 + .active_low = 1,
395 + },
396 + {
397 + .name = "user3",
398 + .gpio = 0,
399 + .active_low = 1,
400 + },
401 + {
402 + .name = "user4",
403 + .gpio = 0,
404 + .active_low = 1,
405 + }
406 +};
407 +
408 +static struct gpio_led_platform_data cambria_gpio_leds_data = {
409 + .num_leds = 1,
410 + .leds = cambria_gpio_leds,
411 +};
412 +
413 +static struct platform_device cambria_gpio_leds_device = {
414 + .name = "leds-gpio",
415 + .id = -1,
416 + .dev.platform_data = &cambria_gpio_leds_data,
417 +};
418 +
419 +static struct resource cambria_gpio_resources[] = {
420 + {
421 + .name = "gpio",
422 + .flags = 0,
423 + },
424 +};
425 +
426 +static struct gpio cambria_gpios_gw2350[] = {
427 + // ARM GPIO
428 +#if 0 // configured from bootloader
429 + { 0, GPIOF_IN, "ARM_DIO0" },
430 + { 1, GPIOF_IN, "ARM_DIO1" },
431 + { 2, GPIOF_IN, "ARM_DIO2" },
432 + { 3, GPIOF_IN, "ARM_DIO3" },
433 + { 4, GPIOF_IN, "ARM_DIO4" },
434 + { 5, GPIOF_IN, "ARM_DIO5" },
435 + { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" },
436 +#endif
437 + { 8, GPIOF_IN, "ARM_DIO8" },
438 + { 9, GPIOF_IN, "ARM_DIO9" },
439 +};
440 +
441 +static struct gpio cambria_gpios_gw2358[] = {
442 + // ARM GPIO
443 +#if 0 // configured from bootloader
444 + { 0, GPIOF_IN, "*VINLOW#" },
445 + { 2, GPIOF_IN, "*GPS_PPS" },
446 + { 3, GPIOF_IN, "*GPS_IRQ#" },
447 + { 4, GPIOF_IN, "*RS485_IRQ#" },
448 + { 5, GPIOF_IN, "*SER_EN#" },
449 + { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
450 +#endif
451 +};
452 +
453 +static struct gpio cambria_gpios_gw2359[] = {
454 + // ARM GPIO
455 +#if 0 // configured from bootloader
456 + { 0, GPIOF_IN, "*PCA_IRQ#" },
457 + { 1, GPIOF_IN, "ARM_DIO1" },
458 + { 2, GPIOF_IN, "ARM_DIO2" },
459 + { 3, GPIOF_IN, "ARM_DIO3" },
460 + { 4, GPIOF_IN, "ARM_DIO4" },
461 + { 5, GPIOF_IN, "ARM_DIO5" },
462 + { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
463 +#endif
464 + { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable
465 + { 12, GPIOF_IN, "*GSC_IRQ#" },
466 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
467 + // GSC GPIO
468 +#if !(defined(CONFIG_INPUT_GPIO_BUTTONS) || defined(CONFIG_INPUT_GPIO_BUTTONS_MODULE))
469 + {100, GPIOF_IN, "*USER_PB#" },
470 +#endif
471 + {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable
472 + {108, GPIOF_IN, "*SMUXDA0" },
473 + {109, GPIOF_IN, "*SMUXDA1" },
474 + {110, GPIOF_IN, "*SMUXDA2" },
475 + {111, GPIOF_IN, "*SMUXDB0" },
476 + {112, GPIOF_IN, "*SMUXDB1" },
477 + {113, GPIOF_IN, "*SMUXDB2" },
478 + // PCA GPIO
479 + {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect
480 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP)
481 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP)
482 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
483 + {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10
484 + {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10
485 + {127, GPIOF_IN, "PCA_DIO0" },
486 + {128, GPIOF_IN, "PCA_DIO1" },
487 + {129, GPIOF_IN, "PCA_DIO2" },
488 + {130, GPIOF_IN, "PCA_DIO3" },
489 + {131, GPIOF_IN, "PCA_DIO4" },
490 +};
491 +
492 +static struct gpio cambria_gpios_gw2360[] = {
493 + // ARM GPIO
494 + { 0, GPIOF_IN, "*PCA_IRQ#" },
495 + { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" },
496 + { 12, GPIOF_IN, "*GSC_IRQ#" },
497 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
498 + // GSC GPIO
499 +#if !(defined(CONFIG_INPUT_GPIO_BUTTONS) || defined(CONFIG_INPUT_GPIO_BUTTONS_MODULE))
500 + {100, GPIOF_IN, "*USER_PB#" },
501 +#endif
502 + {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable
503 + {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present)
504 + {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable
505 + {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present)
506 + // PCA GPIO
507 + {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem)
508 + {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot)
509 + {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot)
510 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1)
511 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1)
512 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
513 + {127, GPIOF_IN, "DIO0" },
514 + {128, GPIOF_IN, "DIO1" },
515 + {129, GPIOF_IN, "DIO2" },
516 + {130, GPIOF_IN, "DIO3" },
517 + {131, GPIOF_IN, "DIO4" },
518 +};
519 +
520 +static struct platform_device cambria_gpio = {
521 + .name = "GPIODEV",
522 + .id = -1,
523 + .num_resources = ARRAY_SIZE(cambria_gpio_resources),
524 + .resource = cambria_gpio_resources,
525 +};
526 +
527 +static struct latch_led cambria_latch_leds[] = {
528 + {
529 + .name = "ledA", /* green led */
530 + .bit = 0,
531 + },
532 + {
533 + .name = "ledB", /* green led */
534 + .bit = 1,
535 + },
536 + {
537 + .name = "ledC", /* green led */
538 + .bit = 2,
539 + },
540 + {
541 + .name = "ledD", /* green led */
542 + .bit = 3,
543 + },
544 + {
545 + .name = "ledE", /* green led */
546 + .bit = 4,
547 + },
548 + {
549 + .name = "ledF", /* green led */
550 + .bit = 5,
551 + },
552 + {
553 + .name = "ledG", /* green led */
554 + .bit = 6,
555 + },
556 + {
557 + .name = "ledH", /* green led */
558 + .bit = 7,
559 + }
560 +};
561 +
562 +static struct latch_led_platform_data cambria_latch_leds_data = {
563 + .num_leds = 8,
564 + .leds = cambria_latch_leds,
565 + .mem = 0x53F40000,
566 +};
567 +
568 +static struct platform_device cambria_latch_leds_device = {
569 + .name = "leds-latch",
570 + .id = -1,
571 + .dev.platform_data = &cambria_latch_leds_data,
572 +};
573 +
574 +static struct resource cambria_usb0_resources[] = {
575 + {
576 + .start = 0xCD000000,
577 + .end = 0xCD000300,
578 + .flags = IORESOURCE_MEM,
579 + },
580 + {
581 + .start = 32,
582 + .flags = IORESOURCE_IRQ,
583 + },
584 +};
585 +
586 +static struct resource cambria_usb1_resources[] = {
587 + {
588 + .start = 0xCE000000,
589 + .end = 0xCE000300,
590 + .flags = IORESOURCE_MEM,
591 + },
592 + {
593 + .start = 33,
594 + .flags = IORESOURCE_IRQ,
595 + },
596 +};
597 +
598 +static u64 ehci_dma_mask = ~(u32)0;
599 +
600 +static struct platform_device cambria_usb0_device = {
601 + .name = "ixp4xx-ehci",
602 + .id = 0,
603 + .resource = cambria_usb0_resources,
604 + .num_resources = ARRAY_SIZE(cambria_usb0_resources),
605 + .dev = {
606 + .dma_mask = &ehci_dma_mask,
607 + .coherent_dma_mask = 0xffffffff,
608 + },
609 +};
610 +
611 +static struct platform_device cambria_usb1_device = {
612 + .name = "ixp4xx-ehci",
613 + .id = 1,
614 + .resource = cambria_usb1_resources,
615 + .num_resources = ARRAY_SIZE(cambria_usb1_resources),
616 + .dev = {
617 + .dma_mask = &ehci_dma_mask,
618 + .coherent_dma_mask = 0xffffffff,
619 + },
620 +};
621 +
622 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = {
623 + .gpio_base = 16,
624 + .nr_gpio = 8,
625 +};
626 +
627 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = {
628 + .gpio_base = 24,
629 + .nr_gpio = 2,
630 +};
631 +
632 +
633 +static struct gpio_button cambria_gpio_buttons[] = {
634 + {
635 + .desc = "user",
636 + .type = EV_KEY,
637 + .code = BTN_0,
638 + .threshold = 2,
639 + .gpio = 25,
640 + }
641 +};
642 +
643 +static struct gpio_buttons_platform_data cambria_gpio_buttons_data = {
644 + .poll_interval = 500,
645 + .nbuttons = 1,
646 + .buttons = cambria_gpio_buttons,
647 +};
648 +
649 +static struct platform_device cambria_gpio_buttons_device = {
650 + .name = "gpio-buttons",
651 + .id = -1,
652 + .dev.platform_data = &cambria_gpio_buttons_data,
653 +};
654 +
655 +static struct platform_device *cambria_devices[] __initdata = {
656 + &cambria_i2c_gpio,
657 + &cambria_flash,
658 + &cambria_uart,
659 +};
660 +
661 +static int cambria_register_gpio(struct gpio *array, size_t num)
662 +{
663 + int i, err, ret;
664 +
665 + ret = 0;
666 + for (i = 0; i < num; i++, array++) {
667 + const char *label = array->label;
668 + if (label[0] == '*')
669 + label++;
670 + err = gpio_request_one(array->gpio, array->flags, label);
671 + if (err)
672 + ret = err;
673 + else {
674 + err = gpio_export(array->gpio, array->label[0] != '*');
675 + }
676 + }
677 + return ret;
678 +}
679 +
680 +static void __init cambria_gw23xx_setup(void)
681 +{
682 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
683 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
684 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
685 +
686 + platform_device_register(&cambria_gpio);
687 + platform_device_register(&cambria_npec_device);
688 + platform_device_register(&cambria_npea_device);
689 +}
690 +
691 +static void __init cambria_gw2350_setup(void)
692 +{
693 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
694 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
695 + cambria_optional_uart_data[0].mapbase = 0x52FF0000;
696 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
697 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
698 +
699 + *IXP4XX_EXP_CS3 = 0xBFFF3C43;
700 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
701 + cambria_optional_uart_data[1].mapbase = 0x53FF0000;
702 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
703 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
704 +
705 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
706 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
707 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
708 +
709 + platform_device_register(&cambria_gpio);
710 + platform_device_register(&cambria_optional_uart);
711 + platform_device_register(&cambria_npec_device);
712 + platform_device_register(&cambria_npea_device);
713 +
714 + platform_device_register(&cambria_usb0_device);
715 + platform_device_register(&cambria_usb1_device);
716 +
717 + platform_device_register(&cambria_gpio_leds_device);
718 +
719 + /* gpio config (/sys/class/gpio) */
720 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350));
721 +}
722 +
723 +static void __init cambria_gw2358_setup(void)
724 +{
725 + *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus
726 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
727 + cambria_optional_uart_data[0].mapbase = 0x53FC0000;
728 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
729 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
730 +
731 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
732 + cambria_optional_uart_data[1].mapbase = 0x53F80000;
733 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
734 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
735 +
736 + cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\
737 + (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25);
738 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
739 +
740 + platform_device_register(&cambria_gpio);
741 + platform_device_register(&cambria_optional_uart);
742 +
743 + platform_device_register(&cambria_npec_device);
744 + platform_device_register(&cambria_npea_device);
745 +
746 + platform_device_register(&cambria_usb0_device);
747 + platform_device_register(&cambria_usb1_device);
748 +
749 + platform_device_register(&cambria_pata);
750 +
751 + cambria_gpio_leds[0].gpio = 24;
752 + platform_device_register(&cambria_gpio_leds_device);
753 +
754 + platform_device_register(&cambria_latch_leds_device);
755 +
756 + platform_device_register(&cambria_gpio_buttons_device);
757 +
758 + /* gpio config (/sys/class/gpio) */
759 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358));
760 +}
761 +
762 +static void __init cambria_gw2359_setup(void)
763 +{
764 + platform_device_register(&cambria_gpio);
765 +
766 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
767 + /* The mvswitch driver has some hard-coded values which could
768 + * easily be turned into a platform resource if needed. For now they
769 + * match our hardware configuration:
770 + * MV_BASE 0x10 - phy base address
771 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
772 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
773 + *
774 + * The mvswitch driver registers a fixup which forces a driver match
775 + * if phy_addr matches MV_BASE
776 + *
777 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
778 + * in the other.
779 + */
780 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
781 +#else
782 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver
783 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
784 + // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14
785 + cambria_npec_data.phy = 0x14;
786 +#endif
787 + platform_device_register(&cambria_npec_device);
788 + platform_device_register(&cambria_npea_device);
789 +
790 + platform_device_register(&cambria_usb0_device);
791 + platform_device_register(&cambria_usb1_device);
792 +
793 + cambria_gpio_leds_data.num_leds = 3;
794 + cambria_gpio_leds[0].name = "user1";
795 + cambria_gpio_leds[0].gpio = 125; // PNLLED1#
796 + cambria_gpio_leds[1].gpio = 126; // PNLLED3#
797 + cambria_gpio_leds[2].gpio = 119; // PNLLED4#
798 + platform_device_register(&cambria_gpio_leds_device);
799 +
800 +#if (defined(CONFIG_INPUT_GPIO_BUTTONS) || defined(CONFIG_INPUT_GPIO_BUTTONS_MODULE))
801 + cambria_gpio_buttons[0].gpio = 100;
802 + platform_device_register(&cambria_gpio_buttons_device);
803 +#endif
804 +
805 + /* gpio config (/sys/class/gpio) */
806 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359));
807 +}
808 +
809 +static void __init cambria_gw2360_setup(void)
810 +{
811 + /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART.
812 + * The chip-selects are expanded via a 3-to-8 decoder and CS2
813 + * and they are 8bit devices
814 + */
815 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
816 + cambria_optional_uart_data[0].mapbase = 0x52000000;
817 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff);
818 + cambria_optional_uart_data[0].uartclk = 18432000;
819 + cambria_optional_uart_data[0].iotype = UPIO_MEM;
820 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2;
821 + irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING);
822 +
823 + cambria_optional_uart_data[1].mapbase = 0x52000008;
824 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff);
825 + cambria_optional_uart_data[1].uartclk = 18432000;
826 + cambria_optional_uart_data[1].iotype = UPIO_MEM;
827 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3;
828 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
829 +
830 + cambria_optional_uart_data[2].mapbase = 0x52000010;
831 + cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff);
832 + cambria_optional_uart_data[2].uartclk = 18432000;
833 + cambria_optional_uart_data[2].iotype = UPIO_MEM;
834 + cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4;
835 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
836 +
837 + cambria_optional_uart_data[3].mapbase = 0x52000018;
838 + cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff);
839 + cambria_optional_uart_data[3].uartclk = 18432000;
840 + cambria_optional_uart_data[3].iotype = UPIO_MEM;
841 + cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5;
842 + irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING);
843 +
844 + cambria_optional_uart_data[4].mapbase = 0x52000020;
845 + cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff);
846 + cambria_optional_uart_data[4].uartclk = 18432000;
847 + cambria_optional_uart_data[4].iotype = UPIO_MEM;
848 + cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8;
849 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING);
850 +
851 + cambria_optional_uart_data[5].mapbase = 0x52000028;
852 + cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff);
853 + cambria_optional_uart_data[5].uartclk = 18432000;
854 + cambria_optional_uart_data[5].iotype = UPIO_MEM;
855 + cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9;
856 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING);
857 +
858 + cambria_optional_uart_data[6].mapbase = 0x52000030;
859 + cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff);
860 + cambria_optional_uart_data[6].uartclk = 18432000;
861 + cambria_optional_uart_data[6].iotype = UPIO_MEM;
862 + cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10;
863 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING);
864 +
865 + cambria_optional_uart.num_resources = 7,
866 + platform_device_register(&cambria_optional_uart);
867 +
868 + platform_device_register(&cambria_gpio);
869 +
870 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
871 + /* The mvswitch driver has some hard-coded values which could
872 + * easily be turned into a platform resource if needed. For now they
873 + * match our hardware configuration:
874 + * MV_BASE 0x10 - phy base address
875 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
876 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
877 + *
878 + * The mvswitch driver registers a fixup which forces a driver match
879 + * if phy_addr matches MV_BASE
880 + *
881 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
882 + * in the other.
883 + */
884 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
885 +#else
886 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver
887 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
888 +#endif
889 +
890 + // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX
891 + //cambria_npec_data.noautoneg = 1; // disable autoneg
892 + cambria_npec_data.speed_10 = 0; // 100mbps
893 + cambria_npec_data.half_duplex = 0; // full-duplex
894 + platform_device_register(&cambria_npec_device);
895 + platform_device_register(&cambria_npea_device);
896 +
897 + platform_device_register(&cambria_usb0_device);
898 + platform_device_register(&cambria_usb1_device);
899 +
900 + cambria_gpio_leds_data.num_leds = 3;
901 + cambria_gpio_leds[0].name = "user1";
902 + cambria_gpio_leds[0].gpio = 125;
903 + cambria_gpio_leds[1].gpio = 126;
904 + cambria_gpio_leds[2].gpio = 119;
905 + platform_device_register(&cambria_gpio_leds_device);
906 +
907 +#if (defined(CONFIG_INPUT_GPIO_BUTTONS) || defined(CONFIG_INPUT_GPIO_BUTTONS_MODULE))
908 + cambria_gpio_buttons[0].gpio = 100;
909 + platform_device_register(&cambria_gpio_buttons_device);
910 +#endif
911 +
912 +#ifdef SFP_SERIALID
913 + /* the SFP modules each have an i2c bus for serial ident via GSC GPIO
914 + * To use these the i2c-gpio driver must be changed to use the _cansleep
915 + * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't
916 + * use that anyway as it doesn't operate in an IRQ context).
917 + * Additionally the i2c-gpio module must set the gpio to output-high prior
918 + * to changing direction to an input to enable internal Pullups
919 + */
920 + platform_device_register(&cambria_i2c_gpio_sfpa);
921 + platform_device_register(&cambria_i2c_gpio_sfpb);
922 +#endif
923 +
924 + /* gpio config (/sys/class/gpio) */
925 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360));
926 +}
927 +
928 +static struct cambria_board_info cambria_boards[] __initdata = {
929 + {
930 + .model = "GW2350",
931 + .setup = cambria_gw2350_setup,
932 + }, {
933 + .model = "GW2351",
934 + .setup = cambria_gw2350_setup,
935 + }, {
936 + .model = "GW2358",
937 + .setup = cambria_gw2358_setup,
938 + }, {
939 + .model = "GW2359",
940 + .setup = cambria_gw2359_setup,
941 + }, {
942 + .model = "GW2360",
943 + .setup = cambria_gw2360_setup,
944 + }, {
945 + .model = "GW2371",
946 + .setup = cambria_gw2358_setup,
947 + }
948 +};
949 +
950 +static struct cambria_board_info * __init cambria_find_board_info(char *model)
951 +{
952 + int i;
953 + model[6] = '\0';
954 +
955 + for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
956 + struct cambria_board_info *info = &cambria_boards[i];
957 + if (strcmp(info->model, model) == 0)
958 + return info;
959 + }
960 +
961 + return NULL;
962 +}
963 +
964 +static struct memory_accessor *at24_mem_acc;
965 +
966 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
967 +{
968 + char mac_addr[ETH_ALEN];
969 + char model[7];
970 +
971 + at24_mem_acc = mem_acc;
972 +
973 + /* Read MAC addresses */
974 + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) {
975 + memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN);
976 + }
977 + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) {
978 + memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN);
979 + }
980 +
981 + /* Read the first 6 bytes of the model number */
982 + if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) {
983 + cambria_info = cambria_find_board_info(model);
984 + }
985 +
986 +}
987 +
988 +static struct at24_platform_data cambria_eeprom_info = {
989 + .byte_len = 1024,
990 + .page_size = 16,
991 + .flags = AT24_FLAG_READONLY,
992 + .setup = at24_setup,
993 +};
994 +
995 +static struct pca953x_platform_data cambria_pca_data = {
996 + .gpio_base = 100,
997 + .irq_base = -1,
998 +};
999 +
1000 +static struct pca953x_platform_data cambria_pca2_data = {
1001 + .gpio_base = 116,
1002 + .irq_base = -1,
1003 +};
1004 +
1005 +static struct i2c_board_info __initdata cambria_i2c_board_info[] = {
1006 + {
1007 + I2C_BOARD_INFO("pca9555", 0x23),
1008 + .platform_data = &cambria_pca_data,
1009 + },
1010 + {
1011 + I2C_BOARD_INFO("pca9555", 0x27),
1012 + .platform_data = &cambria_pca2_data,
1013 + },
1014 + {
1015 + I2C_BOARD_INFO("ds1672", 0x68),
1016 + },
1017 + {
1018 + I2C_BOARD_INFO("gsp", 0x29),
1019 + },
1020 + {
1021 + I2C_BOARD_INFO("ad7418", 0x28),
1022 + },
1023 + {
1024 + I2C_BOARD_INFO("24c08", 0x51),
1025 + .platform_data = &cambria_eeprom_info
1026 + },
1027 + {
1028 + I2C_BOARD_INFO("gw_i2c_pld", 0x56),
1029 + .platform_data = &gw_i2c_pld_data0,
1030 + },
1031 + {
1032 + I2C_BOARD_INFO("gw_i2c_pld", 0x57),
1033 + .platform_data = &gw_i2c_pld_data1,
1034 + },
1035 +};
1036 +
1037 +static void __init cambria_init(void)
1038 +{
1039 + ixp4xx_sys_init();
1040 +
1041 + cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
1042 + cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
1043 +
1044 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable
1045 + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
1046 +
1047 + platform_add_devices(ARRAY_AND_SIZE(cambria_devices));
1048 +
1049 + cambria_pata_resources[0].start = 0x53e00000;
1050 + cambria_pata_resources[0].end = 0x53e3ffff;
1051 +
1052 + cambria_pata_resources[1].start = 0x53e40000;
1053 + cambria_pata_resources[1].end = 0x53e7ffff;
1054 +
1055 + cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
1056 + cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
1057 +
1058 + i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info));
1059 +}
1060 +
1061 +static int __init cambria_model_setup(void)
1062 +{
1063 + if (!machine_is_cambria())
1064 + return 0;
1065 +
1066 + if (cambria_info) {
1067 + printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
1068 + cambria_info->model);
1069 + cambria_info->setup();
1070 + } else {
1071 + printk(KERN_INFO "Unknown/missing Cambria model number"
1072 + " -- defaults will be used\n");
1073 + cambria_gw23xx_setup();
1074 + }
1075 +
1076 + return 0;
1077 +}
1078 +late_initcall(cambria_model_setup);
1079 +
1080 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
1081 + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
1082 + .map_io = ixp4xx_map_io,
1083 + .init_irq = ixp4xx_init_irq,
1084 + .timer = &ixp4xx_timer,
1085 + .atag_offset = 0x0100,
1086 + .init_machine = cambria_init,
1087 +#if defined(CONFIG_PCI)
1088 + .dma_zone_size = SZ_64M,
1089 +#endif
1090 + .restart = ixp4xx_restart,
1091 +MACHINE_END
1092 --- a/arch/arm/mach-ixp4xx/Kconfig
1093 +++ b/arch/arm/mach-ixp4xx/Kconfig
1094 @@ -25,6 +25,14 @@ config MACH_AVILA
1095 Avila Network Platform. For more information on this platform,
1096 see <file:Documentation/arm/IXP4xx>.
1097
1098 +config MACH_CAMBRIA
1099 + bool "Cambria"
1100 + select PCI
1101 + help
1102 + Say 'Y' here if you want your kernel to support the Gateworks
1103 + Cambria series. For more information on this platform,
1104 + see <file:Documentation/arm/IXP4xx>.
1105 +
1106 config MACH_LOFT
1107 bool "Loft"
1108 depends on MACH_AVILA
1109 @@ -222,7 +230,7 @@ config CPU_IXP46X
1110
1111 config CPU_IXP43X
1112 bool
1113 - depends on MACH_KIXRP435
1114 + depends on MACH_KIXRP435 || MACH_CAMBRIA
1115 default y
1116
1117 config MACH_GTWX5715
1118 --- a/arch/arm/mach-ixp4xx/Makefile
1119 +++ b/arch/arm/mach-ixp4xx/Makefile
1120 @@ -7,6 +7,7 @@ obj-pci-n :=
1121
1122 obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
1123 obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
1124 +obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
1125 obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
1126 obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
1127 obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
1128 @@ -31,6 +32,7 @@ obj-y += common.o
1129
1130 obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
1131 obj-$(CONFIG_MACH_AVILA) += avila-setup.o
1132 +obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
1133 obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
1134 obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
1135 obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
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