kirkwood: add linux 3.10 support
[openwrt/svn-archive/archive.git] / target / linux / kirkwood / patches-3.10 / 0011-arm-kirkwood-add-SoC-level-Device-Tree-data-for-PCIe.patch
1 From 8725a4f93dcb242466990261dc2bd78599b0306a Mon Sep 17 00:00:00 2001
2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 Date: Wed, 27 Mar 2013 18:55:20 +0100
4 Subject: [PATCH 11/29] arm: kirkwood: add SoC-level Device Tree data for PCIe
5 interfaces
6
7 This commit adds Device Tree details to enable the PCIe interfaces on
8 Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe
9 interfaces.
10
11 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 Tested-by: Andrew Lunn <andrew@lunn.ch>
13 ---
14 arch/arm/boot/dts/kirkwood-6281.dtsi | 31 +++++++++++++++++++++++
15 arch/arm/boot/dts/kirkwood-6282.dtsi | 48 ++++++++++++++++++++++++++++++++++++
16 arch/arm/boot/dts/kirkwood.dtsi | 1 +
17 3 files changed, 80 insertions(+)
18
19 diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
20 index d6c9d65..5137668 100644
21 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi
22 +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
23 @@ -40,5 +40,36 @@
24 marvell,function = "sdio";
25 };
26 };
27 +
28 + pcie-controller {
29 + compatible = "marvell,kirkwood-pcie";
30 + status = "disabled";
31 + device_type = "pci";
32 +
33 + #address-cells = <3>;
34 + #size-cells = <2>;
35 +
36 + bus-range = <0x00 0xff>;
37 +
38 + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
39 + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
40 + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
41 +
42 + pcie@1,0 {
43 + device_type = "pci";
44 + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
45 + reg = <0x0800 0 0 0 0>;
46 + #address-cells = <3>;
47 + #size-cells = <2>;
48 + #interrupt-cells = <1>;
49 + ranges;
50 + interrupt-map-mask = <0 0 0 0>;
51 + interrupt-map = <0 0 0 0 &intc 9>;
52 + marvell,pcie-port = <0>;
53 + marvell,pcie-lane = <0>;
54 + clocks = <&gate_clk 2>;
55 + status = "disabled";
56 + };
57 + };
58 };
59 };
60 diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
61 index 23991e4..66a751a 100644
62 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi
63 +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
64 @@ -65,5 +65,53 @@
65 clocks = <&gate_clk 7>;
66 status = "disabled";
67 };
68 +
69 + pcie-controller {
70 + compatible = "marvell,kirkwood-pcie";
71 + status = "disabled";
72 + device_type = "pci";
73 +
74 + #address-cells = <3>;
75 + #size-cells = <2>;
76 +
77 + bus-range = <0x00 0xff>;
78 +
79 + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
80 + 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
81 + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
82 + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
83 +
84 + pcie@1,0 {
85 + device_type = "pci";
86 + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
87 + reg = <0x0800 0 0 0 0>;
88 + #address-cells = <3>;
89 + #size-cells = <2>;
90 + #interrupt-cells = <1>;
91 + ranges;
92 + interrupt-map-mask = <0 0 0 0>;
93 + interrupt-map = <0 0 0 0 &intc 9>;
94 + marvell,pcie-port = <0>;
95 + marvell,pcie-lane = <0>;
96 + clocks = <&gate_clk 2>;
97 + status = "disabled";
98 + };
99 +
100 + pcie@2,0 {
101 + device_type = "pci";
102 + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
103 + reg = <0x1000 0 0 0 0>;
104 + #address-cells = <3>;
105 + #size-cells = <2>;
106 + #interrupt-cells = <1>;
107 + ranges;
108 + interrupt-map-mask = <0 0 0 0>;
109 + interrupt-map = <0 0 0 0 &intc 10>;
110 + marvell,pcie-port = <1>;
111 + marvell,pcie-lane = <0>;
112 + clocks = <&gate_clk 18>;
113 + status = "disabled";
114 + };
115 + };
116 };
117 };
118 diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
119 index fada7e6..7eef88f 100644
120 --- a/arch/arm/boot/dts/kirkwood.dtsi
121 +++ b/arch/arm/boot/dts/kirkwood.dtsi
122 @@ -19,6 +19,7 @@
123 ocp@f1000000 {
124 compatible = "simple-bus";
125 ranges = <0x00000000 0xf1000000 0x4000000
126 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */
127 0xf5000000 0xf5000000 0x0000400>;
128 #address-cells = <1>;
129 #size-cells = <1>;
130 --
131 1.8.4.rc1
132