target/linux/kirkwood/patches-3.10/0024-net-mv643xx_eth-proper-initialization-for-Kirkwood-S.patch

   1 From 4c1ae9f272bf34388d0fbdc99aa18af2b6c9eda1 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   3 Date: Wed, 29 May 2013 09:32:47 +0000
   4 Subject: [PATCH 24/29] net: mv643xx_eth: proper initialization for Kirkwood
   5  SoCs
   6
   7 Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
   8 MAC address register contents on clock gating but also some important
   9 registers are reset to values that would break ethernet. This patch
  10 clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
  11 of_device_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
  12 affected as it installs a clock gating workaround because of the MAC
  13 address issue above. Other Orion SoCs do not suffer from register reset,
  14 do not have the bit in question, or do not have the register at all.
  15 Moreover, system controllers on PPC using this driver should also be
  16 protected from clearing that bit.
  17
  18 Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  19 Signed-off-by: David S. Miller <davem@davemloft.net>
  20 ---
  21  drivers/net/ethernet/marvell/mv643xx_eth.c | 11 +++++++++++
  22  1 file changed, 11 insertions(+)
  23
  24 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
  25 +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
  26 @@ -116,6 +116,8 @@ static char mv643xx_eth_driver_version[]
  27  #define  LINK_UP                       0x00000002
  28  #define TXQ_COMMAND                    0x0048
  29  #define TXQ_FIX_PRIO_CONF              0x004c
  30 +#define PORT_SERIAL_CONTROL1           0x004c
  31 +#define  CLK125_BYPASS_EN              0x00000010
  32  #define TX_BW_RATE                     0x0050
  33  #define TX_BW_MTU                      0x0058
  34  #define TX_BW_BURST                    0x005c
  35 @@ -2701,6 +2703,15 @@ static int mv643xx_eth_probe(struct plat
  36
  37         mp->dev = dev;
  38
  39 +       /* Kirkwood resets some registers on gated clocks. Especially
  40 +        * CLK125_BYPASS_EN must be cleared but is not available on
  41 +        * all other SoCs/System Controllers using this driver.
  42 +        */
  43 +       if (of_device_is_compatible(pdev->dev.of_node,
  44 +                                   "marvell,kirkwood-eth-port"))
  45 +               wrlp(mp, PORT_SERIAL_CONTROL1,
  46 +                    rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
  47 +
  48         /*
  49          * Start with a default rate, and if there is a clock, allow
  50          * it to override the default.