[lantiq]
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-2.6.39 / 110-falcon_board.patch
1 --- /dev/null
2 +++ b/arch/mips/lantiq/falcon/Kconfig
3 @@ -0,0 +1,11 @@
4 +if SOC_FALCON
5 +
6 +menu "Mips Machine"
7 +
8 +config LANTIQ_MACH_EASY98000
9 + bool "Easy98000"
10 + default y
11 +
12 +endmenu
13 +
14 +endif
15 --- /dev/null
16 +++ b/arch/mips/lantiq/falcon/Makefile
17 @@ -0,0 +1,3 @@
18 +obj-y := clk-falcon.o devices.o gpio.o prom.o sysctrl.o reset.o
19 +obj-y += softdog_vpe.o
20 +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
21 --- /dev/null
22 +++ b/arch/mips/lantiq/falcon/clk-falcon.c
23 @@ -0,0 +1,48 @@
24 +/*
25 + * This program is free software; you can redistribute it and/or modify
26 + * it under the terms of the GNU General Public License as published by
27 + * the Free Software Foundation; either version 2 of the License, or
28 + * (at your option) any later version.
29 + *
30 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
31 + */
32 +
33 +#include <linux/io.h>
34 +#include <linux/module.h>
35 +#include <linux/init.h>
36 +
37 +#include <asm/time.h>
38 +#include <asm/irq.h>
39 +#include <asm/div64.h>
40 +
41 +#include <lantiq_soc.h>
42 +
43 +#include <falcon.h>
44 +#include <gpon_reg_base.h>
45 +#include <sys1_reg.h>
46 +
47 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
48 +
49 +unsigned int
50 +ltq_get_io_region_clock(void)
51 +{
52 + return 200000000; /* 200 MHz */
53 +}
54 +EXPORT_SYMBOL(ltq_get_io_region_clock);
55 +
56 +unsigned int
57 +ltq_get_cpu_hz(void)
58 +{
59 + if ((ltq_r32(&pSYS1->cpu0cc) & CPU0CC_CPUDIV) == CPU0CC_CPUDIV_SELFHALF)
60 + return 200000000; /* 200 MHz */
61 + else
62 + return 400000000; /* 400 MHz */
63 +}
64 +EXPORT_SYMBOL(ltq_get_cpu_hz);
65 +
66 +unsigned int
67 +ltq_get_fpi_hz(void)
68 +{
69 + return 100000000;
70 +}
71 +EXPORT_SYMBOL(ltq_get_fpi_hz);
72 --- /dev/null
73 +++ b/arch/mips/lantiq/falcon/devices.c
74 @@ -0,0 +1,180 @@
75 +#include <linux/init.h>
76 +#include <linux/module.h>
77 +#include <linux/types.h>
78 +#include <linux/string.h>
79 +#include <linux/mtd/physmap.h>
80 +#include <linux/kernel.h>
81 +#include <linux/reboot.h>
82 +#include <linux/platform_device.h>
83 +#include <linux/leds.h>
84 +#include <linux/etherdevice.h>
85 +#include <linux/reboot.h>
86 +#include <linux/time.h>
87 +#include <linux/io.h>
88 +#include <linux/gpio.h>
89 +#include <linux/leds.h>
90 +#include <linux/spi/spi.h>
91 +
92 +#include <asm/bootinfo.h>
93 +#include <asm/irq.h>
94 +
95 +#include <lantiq.h>
96 +
97 +#include <falcon/falcon_irq.h>
98 +#include <falcon/gpon_reg_base.h>
99 +#include <falcon/sys1_reg.h>
100 +#include <falcon/sys_eth_reg.h>
101 +
102 +#include <falcon/sysctrl.h>
103 +
104 +#include "devices.h"
105 +
106 +unsigned char ltq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
107 +EXPORT_SYMBOL(ltq_ethaddr);
108 +
109 +static int __init
110 +falcon_set_ethaddr(char *str)
111 +{
112 + sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
113 + &ltq_ethaddr[0], &ltq_ethaddr[1], &ltq_ethaddr[2],
114 + &ltq_ethaddr[3], &ltq_ethaddr[4], &ltq_ethaddr[5]);
115 + return 0;
116 +}
117 +__setup("ethaddr=", falcon_set_ethaddr);
118 +
119 +/* asc ports */
120 +static struct resource falcon_asc0_resources[] =
121 +{
122 + MEM_RES("asc0",GPON_ASC0_BASE,GPON_ASC0_END),
123 + IRQ_RES("tx",INT_NUM_IM3_IRL0),
124 + IRQ_RES("rx",INT_NUM_IM3_IRL0+1),
125 + IRQ_RES("err",INT_NUM_IM3_IRL0+2),
126 +};
127 +
128 +static struct resource falcon_asc1_resources[] =
129 +{
130 + MEM_RES("asc1",GPON_ASC1_BASE,GPON_ASC1_END),
131 + IRQ_RES("tx",INT_NUM_IM3_IRL0+8),
132 + IRQ_RES("rx",INT_NUM_IM3_IRL0+9),
133 + IRQ_RES("err",INT_NUM_IM3_IRL0+10),
134 +};
135 +
136 +void __init falcon_register_asc(int port)
137 +{
138 + switch (port) {
139 + case 0:
140 + platform_device_register_simple("ltq_asc", 0,
141 + falcon_asc0_resources, ARRAY_SIZE(falcon_asc0_resources));
142 + break;
143 + case 1:
144 + platform_device_register_simple("ltq_asc", 1,
145 + falcon_asc1_resources, ARRAY_SIZE(falcon_asc1_resources));
146 + break;
147 + default:
148 + break;
149 + }
150 +}
151 +
152 +/* nor flash */
153 +static struct resource ltq_nor_resource =
154 + MEM_RES("nor",LTQ_FLASH_START,LTQ_FLASH_START + LTQ_FLASH_MAX - 1);
155 +
156 +static struct platform_device ltq_nor = {
157 + .name = "ltq_nor",
158 + .resource = &ltq_nor_resource,
159 + .num_resources = 1,
160 +};
161 +
162 +void __init falcon_register_nor(struct physmap_flash_data *data)
163 +{
164 + ltq_nor.dev.platform_data = data;
165 + platform_device_register(&ltq_nor);
166 +}
167 +
168 +/* spi flash */
169 +static struct resource ltq_spi_resources[] = {
170 + MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
171 + MEM_RES("sys1", GPON_SYS1_BASE, GPON_SYS1_END)
172 +};
173 +
174 +static struct platform_device ltq_spi = {
175 + .name = "falcon_spi",
176 + .resource = ltq_spi_resources,
177 + .num_resources = ARRAY_SIZE(ltq_spi_resources)
178 +};
179 +
180 +void __init falcon_register_spi_flash(struct spi_board_info *data)
181 +{
182 + spi_register_board_info(data, 1);
183 + platform_device_register(&ltq_spi);
184 +}
185 +
186 +/* watchdog */
187 +static struct resource falcon_wdt_resource =
188 + MEM_RES("watchdog",GPON_WDT_BASE,GPON_WDT_END);
189 +
190 +void __init falcon_register_wdt(void)
191 +{
192 + platform_device_register_simple("ltq_wdt", 0, &falcon_wdt_resource, 1);
193 +}
194 +
195 +/* gpio */
196 +#define DECLARE_GPIO_RES(port) \
197 +static struct resource falcon_gpio ## port ## _resources[] = { \
198 + MEM_RES("gpio"#port,GPON_GPIO ## port ## _BASE,GPON_GPIO ## port ## _END), \
199 + MEM_RES("padctrl"#port,GPON_PADCTRL ## port ## _BASE,GPON_PADCTRL ## port ## _END), \
200 + IRQ_RES("gpio_mux"#port,FALCON_IRQ_GPIO_P ## port ) \
201 +}
202 +DECLARE_GPIO_RES(0);
203 +DECLARE_GPIO_RES(1);
204 +DECLARE_GPIO_RES(2);
205 +#ifdef REGISTER_ALL_GPIO_PORTS
206 +#if NR_IRQS < 328
207 +#error NR_IRQS to low for all gpio irqs
208 +#endif
209 +DECLARE_GPIO_RES(3);
210 +DECLARE_GPIO_RES(4);
211 +#endif
212 +
213 +void __init falcon_register_gpio(void)
214 +{
215 + platform_device_register_simple("falcon_gpio", 0,
216 + falcon_gpio0_resources, ARRAY_SIZE(falcon_gpio0_resources));
217 + platform_device_register_simple("falcon_gpio", 1,
218 + falcon_gpio1_resources, ARRAY_SIZE(falcon_gpio1_resources));
219 + platform_device_register_simple("falcon_gpio", 2,
220 + falcon_gpio2_resources, ARRAY_SIZE(falcon_gpio2_resources));
221 + sys1_hw_activate(ACTS_PADCTRL1 | ACTS_P1);
222 + sys_eth_hw_activate(SYS_ETH_ACTS_PADCTRL0 | SYS_ETH_ACTS_PADCTRL2 |
223 + SYS_ETH_ACTS_P0 | SYS_ETH_ACTS_P2);
224 +
225 +#ifdef REGISTER_ALL_GPIO_PORTS
226 + /* optional gpio ports: not registered,
227 + as the pins are EBU specific and always used by linux */
228 + platform_device_register_simple("falcon_gpio", 3,
229 + falcon_gpio3_resources, ARRAY_SIZE(falcon_gpio3_resources));
230 + platform_device_register_simple("falcon_gpio", 4,
231 + falcon_gpio4_resources, ARRAY_SIZE(falcon_gpio4_resources));
232 + sys1_hw_activate(ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
233 +#endif
234 +}
235 +
236 +static struct resource falcon_i2c_resources[] = {
237 + MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
238 + IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
239 + IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
240 + IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
241 + IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
242 +};
243 +
244 +void __init falcon_register_i2c(void)
245 +{
246 + platform_device_register_simple("i2c-falcon", 0,
247 + falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
248 + sys1_hw_activate(ACTS_I2C_ACT);
249 +}
250 +
251 +void __init falcon_register_crypto(void)
252 +{
253 + platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
254 +}
255 --- /dev/null
256 +++ b/arch/mips/lantiq/falcon/devices.h
257 @@ -0,0 +1,21 @@
258 +#ifndef _FALCON_DEVICES_H__
259 +#define _FALCON_DEVICES_H__
260 +
261 +#include <linux/mtd/physmap.h>
262 +#include <linux/spi/spi.h>
263 +#include <linux/spi/flash.h>
264 +
265 +extern void __init falcon_register_asc(int port);
266 +extern void __init falcon_register_i2c(void);
267 +extern void __init falcon_register_spi_flash(struct spi_board_info *data);
268 +extern void __init falcon_register_gpio(void);
269 +extern void __init falcon_register_nor(struct physmap_flash_data *data);
270 +extern void __init falcon_register_wdt(void);
271 +extern void __init falcon_register_crypto(void);
272 +
273 +#define IRQ_RES(resname,irq) {.name=resname,.start=(irq),.flags=IORESOURCE_IRQ}
274 +#define MEM_RES(resname,adr_start,adr_end) \
275 + { .name=resname, .flags=IORESOURCE_MEM, \
276 + .start=((adr_start)&~KSEG1),.end=((adr_end)&~KSEG1) }
277 +
278 +#endif
279 --- /dev/null
280 +++ b/arch/mips/lantiq/falcon/prom.c
281 @@ -0,0 +1,52 @@
282 +/*
283 + * This program is free software; you can redistribute it and/or modify
284 + * it under the terms of the GNU General Public License as published by
285 + * the Free Software Foundation; either version 2 of the License, or
286 + * (at your option) any later version.
287 + *
288 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
289 + */
290 +
291 +#include <linux/module.h>
292 +#include <linux/clk.h>
293 +#include <asm/bootinfo.h>
294 +#include <asm/time.h>
295 +
296 +#include <lantiq_soc.h>
297 +
298 +#include <falcon.h>
299 +
300 +#include <falcon/gpon_reg_base.h>
301 +#include <falcon/status_reg.h>
302 +#include <falcon/sys1_reg.h>
303 +
304 +#include "../prom.h"
305 +
306 +static struct gpon_reg_status * const pSTATUS = (struct gpon_reg_status *)GPON_STATUS_BASE;
307 +
308 +#define SOC_FALCON "Falcon"
309 +
310 +void __init
311 +ltq_soc_setup(void)
312 +{
313 + /* not used */
314 +}
315 +
316 +void __init
317 +ltq_soc_detect(struct ltq_soc_info *i)
318 +{
319 + i->partnum = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_PARTNR_MASK) >> STATUS_CHIPID_PARTNR_OFFSET;
320 + i->rev = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_VERSION_MASK) >> STATUS_CHIPID_VERSION_OFFSET;
321 + switch (i->partnum)
322 + {
323 + case SOC_ID_FALCON:
324 + i->name = SOC_FALCON;
325 + i->type = SOC_TYPE_FALCON;
326 + break;
327 +
328 + default:
329 + printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum);
330 + while(1) { };
331 + break;
332 + }
333 +}
334 --- /dev/null
335 +++ b/arch/mips/lantiq/falcon/sysctrl.c
336 @@ -0,0 +1,381 @@
337 +/*
338 + * This program is free software; you can redistribute it and/or
339 + * modify it under the terms of the GNU General Public License as
340 + * published by the Free Software Foundation; either version 2 of
341 + * the License, or (at your option) any later version.
342 + *
343 + * This program is distributed in the hope that it will be useful,
344 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
345 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
346 + * GNU General Public License for more details.
347 + *
348 + * You should have received a copy of the GNU General Public License
349 + * along with this program; if not, write to the Free Software
350 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
351 + * MA 02111-1307 USA
352 + *
353 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
354 + */
355 +
356 +#include <linux/cpu.h>
357 +#include <linux/init.h>
358 +#include <linux/kernel.h>
359 +#include <linux/pm.h>
360 +#include <linux/io.h>
361 +#include <linux/ioport.h>
362 +#include <linux/clk.h>
363 +#include <asm/reboot.h>
364 +
365 +#include <falcon/gpon_reg_base.h>
366 +#include <falcon/status_reg.h>
367 +#include <falcon/sys1_reg.h>
368 +#include <falcon/sys_eth_reg.h>
369 +#include <falcon/sys_gpe_reg.h>
370 +
371 +#include <falcon/sysctrl.h>
372 +
373 +/* mapping to linux hw-accessor routines */
374 +#define reg_r32(reg) __raw_readl(reg)
375 +#define reg_w32(val, reg) __raw_writel(val, reg)
376 +#define reg_w32_mask(clear, set, reg) reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
377 +
378 +static struct gpon_reg_sys1 * const sys1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
379 +static struct gpon_reg_sys_eth * const sys_eth = (struct gpon_reg_sys_eth *)GPON_SYS_ETH_BASE;
380 +static struct gpon_reg_sys_gpe * const sys_gpe = (struct gpon_reg_sys_gpe *)GPON_SYS_GPE_BASE;
381 +static struct gpon_reg_status * const status = (struct gpon_reg_status *)GPON_STATUS_BASE;
382 +
383 +/**
384 + * Activate the selected module(s)
385 + * Enables the clock of the module and activates the module itself.
386 + *
387 + * \param[in] mask bitmask of module(s), as for registers SYS1.ACT
388 + * \return void
389 + */
390 +void sys1_hw_activate(u32 mask)
391 +{
392 + sys1_w32(mask, clken);
393 + sys1_w32(mask, act);
394 +
395 + while ( (sys1_r32(acts) & mask) != mask) {
396 + /*NOP;*/
397 + };
398 +}
399 +EXPORT_SYMBOL(sys1_hw_activate);
400 +
401 +/**
402 + * Deactivate the selected module(s)
403 + * Disables the clock of the module and deactivates the module itself.
404 + *
405 + * \param[in] mask bitmask of module(s), as for registers SYS1.DEACT
406 + * \return void
407 + */
408 +void sys1_hw_deactivate(u32 mask)
409 +{
410 + sys1_w32(mask, clkclr);
411 + sys1_w32(mask, deact);
412 +
413 + while ( (sys1_r32(acts) & mask) != 0) {
414 + /*NOP;*/
415 + };
416 +}
417 +EXPORT_SYMBOL(sys1_hw_deactivate);
418 +
419 +/**
420 + * Clock enable for the selected module(s)
421 + * Enables the clock of the module.
422 + *
423 + * \param[in] mask bitmask of module(s), as for registers SYS1.CLKEN
424 + * \return void
425 + */
426 +void sys1_hw_clk_enable(u32 mask)
427 +{
428 + sys1_w32(mask, clken);
429 +
430 + while ( (sys1_r32(clks) & mask) != mask) {
431 + /*NOP;*/
432 + };
433 +}
434 +EXPORT_SYMBOL(sys1_hw_clk_enable);
435 +
436 +/**
437 + * Clock disable for the selected module(s)
438 + * disables the clock of the module.
439 + *
440 + * \param[in] mask bitmask of module(s), as for registers SYS1.CLKCLR
441 + * \return void
442 + */
443 +void sys1_hw_clk_disable(u32 mask)
444 +{
445 + sys1_w32(mask, clkclr);
446 +
447 + while ( (sys1_r32(clks) & mask) != 0) {
448 + /*NOP;*/
449 + };
450 +}
451 +EXPORT_SYMBOL(sys1_hw_clk_disable);
452 +
453 +/**
454 + * Reboots the selected module(s)
455 + * Triggers the reboot of the module.
456 + *
457 + * \param[in] mask bitmask of module(s), as for registers SYS1.RBT
458 + * \return void
459 + */
460 +void sys1_hw_activate_or_reboot(u32 mask)
461 +{
462 + u32 acts = sys1_r32(acts);
463 + /* is not already active? */
464 + if ((~acts & mask) != 0)
465 + sys1_hw_activate(~acts & mask);
466 + sys1_w32(acts & mask, rbt);
467 + while ( (sys1_r32(acts) & mask) != mask) {
468 + /*NOP;*/
469 + };
470 +}
471 +EXPORT_SYMBOL(sys1_hw_activate_or_reboot);
472 +
473 +/**
474 + * Activate the selected module(s)
475 + * Enables the clock of the module and activates the module itself.
476 + *
477 + * \param[in] mask bitmask of module(s), as for registers SYS_ETH.ACT
478 + * \return void
479 + */
480 +void sys_eth_hw_activate(u32 mask)
481 +{
482 + sys_eth_w32(mask, clken);
483 + sys_eth_w32(mask, act);
484 +
485 + while ( (sys_eth_r32(acts) & mask) != mask) {
486 + /*NOP;*/
487 + };
488 +}
489 +EXPORT_SYMBOL(sys_eth_hw_activate);
490 +
491 +/**
492 + * Deactivate the selected module(s)
493 + * Disables the clock of the module and deactivates the module itself.
494 + *
495 + * \param[in] mask bitmask of module(s), as for registers SYS_ETH.DEACT
496 + * \return void
497 + */
498 +void sys_eth_hw_deactivate(u32 mask)
499 +{
500 + sys_eth_w32(mask, clkclr);
501 + sys_eth_w32(mask, deact);
502 +
503 + while ( (sys_eth_r32(acts) & mask) != 0) {
504 + /*NOP;*/
505 + };
506 +}
507 +EXPORT_SYMBOL(sys_eth_hw_deactivate);
508 +
509 +/**
510 + * Clock enable for the selected module(s)
511 + * Enables the clock of the module.
512 + *
513 + * \param[in] mask bitmask of module(s), as for registers SYS_ETH.CLKEN
514 + * \return void
515 + */
516 +void sys_eth_hw_clk_enable(u32 mask)
517 +{
518 + sys_eth_w32(mask, clken);
519 +
520 + while ( (sys_eth_r32(clks) & mask) != mask) {
521 + /*NOP;*/
522 + };
523 +}
524 +EXPORT_SYMBOL(sys_eth_hw_clk_enable);
525 +
526 +/**
527 + * Clock disable for the selected module(s)
528 + * disables the clock of the module.
529 + *
530 + * \param[in] mask bitmask of module(s), as for registers SYS_ETH.CLKCLR
531 + * \return void
532 + */
533 +void sys_eth_hw_clk_disable(u32 mask)
534 +{
535 + sys_eth_w32(mask, clkclr);
536 +
537 + while ( (sys_eth_r32(clks) & mask) != 0) {
538 + /*NOP;*/
539 + };
540 +}
541 +EXPORT_SYMBOL(sys_eth_hw_clk_disable);
542 +
543 +/**
544 + * Reboots the selected module(s)
545 + * Triggers the reboot of the module.
546 + *
547 + * \param[in] mask bitmask of module(s), as for registers SYS_ETH.RBT
548 + * \return void
549 + */
550 +void sys_eth_hw_activate_or_reboot(u32 mask)
551 +{
552 + u32 acts = sys_eth_r32(acts);
553 + /* is not already active? */
554 + if ((~acts & mask) != 0)
555 + sys_eth_hw_activate(~acts & mask);
556 + sys_eth_w32(acts & mask, rbt);
557 + while ( (sys_eth_r32(acts) & mask) != mask) {
558 + /*NOP;*/
559 + };
560 +}
561 +EXPORT_SYMBOL(sys_eth_hw_activate_or_reboot);
562 +
563 +static int gpe_clk_is_enabled(void)
564 +{
565 + u32 rd_data;
566 +
567 + rd_data = sys1_r32(infrac);
568 + if (rd_data & (1<<(INFRAC_GP_OFFSET+1)))
569 + return 1;
570 + return 0;
571 +}
572 +
573 +static void enable_gpe_clk(void)
574 +{
575 + u32 aeFreq;
576 + u32 rd_data;
577 + u32 rd_data_to_keep;
578 + int i;
579 +
580 + if (gpe_clk_is_enabled())
581 + /* clock already active, no need to change here */
582 + return;
583 +
584 + if (status_r32(config) == 0)
585 + aeFreq = 1; /* use 625MHz on unfused chip */
586 + else
587 + aeFreq = (status_r32(config) & STATUS_CONFIG_GPEFREQ_MASK) >> STATUS_CONFIG_GPEFREQ_OFFSET;
588 + rd_data = sys1_r32(infrac);
589 + /* clear gpe-fsel and enable bits */
590 + rd_data_to_keep = rd_data & ~(7<<(INFRAC_GP_OFFSET+1));
591 +
592 + /* set new fsel */
593 + sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)), infrac);
594 +
595 + for (i = 0; i <10; i++) /* wait 10 cycles */
596 + {}
597 +
598 + /* keep new fsel and enable */
599 + sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)) |
600 + (1<<(INFRAC_GP_OFFSET+1)), infrac);
601 + for (i = 0; i <100; i++) /* wait 100 cycles */
602 + {}
603 +}
604 +
605 +/**
606 + * Activate the selected module(s)
607 + * Enables the clock of the module and activates the module itself.
608 + *
609 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.ACT
610 + * \return void
611 + */
612 +void sys_gpe_hw_activate(u32 mask)
613 +{
614 + enable_gpe_clk();
615 + sys_gpe_w32(mask, clken);
616 + sys_gpe_w32(mask, act);
617 +
618 + while ( (sys_gpe_r32(acts) & mask) != mask) {
619 + /*NOP;*/
620 + };
621 +}
622 +EXPORT_SYMBOL(sys_gpe_hw_activate);
623 +
624 +/**
625 + * Deactivate the selected module(s)
626 + * Disables the clock of the module and deactivates the module itself.
627 + *
628 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.DEACT
629 + * \return void
630 + */
631 +void sys_gpe_hw_deactivate(u32 mask)
632 +{
633 + enable_gpe_clk();
634 + sys_gpe_w32(mask, clkclr);
635 + sys_gpe_w32(mask, deact);
636 +
637 + while ( (sys_gpe_r32(acts) & mask) != 0) {
638 + /*NOP;*/
639 + };
640 +}
641 +EXPORT_SYMBOL(sys_gpe_hw_deactivate);
642 +
643 +/**
644 + * Clock enable for the selected module(s)
645 + * Enables the clock of the module.
646 + *
647 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.CLKEN
648 + * \return void
649 + */
650 +void sys_gpe_hw_clk_enable(u32 mask)
651 +{
652 + enable_gpe_clk();
653 + sys_gpe_w32(mask, clken);
654 +
655 + while ( (sys_gpe_r32(clks) & mask) != mask) {
656 + /*NOP;*/
657 + };
658 +}
659 +EXPORT_SYMBOL(sys_gpe_hw_clk_enable);
660 +
661 +/**
662 + * Clock disable for the selected module(s)
663 + * disables the clock of the module.
664 + *
665 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.CLKCLR
666 + * \return void
667 + */
668 +void sys_gpe_hw_clk_disable(u32 mask)
669 +{
670 + enable_gpe_clk();
671 + sys_gpe_w32(mask, clkclr);
672 +
673 + while ( (sys_gpe_r32(clks) & mask) != 0) {
674 + /*NOP;*/
675 + };
676 +}
677 +EXPORT_SYMBOL(sys_gpe_hw_clk_disable);
678 +
679 +/**
680 + * Reboots the selected module(s)
681 + * Triggers the reboot of the module.
682 + *
683 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.RBT
684 + * \return void
685 + */
686 +void sys_gpe_hw_activate_or_reboot(u32 mask)
687 +{
688 + u32 acts;
689 + enable_gpe_clk();
690 + acts = sys_gpe_r32(acts);
691 + /* is not already active? */
692 + if ((~acts & mask) != 0)
693 + sys_gpe_hw_activate(~acts & mask);
694 + sys_gpe_w32(acts & mask, rbt);
695 + while ( (sys_gpe_r32(acts) & mask) != mask) {
696 + /*NOP;*/
697 + };
698 +}
699 +EXPORT_SYMBOL(sys_gpe_hw_activate_or_reboot);
700 +
701 +/**
702 + * Retrieve activation status of the selected hardware module(s)
703 + *
704 + * \param[in] mask bitmask of module(s), as for registers SYS_GPE.RBT
705 + * \return int 1 - if hardware module(s) is activated (including clock)
706 + */
707 + int sys_gpe_hw_is_activated(u32 mask)
708 +{
709 + if (gpe_clk_is_enabled() == 0)
710 + return 0;
711 +
712 + if ((sys_gpe_r32(clks) & mask) != mask)
713 + return 0;
714 +
715 + return ((sys_gpe_r32(acts) & mask) == mask);
716 +}
717 +EXPORT_SYMBOL(sys_gpe_hw_is_activated);
718 --- /dev/null
719 +++ b/arch/mips/lantiq/falcon/gpio.c
720 @@ -0,0 +1,463 @@
721 +/*
722 + * This program is free software; you can redistribute it and/or modify
723 + * it under the terms of the GNU General Public License as published by
724 + * the Free Software Foundation; either version 2 of the License, or
725 + * (at your option) any later version.
726 + *
727 + * This program is distributed in the hope that it will be useful,
728 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
729 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
730 + * GNU General Public License for more details.
731 + *
732 + * You should have received a copy of the GNU General Public License
733 + * along with this program; if not, write to the Free Software
734 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
735 + *
736 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
737 + */
738 +
739 +/**
740 + TODO:
741 + - add locking?
742 + - provide mask of available pins per platform_data
743 +*/
744 +
745 +#include <linux/module.h>
746 +#include <linux/types.h>
747 +#include <linux/errno.h>
748 +#include <linux/init.h>
749 +#include <linux/seq_file.h>
750 +#include <linux/platform_device.h>
751 +#include <linux/uaccess.h>
752 +#include <linux/gpio.h>
753 +#include <linux/irq.h>
754 +#include <linux/interrupt.h>
755 +#include <linux/slab.h>
756 +
757 +#include <falcon.h>
758 +#include <falcon/falcon_irq.h>
759 +
760 +#include <linux/version.h>
761 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
762 +#define for_each_set_bit for_each_bit
763 +#endif
764 +
765 +#define gpio_r32(reg) __raw_readl(reg)
766 +#define gpio_w32(val, reg) __raw_writel(val, reg)
767 +#define gpio_w32_mask(clear, set, reg) gpio_w32((gpio_r32(reg) & ~(clear)) | (set), reg)
768 +
769 +
770 +/** register structure for padctrl
771 + (mainly needed for mux control) */
772 +typedef struct gpon_padctrl_s
773 +{
774 + /** Multiplexer Control Register
775 + The value 0 (the reset-value) is always the default function corresponding to the pad's name. The value 1 selects always the GPIO functionality (if available). */
776 + unsigned int muxc[32];
777 + /** Pull Up Enable Register */
778 + unsigned int puen; /* 0x00000080 */
779 + /** Pull Down Enable Register */
780 + unsigned int pden; /* 0x00000084 */
781 + /** Slew Rate Control Register */
782 + unsigned int src; /* 0x00000088 */
783 + /** Drive Current Control Register */
784 + unsigned int dcc; /* 0x0000008C */
785 + /** Reserved */
786 + unsigned int res_0[24]; /* 0x00000090 */
787 + /** Pad Control Availability Register */
788 + unsigned int avail; /* 0x000000F0 */
789 +} gpon_padctrl0_t;
790 +
791 +/** register structure for gpio port */
792 +typedef struct gpon_gpio_s
793 +{
794 + /** Data Output Register
795 + Via this register the output values of the different bits can be set if they are switched as outputs. */
796 + unsigned int out; /* 0x00000000 */
797 + /** Data Input Register
798 + Via this register the input values of the different bits can be observed. */
799 + unsigned int in; /* 0x00000004 */
800 + /** Direction Register
801 + Via this register the input direction of the different bits can be determined. */
802 + unsigned int dir; /* 0x00000008 */
803 + /** Reserved */
804 + unsigned int res_0[3]; /* 0x0000000C */
805 + /** External Interrupt Control Register 0 */
806 + unsigned int exintcr0; /* 0x00000018 */
807 + /** External Interrupt Control Register 1 */
808 + unsigned int exintcr1; /* 0x0000001C */
809 + /** IRN Capture Register
810 + This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
811 + unsigned int irncr; /* 0x00000020 */
812 + /** IRN Interrupt Control Register
813 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
814 + unsigned int irnicr; /* 0x00000024 */
815 + /** IRN Interrupt Enable Register
816 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
817 + unsigned int irnen; /* 0x00000028 */
818 + /** IRN Interrupt Configuration Register
819 + Configures the interrupts bitwise to be edge-senstivie or level-sensitive. */
820 + unsigned int irncfg; /* 0x0000002C */
821 + /** IRN Interrupt Enable Set Register
822 + The corresponding bit in the IRNEN register can be set with an atomic access. */
823 + unsigned int irnenset; /* 0x00000030 */
824 + /** IRN Interrupt Enable Clear Register
825 + The corresponding bit in the IRNEN register can be cleared with an atomic access. */
826 + unsigned int irnenclr; /* 0x00000034 */
827 + /** Reserved */
828 + unsigned int res_1[2]; /* 0x00000038 */
829 + /** Output Set Register
830 + This register can be used to set certain bits within the OUT register without touching the other bits. */
831 + unsigned int outset; /* 0x00000040 */
832 + /** Output Clear Register
833 + This register can be used to clear certain bits within the OUT register without touching the other bits. */
834 + unsigned int outclr; /* 0x00000044 */
835 + /** Direction Set Register
836 + This register can be used to set certain bits within the DIR register without touching the other bits. */
837 + unsigned int dirset; /* 0x00000048 */
838 + /** Direction Clear Register
839 + This register can be used to clear certain bits within the DIR register without touching the other bits. */
840 + unsigned int dirclr; /* 0x0000004C */
841 +} gpon_gpio_t;
842 +
843 +struct falcon_gpio_port {
844 + struct gpio_chip gpio_chip;
845 + gpon_padctrl0_t __iomem *pad;
846 + gpon_gpio_t __iomem *port;
847 + struct resource *pad_req; /* resources requested */
848 + struct resource *port_req;
849 + unsigned int irq_base;
850 + unsigned int chained_irq;
851 +};
852 +
853 +static int gpio_exported = 0;
854 +static int __init gpio_export_setup(char *str)
855 +{
856 + get_option(&str, &gpio_exported);
857 + return 1;
858 +}
859 +__setup("gpio_exported=", gpio_export_setup);
860 +
861 +static inline struct falcon_gpio_port *to_falcon_gpio_port(struct gpio_chip *chip)
862 +{
863 + return container_of(chip, struct falcon_gpio_port, gpio_chip);
864 +}
865 +
866 +static int falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
867 +{
868 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
869 + gpio_w32(1<<offset, &gpio_port->port->dirclr);
870 + return 0;
871 +}
872 +
873 +static int falcon_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
874 +{
875 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
876 + gpio_w32(1<<offset, &gpio_port->port->dirset);
877 + return 0;
878 +}
879 +
880 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
881 +{
882 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
883 + if (value)
884 + gpio_w32(1<<offset, &gpio_port->port->outset);
885 + else
886 + gpio_w32(1<<offset, &gpio_port->port->outclr);
887 +}
888 +
889 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
890 +{
891 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
892 + if ((gpio_r32(&gpio_port->port->dir) >> offset) & 1)
893 + return (gpio_r32(&gpio_port->port->out) >> offset) & 1;
894 + else
895 + return (gpio_r32(&gpio_port->port->in) >> offset) & 1;
896 +}
897 +
898 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
899 +{
900 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
901 + if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
902 + if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
903 + return -EBUSY;
904 + /* switch on gpio function */
905 + gpio_w32(1, &gpio_port->pad->muxc[offset]);
906 + return 0;
907 + }
908 +
909 + return -ENODEV;
910 +}
911 +
912 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
913 +{
914 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
915 + if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
916 + if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
917 + return;
918 + /* switch off gpio function */
919 + gpio_w32(0, &gpio_port->pad->muxc[offset]);
920 + }
921 +}
922 +
923 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
924 +{
925 + struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
926 + /* no checks: this functions is only registered with valid irq_base */
927 + return gpio_port->irq_base + offset;
928 +}
929 +
930 +static void falcon_gpio_disable_irq(struct irq_data *d)
931 +{
932 + struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
933 + unsigned int offset = d->irq-gpio_port->irq_base;
934 + gpio_w32(1<<offset, &gpio_port->port->irnenclr);
935 +}
936 +
937 +static void falcon_gpio_enable_irq(struct irq_data *d)
938 +{
939 + struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
940 + unsigned int offset = d->irq-gpio_port->irq_base;
941 +
942 + if (gpio_r32(&gpio_port->pad->muxc[offset]) < 1) {
943 + /* switch on gpio function */
944 + gpio_w32(1, &gpio_port->pad->muxc[offset]);
945 + }
946 +
947 + gpio_w32(1<<offset, &gpio_port->port->irnenset);
948 +}
949 +
950 +static void falcon_gpio_ack_irq(struct irq_data *d)
951 +{
952 + struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
953 + unsigned int offset = d->irq-gpio_port->irq_base;
954 + gpio_w32(1<<offset, &gpio_port->port->irncr);
955 +}
956 +
957 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
958 +{
959 + struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
960 + unsigned int offset = d->irq-gpio_port->irq_base;
961 + gpio_w32(1<<offset, &gpio_port->port->irnenclr);
962 + gpio_w32(1<<offset, &gpio_port->port->irncr);
963 +}
964 +
965 +static struct irq_chip falcon_gpio_irq_chip;
966 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
967 +{
968 + struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
969 + unsigned int offset = d->irq-gpio_port->irq_base;
970 + unsigned int mask = 1 << offset;
971 +
972 + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
973 + return 0;
974 +
975 + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
976 + /* level triggered */
977 + gpio_w32_mask(0, mask, &gpio_port->port->irncfg);
978 + irq_set_chip_and_handler_name(d->irq,
979 + &falcon_gpio_irq_chip, handle_level_irq, "mux");
980 + } else {
981 + /* edge triggered */
982 + gpio_w32_mask(mask, 0, &gpio_port->port->irncfg);
983 + irq_set_chip_and_handler_name(d->irq,
984 + &falcon_gpio_irq_chip, handle_simple_irq, "mux");
985 + }
986 +
987 + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
988 + gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
989 + gpio_w32_mask(0, mask, &gpio_port->port->exintcr1);
990 + } else {
991 + if ((type & (IRQ_TYPE_EDGE_RISING |IRQ_TYPE_LEVEL_HIGH)) != 0) {
992 + /* positive logic: rising edge, high level */
993 + gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
994 + } else {
995 + /* negative logic: falling edge, low level */
996 + gpio_w32_mask(0, mask, &gpio_port->port->exintcr0);
997 + }
998 + gpio_w32_mask(mask, 0, &gpio_port->port->exintcr1);
999 + }
1000 +
1001 + return gpio_direction_input(gpio_port->gpio_chip.base + offset);
1002 +}
1003 +
1004 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1005 +{
1006 + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
1007 + unsigned long irncr;
1008 + int offset;
1009 +
1010 + irncr = gpio_r32(&gpio_port->port->irncr);
1011 + /* acknowledge interrupt */
1012 + gpio_w32(irncr, &gpio_port->port->irncr);
1013 +
1014 + desc->irq_data.chip->irq_ack(&desc->irq_data);
1015 +
1016 + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
1017 + generic_handle_irq(gpio_port->irq_base + offset);
1018 +}
1019 +
1020 +static struct irq_chip falcon_gpio_irq_chip = {
1021 + .name = "gpio_irq_mux",
1022 + .irq_mask = falcon_gpio_disable_irq,
1023 + .irq_unmask = falcon_gpio_enable_irq,
1024 + .irq_ack = falcon_gpio_ack_irq,
1025 + .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
1026 + .irq_set_type = falcon_gpio_irq_type,
1027 +};
1028 +
1029 +static struct irqaction gpio_cascade = {
1030 + .handler = no_action,
1031 + .flags = IRQF_DISABLED,
1032 + .name = "gpio_cascade",
1033 +};
1034 +
1035 +static int falcon_gpio_probe(struct platform_device *pdev)
1036 +{
1037 + struct falcon_gpio_port *gpio_port;
1038 + int ret, i;
1039 + struct resource *gpiores, *padres;
1040 + int irq;
1041 +
1042 + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1043 + padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1044 + irq = platform_get_irq(pdev, 0);
1045 + if (!gpiores || !padres)
1046 + return -ENODEV;
1047 +
1048 + gpio_port = kzalloc(sizeof(*gpio_port), GFP_KERNEL);
1049 + if (gpio_port == NULL)
1050 + return -ENOMEM;
1051 +
1052 + gpio_port->gpio_chip.label = "falcon-gpio";
1053 + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
1054 + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
1055 + gpio_port->gpio_chip.get = falcon_gpio_get;
1056 + gpio_port->gpio_chip.set = falcon_gpio_set;
1057 + gpio_port->gpio_chip.request = falcon_gpio_request;
1058 + gpio_port->gpio_chip.free = falcon_gpio_free;
1059 + gpio_port->gpio_chip.base = 100 * pdev->id;
1060 + gpio_port->gpio_chip.ngpio = 32;
1061 + gpio_port->gpio_chip.dev = &pdev->dev;
1062 + gpio_port->gpio_chip.exported = gpio_exported;
1063 +
1064 + gpio_port->port_req = request_mem_region(gpiores->start,
1065 + resource_size(gpiores), pdev->name);
1066 + gpio_port->pad_req = request_mem_region(padres->start,
1067 + resource_size(padres), pdev->name);
1068 + if (!gpio_port->port_req || !gpio_port->pad_req) {
1069 + dev_err(&pdev->dev, "cannot claim register area\n");
1070 + ret = -EIO;
1071 + goto err;
1072 + }
1073 +
1074 + gpio_port->port = ioremap_nocache(gpiores->start,
1075 + resource_size(gpiores));
1076 + gpio_port->pad = ioremap_nocache(padres->start,
1077 + resource_size(padres));
1078 + if (!gpio_port->port || !gpio_port->pad) {
1079 + dev_err(&pdev->dev, "Could not map io ranges\n");
1080 + ret = -ENOMEM;
1081 + goto err;
1082 + }
1083 +
1084 + if (irq>0) {
1085 + /*
1086 + * irq_chip support
1087 + */
1088 + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
1089 + gpio_port->irq_base = INT_NUM_EXTRA_START + 32 * pdev->id;
1090 +
1091 + for (i = 0; i < 32; i++) {
1092 + irq_set_chip_and_handler_name(gpio_port->irq_base + i,
1093 + &falcon_gpio_irq_chip, handle_simple_irq, "mux");
1094 + irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
1095 + /* FIXME: set default cfg to level triggered */
1096 + //gpio_w32_mask(0, 1<<i, &gpio_port->port->irncfg);
1097 + /* set to negative logic (falling edge, low level) */
1098 + gpio_w32_mask(0, 1<<i, &gpio_port->port->exintcr0);
1099 + }
1100 +
1101 + gpio_port->chained_irq = irq;
1102 + setup_irq(irq, &gpio_cascade);
1103 + irq_set_handler_data(irq, gpio_port);
1104 + irq_set_chained_handler(irq, falcon_gpio_irq_handler);
1105 + }
1106 +
1107 + ret = gpiochip_add(&gpio_port->gpio_chip);
1108 + if (ret < 0) {
1109 + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
1110 + pdev->id, ret);
1111 + goto err;
1112 + }
1113 + platform_set_drvdata(pdev, gpio_port);
1114 + return ret;
1115 +
1116 +err:
1117 + dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
1118 + if (gpio_port->port_req)
1119 + release_resource(gpio_port->port_req);
1120 + if (gpio_port->pad_req)
1121 + release_resource(gpio_port->pad_req);
1122 +
1123 + if (gpio_port->port)
1124 + iounmap(gpio_port->port);
1125 + if (gpio_port->pad)
1126 + iounmap(gpio_port->pad);
1127 + kfree(gpio_port);
1128 + return ret;
1129 +}
1130 +
1131 +static int falcon_gpio_remove(struct platform_device *pdev)
1132 +{
1133 + struct falcon_gpio_port *gpio_port = platform_get_drvdata(pdev);
1134 + int ret;
1135 +
1136 + ret = gpiochip_remove(&gpio_port->gpio_chip);
1137 + if (gpio_port->port_req)
1138 + release_resource(gpio_port->port_req);
1139 + if (gpio_port->pad_req)
1140 + release_resource(gpio_port->pad_req);
1141 + if (gpio_port->port)
1142 + iounmap(gpio_port->port);
1143 + if (gpio_port->pad)
1144 + iounmap(gpio_port->pad);
1145 + if (ret == 0)
1146 + kfree(gpio_port);
1147 +
1148 + return ret;
1149 +}
1150 +
1151 +static struct platform_driver falcon_gpio_driver = {
1152 + .probe = falcon_gpio_probe,
1153 + .remove = __devexit_p(falcon_gpio_remove),
1154 + .driver = {
1155 + .name = "falcon_gpio",
1156 + .owner = THIS_MODULE,
1157 + },
1158 +};
1159 +
1160 +int __init falcon_gpio_init(void)
1161 +{
1162 + int ret;
1163 +
1164 + printk(KERN_INFO "FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
1165 + ret = platform_driver_register(&falcon_gpio_driver);
1166 + if (ret)
1167 + pr_err( "falcon_gpio: Error registering platform driver!");
1168 + return ret;
1169 +}
1170 +
1171 +void __exit falcon_gpio_exit(void)
1172 +{
1173 + platform_driver_unregister(&falcon_gpio_driver);
1174 +}
1175 +
1176 +int gpio_to_irq(unsigned int gpio)
1177 +{
1178 + return __gpio_to_irq(gpio);
1179 +}
1180 +EXPORT_SYMBOL(gpio_to_irq);
1181 +
1182 +module_init(falcon_gpio_init);
1183 +module_exit(falcon_gpio_exit);
1184 --- /dev/null
1185 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon.h
1186 @@ -0,0 +1,16 @@
1187 +/*
1188 + * This program is free software; you can redistribute it and/or modify
1189 + * it under the terms of the GNU General Public License as published by
1190 + * the Free Software Foundation; either version 2 of the License, or
1191 + * (at your option) any later version.
1192 + *
1193 + * Copyright (C) 2005 infineon
1194 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1195 + */
1196 +
1197 +#ifdef CONFIG_SOC_FALCON
1198 +
1199 +#include <lantiq_soc.h>
1200 +#include <falcon/gpon_reg_base.h>
1201 +
1202 +#endif
1203 --- /dev/null
1204 +++ b/arch/mips/lantiq/falcon/reset.c
1205 @@ -0,0 +1,80 @@
1206 +/*
1207 + * This program is free software; you can redistribute it and/or modify
1208 + * it under the terms of the GNU General Public License as published by
1209 + * the Free Software Foundation; either version 2 of the License, or
1210 + * (at your option) any later version.
1211 + *
1212 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1213 + */
1214 +
1215 +#include <linux/init.h>
1216 +#include <linux/io.h>
1217 +#include <linux/pm.h>
1218 +#include <asm/reboot.h>
1219 +#include <linux/module.h>
1220 +
1221 +#include <falcon.h>
1222 +#include <falcon/gpon_reg_base.h>
1223 +#include <falcon/status_reg.h>
1224 +#include <falcon/sys1_reg.h>
1225 +
1226 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
1227 +
1228 +#define WDT_PW1 0x00BE0000
1229 +#define WDT_PW2 0x00DC0000
1230 +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
1231 +
1232 +/* This function is used by the watchdog driver */
1233 +int ltq_reset_cause(void)
1234 +{
1235 + return 0;
1236 +}
1237 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
1238 +
1239 +static void
1240 +ltq_machine_restart(char *command)
1241 +{
1242 + printk(KERN_NOTICE "System restart\n");
1243 + local_irq_disable();
1244 + ltq_w32(0, (void*)0xBF200000); /* reset Bootreg RVEC */
1245 +#if 0
1246 + ltq_w32(RBT_CPU_TRIG, &pSYS1->rbt);
1247 +#else
1248 + /* use workaround via watchdog timer */
1249 + ltq_w32(WDT_PW1, (void*)WDT_REG_BASE);
1250 + ltq_w32(WDT_PW2 |
1251 + (0x3 << 26) | /* PWL */
1252 + (0x2 << 24) | /* CLKDIV */
1253 + (0x1 << 31) | /* enable */
1254 + (1), /* reload */
1255 + (void*)WDT_REG_BASE);
1256 +#endif
1257 + for(;;);
1258 +}
1259 +
1260 +static void
1261 +ltq_machine_halt(void)
1262 +{
1263 + printk(KERN_NOTICE "System halted.\n");
1264 + local_irq_disable();
1265 + for(;;);
1266 +}
1267 +
1268 +static void
1269 +ltq_machine_power_off(void)
1270 +{
1271 + printk(KERN_NOTICE "Please turn off the power now.\n");
1272 + local_irq_disable();
1273 + for(;;);
1274 +}
1275 +
1276 +static int __init
1277 +mips_reboot_setup(void)
1278 +{
1279 + _machine_restart = ltq_machine_restart;
1280 + _machine_halt = ltq_machine_halt;
1281 + pm_power_off = ltq_machine_power_off;
1282 + return 0;
1283 +}
1284 +
1285 +arch_initcall(mips_reboot_setup);
1286 --- /dev/null
1287 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
1288 @@ -0,0 +1,247 @@
1289 +#include <linux/init.h>
1290 +#include <linux/platform_device.h>
1291 +#include <linux/leds.h>
1292 +#include <linux/gpio.h>
1293 +#include <linux/gpio_buttons.h>
1294 +#include <linux/etherdevice.h>
1295 +#include <linux/mtd/mtd.h>
1296 +#include <linux/mtd/partitions.h>
1297 +#include <linux/mtd/physmap.h>
1298 +#include <linux/input.h>
1299 +#include <linux/interrupt.h>
1300 +#include <linux/dm9000.h>
1301 +#include <linux/i2c.h>
1302 +#include <linux/i2c-gpio.h>
1303 +#include <linux/spi/spi.h>
1304 +#include <linux/spi/spi_gpio.h>
1305 +#include <linux/spi/eeprom.h>
1306 +
1307 +#include "../machtypes.h"
1308 +
1309 +#include "devices.h"
1310 +#include "dev-leds-gpio.h"
1311 +
1312 +#define EASY98000_GPIO_LED_0 9
1313 +#define EASY98000_GPIO_LED_1 10
1314 +#define EASY98000_GPIO_LED_2 11
1315 +#define EASY98000_GPIO_LED_3 12
1316 +#define EASY98000_GPIO_LED_4 13
1317 +#define EASY98000_GPIO_LED_5 14
1318 +
1319 +extern unsigned char ltq_ethaddr[6];
1320 +
1321 +#ifdef CONFIG_MTD_PARTITIONS
1322 +static struct mtd_partition easy98000_nor_partitions[] =
1323 +{
1324 + {
1325 + .name = "uboot",
1326 + .offset = 0x0,
1327 + .size = 0x40000,
1328 + },
1329 + {
1330 + .name = "uboot_env",
1331 + .offset = 0x40000,
1332 + .size = 0x40000, /* 2 sectors for redundant env. */
1333 + },
1334 + {
1335 + .name = "linux",
1336 + .offset = 0x80000,
1337 + .size = 0xF80000, /* map only 16 MiB */
1338 + },
1339 +};
1340 +#endif
1341 +
1342 +static struct physmap_flash_data easy98000_nor_flash_data = {
1343 +#ifdef CONFIG_MTD_PARTITIONS
1344 + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions),
1345 + .parts = easy98000_nor_partitions,
1346 +#endif
1347 +};
1348 +
1349 +#ifdef CONFIG_MTD_PARTITIONS
1350 +static struct flash_platform_data easy98000_spi_flash_platform_data = {
1351 + .name = "sflash",
1352 + .parts = easy98000_nor_partitions,
1353 + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
1354 +};
1355 +#endif
1356 +
1357 +static struct spi_board_info easy98000_spi_flash_data __initdata = {
1358 + .modalias = "m25p80",
1359 + .bus_num = 0,
1360 + .chip_select = 0,
1361 + .max_speed_hz = 10 * 1000 * 1000,
1362 + .mode = SPI_MODE_3,
1363 +#ifdef CONFIG_MTD_PARTITIONS
1364 + .platform_data = &easy98000_spi_flash_platform_data
1365 +#endif
1366 +};
1367 +
1368 +static struct gpio_led easy98000_leds_gpio[] __initdata = {
1369 + {
1370 + .name = "easy98000:green:0",
1371 + .gpio = EASY98000_GPIO_LED_0,
1372 + .active_low = 0,
1373 + }, {
1374 + .name = "easy98000:green:1",
1375 + .gpio = EASY98000_GPIO_LED_1,
1376 + .active_low = 0,
1377 + }, {
1378 + .name = "easy98000:green:2",
1379 + .gpio = EASY98000_GPIO_LED_2,
1380 + .active_low = 0,
1381 + }, {
1382 + .name = "easy98000:green:3",
1383 + .gpio = EASY98000_GPIO_LED_3,
1384 + .active_low = 0,
1385 + }, {
1386 + .name = "easy98000:green:4",
1387 + .gpio = EASY98000_GPIO_LED_4,
1388 + .active_low = 0,
1389 + }, {
1390 + .name = "easy98000:green:5",
1391 + .gpio = EASY98000_GPIO_LED_5,
1392 + .active_low = 0,
1393 + }
1394 +};
1395 +
1396 +#define CONFIG_DM9000_BASE 0x14000000
1397 +#define DM9000_IO (CONFIG_DM9000_BASE + 3)
1398 +#define DM9000_DATA (CONFIG_DM9000_BASE + 1)
1399 +
1400 +static struct dm9000_plat_data dm9000_plat_data = {
1401 + .flags = DM9000_PLATF_8BITONLY,
1402 + //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */
1403 +};
1404 +
1405 +static struct resource dm9000_resources[] = {
1406 + MEM_RES("dm9000_io", DM9000_IO, DM9000_IO),
1407 + MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA),
1408 + [2] = {
1409 + /* with irq (210 -> gpio 110) the driver is very unreliable */
1410 + .start = -1, /* use polling */
1411 + .end = -1,
1412 + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
1413 + },
1414 +};
1415 +
1416 +static struct platform_device dm9000_platform = {
1417 + .name = "dm9000",
1418 + .id = 0,
1419 + .num_resources = ARRAY_SIZE(dm9000_resources),
1420 + .resource = dm9000_resources,
1421 + .dev = {
1422 + .platform_data = (void *) &dm9000_plat_data,
1423 + }
1424 +};
1425 +
1426 +static void __init register_davicom(void)
1427 +{
1428 + if (!is_valid_ether_addr(ltq_ethaddr))
1429 + random_ether_addr(dm9000_plat_data.dev_addr);
1430 + else {
1431 + memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6);
1432 + /* change to "Locally Administered Address" */
1433 + dm9000_plat_data.dev_addr[0] |= 0x2;
1434 + }
1435 + platform_device_register(&dm9000_platform);
1436 +}
1437 +
1438 +static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = {
1439 + .sda_pin = 107,
1440 + .scl_pin = 108,
1441 +};
1442 +
1443 +static struct platform_device easy98000_i2c_gpio_device = {
1444 + .name = "i2c-gpio",
1445 + .id = 0,
1446 + .dev = {
1447 + .platform_data = &easy98000_i2c_gpio_data,
1448 + }
1449 +};
1450 +
1451 +void __init register_easy98000_cpld_led(void)
1452 +{
1453 + platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0);
1454 +}
1455 +
1456 +/* setup gpio based spi bus/device for access to the eeprom on the board */
1457 +#define SPI_GPIO_MRST 102
1458 +#define SPI_GPIO_MTSR 103
1459 +#define SPI_GPIO_CLK 104
1460 +#define SPI_GPIO_CS0 105
1461 +#define SPI_GPIO_CS1 106
1462 +#define SPI_GPIO_BUS_NUM 1
1463 +
1464 +static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
1465 + .sck = SPI_GPIO_CLK,
1466 + .mosi = SPI_GPIO_MTSR,
1467 + .miso = SPI_GPIO_MRST,
1468 + .num_chipselect = 2,
1469 +};
1470 +
1471 +static struct platform_device easy98000_spi_gpio_device = {
1472 + .name = "spi_gpio",
1473 + .id = SPI_GPIO_BUS_NUM,
1474 + .dev.platform_data = &easy98000_spi_gpio_data,
1475 +};
1476 +
1477 +static struct spi_eeprom at25160n = {
1478 + .byte_len = 16 * 1024 / 8,
1479 + .name = "at25160n",
1480 + .page_size = 32,
1481 + .flags = EE_ADDR2,
1482 +};
1483 +
1484 +static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
1485 + .modalias = "at25",
1486 + .bus_num = SPI_GPIO_BUS_NUM,
1487 + .max_speed_hz = 1000 * 1000,
1488 + .mode = SPI_MODE_3,
1489 + .chip_select = 1,
1490 + .controller_data = (void *) SPI_GPIO_CS1,
1491 + .platform_data = &at25160n,
1492 +};
1493 +
1494 +static void __init easy98000_spi_gpio_init(void)
1495 +{
1496 + spi_register_board_info(&easy98000_spi_gpio_devices, 1);
1497 + platform_device_register(&easy98000_spi_gpio_device);
1498 +}
1499 +
1500 +static void __init easy98000_init_common(void)
1501 +{
1502 + falcon_register_asc(0);
1503 + falcon_register_gpio();
1504 + falcon_register_wdt();
1505 + falcon_register_i2c();
1506 + platform_device_register(&easy98000_i2c_gpio_device);
1507 + register_davicom();
1508 + ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio),
1509 + easy98000_leds_gpio);
1510 + register_easy98000_cpld_led();
1511 + falcon_register_crypto();
1512 + easy98000_spi_gpio_init();
1513 +}
1514 +
1515 +static void __init easy98000_init(void)
1516 +{
1517 + easy98000_init_common();
1518 + falcon_register_nor(&easy98000_nor_flash_data);
1519 +}
1520 +
1521 +static void __init easy98000sf_init(void)
1522 +{
1523 + easy98000_init_common();
1524 + falcon_register_spi_flash(&easy98000_spi_flash_data);
1525 +}
1526 +
1527 +MIPS_MACHINE(LANTIQ_MACH_EASY98000,
1528 + "EASY98000",
1529 + "EASY98000 Eval Board",
1530 + easy98000_init);
1531 +
1532 +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
1533 + "EASY98000SF",
1534 + "EASY98000 Eval Board (Serial Flash)",
1535 + easy98000sf_init);
1536 --- /dev/null
1537 +++ b/arch/mips/lantiq/falcon/softdog_vpe.c
1538 @@ -0,0 +1,109 @@
1539 +/*
1540 +** =============================================================================
1541 +** FILE NAME : softdog_vpe.c
1542 +** MODULES : LXDB
1543 +** DATE : 24-03-2008
1544 +** AUTHOR : LXDB Team
1545 +** DESCRIPTION : This header file contains the code for the watchdog
1546 +** implentation on vpe1 side.
1547 +** REFERENCES :
1548 +** COPYRIGHT : Copyright (c) 2008
1549 +** Am Campeon 1-12, 85579 Neubiberg, Germany
1550 +** Any use of this software is subject to the conclusion of a respective
1551 +** License agreement. Without such a License agreement no rights to the
1552 +** software are granted
1553 +**
1554 +** HISTORY :
1555 +** $Date $Author $Comment
1556 +** 24-03-2008 LXDB Initial version
1557 +** ============================================================================
1558 +*/
1559 +
1560 +#include <linux/module.h>
1561 +#include <linux/moduleparam.h>
1562 +#include <linux/types.h>
1563 +#include <linux/timer.h>
1564 +#include <linux/reboot.h>
1565 +#include <linux/init.h>
1566 +#include <linux/jiffies.h>
1567 +
1568 +#include <falcon/vpe.h>
1569 +
1570 +static unsigned long last_wdog_value;
1571 +static unsigned long vpe1_wdog_cleared;
1572 +
1573 +static unsigned long vpe1_wdog_dead;
1574 +static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */
1575 +static void keep_alive_vpe0(unsigned long);
1576 +VPE_SW_WDOG_RESET reset_local_fn;
1577 +
1578 +
1579 +static struct timer_list watchdog_vpe0_ticktock =
1580 + TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0);
1581 +
1582 +static void watchdog_vpe0_fire (unsigned long flags)
1583 +{
1584 + volatile unsigned long *wdog_ctr_value;
1585 + wdog_ctr_value = (void*)vpe1_wdog_ctr;
1586 + if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */
1587 + vpe1_sw_wdog_stop(flags);
1588 + vpe1_wdog_dead++;
1589 + printk(KERN_DEBUG "VPE1 watchdog reset handler called\n");
1590 + /* Call the reset handler function */
1591 + reset_local_fn(flags);
1592 + } else { /* Everything is OK on vpe1 side. Continue. */
1593 + last_wdog_value = *wdog_ctr_value;
1594 + vpe1_wdog_cleared++;
1595 + keep_alive_vpe0(flags);
1596 + }
1597 +}
1598 +
1599 +int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn)
1600 +{
1601 + reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn;
1602 + return 0;
1603 +}
1604 +
1605 +static void keep_alive_vpe0(unsigned long flags)
1606 +{
1607 + mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout );
1608 +}
1609 +
1610 +unsigned long vpe1_sw_wdog_start(unsigned long flags)
1611 +{
1612 + volatile unsigned long *wdog_ctr_value;
1613 + wdog_ctr_value = (void*)vpe1_wdog_ctr;
1614 + *wdog_ctr_value = 0;
1615 + last_wdog_value = 0;
1616 + keep_alive_vpe0(flags);
1617 + return 0;
1618 +}
1619 +
1620 +unsigned long vpe1_sw_wdog_stop(unsigned long flags)
1621 +{
1622 + del_timer(&watchdog_vpe0_ticktock);
1623 + return 0;
1624 +}
1625 +
1626 +static int __init watchdog_vpe1_init(void)
1627 +{
1628 + /* Nothing to be done here */
1629 + return 0;
1630 +}
1631 +
1632 +static void __exit watchdog_vpe1_exit(void)
1633 +{
1634 + unsigned long flags=0;
1635 + vpe1_sw_wdog_stop(flags);
1636 +}
1637 +
1638 +module_init(watchdog_vpe1_init);
1639 +module_exit(watchdog_vpe1_exit);
1640 +
1641 +EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler);
1642 +EXPORT_SYMBOL(vpe1_sw_wdog_start);
1643 +EXPORT_SYMBOL(vpe1_sw_wdog_stop);
1644 +
1645 +MODULE_AUTHOR("LXDB");
1646 +MODULE_DESCRIPTION("Software Watchdog For VPE1");
1647 +MODULE_LICENSE("GPL");
1648 --- /dev/null
1649 +++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
1650 @@ -0,0 +1,44 @@
1651 +/*
1652 + * This program is free software; you can redistribute it and/or modify
1653 + * it under the terms of the GNU General Public License as published by
1654 + * the Free Software Foundation; either version 2 of the License, or
1655 + * (at your option) any later version.
1656 + *
1657 + * This program is distributed in the hope that it will be useful,
1658 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1659 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1660 + * GNU General Public License for more details.
1661 + *
1662 + * You should have received a copy of the GNU General Public License
1663 + * along with this program; if not, write to the Free Software
1664 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1665 + *
1666 + * Copyright (C) 2005 infineon
1667 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
1668 + *
1669 + */
1670 +#ifndef _IFXMIPS_VPE_H__
1671 +#define _IFXMIPS_VPE_H__
1672 +
1673 +/* For the explanation of the APIs please refer the section "MT APRP Kernel
1674 + * Programming" in AR9 SW Architecture Specification
1675 + */
1676 +int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags);
1677 +int32_t vpe1_sw_stop(uint32_t flags);
1678 +uint32_t vpe1_get_load_addr (uint32_t flags);
1679 +uint32_t vpe1_get_max_mem (uint32_t flags);
1680 +
1681 +int32_t vpe1_set_boot_param(char *field, char *value, char flags);
1682 +int32_t vpe1_get_boot_param(char *field, char **value, char flags);
1683 +
1684 +/* Watchdog APIs */
1685 +extern unsigned long vpe1_wdog_ctr;
1686 +extern unsigned long vpe1_wdog_timeout;
1687 +
1688 +unsigned long vpe1_sw_wdog_start(unsigned long);
1689 +unsigned long vpe1_sw_wdog_stop(unsigned long);
1690 +
1691 +typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
1692 +int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
1693 +
1694 +#endif
1695 --- a/arch/mips/lantiq/Kconfig
1696 +++ b/arch/mips/lantiq/Kconfig
1697 @@ -16,8 +16,12 @@
1698 bool "XWAY"
1699 select SOC_TYPE_XWAY
1700 select HW_HAS_PCI
1701 +
1702 +config SOC_FALCON
1703 + bool "FALCON"
1704 endchoice
1705
1706 source "arch/mips/lantiq/xway/Kconfig"
1707 +source "arch/mips/lantiq/falcon/Kconfig"
1708
1709 endif
1710 --- a/arch/mips/lantiq/Makefile
1711 +++ b/arch/mips/lantiq/Makefile
1712 @@ -9,3 +9,4 @@
1713 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
1714
1715 obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
1716 +obj-$(CONFIG_SOC_FALCON) += falcon/
1717 --- a/arch/mips/lantiq/Platform
1718 +++ b/arch/mips/lantiq/Platform
1719 @@ -6,3 +6,4 @@
1720 cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
1721 load-$(CONFIG_LANTIQ) = 0xffffffff80002000
1722 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
1723 +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
1724 --- a/arch/mips/lantiq/machtypes.h
1725 +++ b/arch/mips/lantiq/machtypes.h
1726 @@ -15,6 +15,11 @@
1727 LTQ_MACH_GENERIC = 0,
1728 LTQ_MACH_EASY50712, /* Danube evaluation board */
1729 LTQ_MACH_EASY50601, /* Amazon SE evaluation board */
1730 +
1731 + /* FALCON */
1732 + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */
1733 + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */
1734 + LANTIQ_MACH_EASY98020, /* Falcon Reference Board */
1735 };
1736
1737 #endif