a0e517a7c94a519369db1127d13287494872cf3d
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-2.6.39 / 420-spi3.patch
1 From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2 Date: Thu, 3 Mar 2011 20:42:26 +0000 (+0100)
3 Subject: MIPS: lantiq: Add device register helper for SPI controller and devices
4 X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=b35b07062b718ece9b9cb7b23b12d83a087eafb0;hp=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90
5
6 MIPS: lantiq: Add device register helper for SPI controller and devices
7
8 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 ---
10
11 --- a/arch/mips/lantiq/xway/devices.c
12 +++ b/arch/mips/lantiq/xway/devices.c
13 @@ -21,6 +21,7 @@
14 #include <linux/io.h>
15 #include <linux/gpio.h>
16 #include <linux/leds.h>
17 +#include <linux/spi/spi.h>
18
19 #include <asm/bootinfo.h>
20 #include <asm/irq.h>
21 @@ -119,3 +120,41 @@
22 platform_device_register(&ltq_etop);
23 }
24 }
25 +
26 +static struct resource ltq_spi_resources[] = {
27 + {
28 + .start = LTQ_SSC_BASE_ADDR,
29 + .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
30 + .flags = IORESOURCE_MEM,
31 + },
32 + IRQ_RES(spi_tx, LTQ_SSC_TIR),
33 + IRQ_RES(spi_rx, LTQ_SSC_RIR),
34 + IRQ_RES(spi_err, LTQ_SSC_EIR),
35 +};
36 +
37 +static struct resource ltq_spi_resources_ar9[] = {
38 + {
39 + .start = LTQ_SSC_BASE_ADDR,
40 + .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
41 + .flags = IORESOURCE_MEM,
42 + },
43 + IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
44 + IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
45 + IRQ_RES(spi_err, LTQ_SSC_EIR),
46 +};
47 +
48 +static struct platform_device ltq_spi = {
49 + .name = "ltq-spi",
50 + .resource = ltq_spi_resources,
51 + .num_resources = ARRAY_SIZE(ltq_spi_resources),
52 +};
53 +
54 +void __init ltq_register_spi(struct ltq_spi_platform_data *pdata,
55 + struct spi_board_info const *info, unsigned n)
56 +{
57 + if(ltq_is_ar9())
58 + ltq_spi.resource = ltq_spi_resources_ar9;
59 + spi_register_board_info(info, n);
60 + ltq_spi.dev.platform_data = pdata;
61 + platform_device_register(&ltq_spi);
62 +}
63 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
64 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
65 @@ -27,6 +27,8 @@
66
67 #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
68 #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
69 +#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14)
70 +#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15)
71 #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
72
73 #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)