lantiq: fix ath9k eeprom loading order bug
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.10 / 0010-MIPS-lantiq-wifi-and-ethernet-eeprom-handling.patch
1 From 8c19ced548538d964dcfb83bdf9ea9e8fbb7bdb1 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 13 Mar 2013 10:02:58 +0100
4 Subject: [PATCH 10/34] MIPS: lantiq: wifi and ethernet eeprom handling
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 +
9 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
10 arch/mips/lantiq/xway/Makefile | 2 +
11 arch/mips/lantiq/xway/ath_eep.c | 237 ++++++++++++++++++++
12 arch/mips/lantiq/xway/pci-ath-fixup.c | 109 +++++++++
13 arch/mips/lantiq/xway/rt_eep.c | 60 +++++
14 6 files changed, 417 insertions(+)
15 create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
16 create mode 100644 arch/mips/lantiq/xway/ath_eep.c
17 create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c
18 create mode 100644 arch/mips/lantiq/xway/rt_eep.c
19
20 Index: linux-3.10.12/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
21 ===================================================================
22 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
23 +++ linux-3.10.12/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 2013-09-17 22:32:50.385021711 +0200
24 @@ -0,0 +1,6 @@
25 +#ifndef _PCI_ATH_FIXUP
26 +#define _PCI_ATH_FIXUP
27 +
28 +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init;
29 +
30 +#endif /* _PCI_ATH_FIXUP */
31 Index: linux-3.10.12/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
32 ===================================================================
33 --- linux-3.10.12.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2013-09-14 15:55:12.000000000 +0200
34 +++ linux-3.10.12/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2013-09-17 22:32:50.389021711 +0200
35 @@ -90,5 +90,8 @@
36 extern void ltq_pmu_enable(unsigned int module);
37 extern void ltq_pmu_disable(unsigned int module);
38
39 +/* allow the ethernet driver to load a flash mapped mac addr */
40 +const u8* ltq_get_eth_mac(void);
41 +
42 #endif /* CONFIG_SOC_TYPE_XWAY */
43 #endif /* _LTQ_XWAY_H__ */
44 Index: linux-3.10.12/arch/mips/lantiq/xway/Makefile
45 ===================================================================
46 --- linux-3.10.12.orig/arch/mips/lantiq/xway/Makefile 2013-09-17 22:32:50.305021707 +0200
47 +++ linux-3.10.12/arch/mips/lantiq/xway/Makefile 2013-09-18 02:41:31.613659574 +0200
48 @@ -2,4 +2,6 @@
49
50 obj-y += vmmc.o
51
52 +obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
53 +
54 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
55 Index: linux-3.10.12/arch/mips/lantiq/xway/ath_eep.c
56 ===================================================================
57 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
58 +++ linux-3.10.12/arch/mips/lantiq/xway/ath_eep.c 2013-09-18 02:41:28.525659442 +0200
59 @@ -0,0 +1,250 @@
60 +/*
61 + * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
62 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
63 + * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
64 + * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
65 + * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
66 + *
67 + * This program is free software; you can redistribute it and/or modify it
68 + * under the terms of the GNU General Public License version 2 as published
69 + * by the Free Software Foundation.
70 + */
71 +
72 +#include <linux/init.h>
73 +#include <linux/module.h>
74 +#include <linux/platform_device.h>
75 +#include <linux/etherdevice.h>
76 +#include <linux/ath5k_platform.h>
77 +#include <linux/ath9k_platform.h>
78 +#include <linux/pci.h>
79 +#include <linux/err.h>
80 +#include <linux/mtd/mtd.h>
81 +#include <pci-ath-fixup.h>
82 +#include <lantiq_soc.h>
83 +#include <linux/of_net.h>
84 +
85 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
86 +struct ath5k_platform_data ath5k_pdata;
87 +struct ath9k_platform_data ath9k_pdata = {
88 + .led_pin = -1,
89 +};
90 +static u8 athxk_eeprom_mac[6];
91 +
92 +static int ath9k_pci_plat_dev_init(struct pci_dev *dev)
93 +{
94 + dev->dev.platform_data = &ath9k_pdata;
95 + return 0;
96 +}
97 +
98 +int __init of_ath9k_eeprom_probe(struct platform_device *pdev)
99 +{
100 + struct device_node *np = pdev->dev.of_node, *mtd_np;
101 + int mac_offset;
102 + u32 mac_inc = 0, pci_slot = 0;
103 + int i;
104 + struct mtd_info *the_mtd;
105 + size_t flash_readlen;
106 + const __be32 *list;
107 + const char *part;
108 + phandle phandle;
109 +
110 + list = of_get_property(np, "ath,eep-flash", &i);
111 + if (!list || (i != (2 * sizeof(*list)))) {
112 + dev_err(&pdev->dev, "failed to find ath,eep-flash\n");
113 + return -ENODEV;
114 + }
115 +
116 + phandle = be32_to_cpup(list++);
117 + if (!phandle) {
118 + dev_err(&pdev->dev, "failed to find phandle\n");
119 + return -ENODEV;
120 + }
121 +
122 + mtd_np = of_find_node_by_phandle(phandle);
123 + if (!mtd_np) {
124 + dev_err(&pdev->dev, "failed to find mtd node\n");
125 + return -ENODEV;
126 + }
127 +
128 + part = of_get_property(mtd_np, "label", NULL);
129 + if (!part)
130 + part = mtd_np->name;
131 +
132 + the_mtd = get_mtd_device_nm(part);
133 + if (the_mtd == ERR_PTR(-ENODEV)) {
134 + dev_err(&pdev->dev, "failed to find mtd device\n");
135 + return -ENODEV;
136 + }
137 +
138 + i = mtd_read(the_mtd, be32_to_cpup(list),
139 + ATH9K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
140 + (void *) ath9k_pdata.eeprom_data);
141 + put_mtd_device(the_mtd);
142 + if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) {
143 + dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
144 + return -ENODEV;
145 + }
146 +
147 + if (of_find_property(np, "ath,eep-swap", NULL))
148 + for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++)
149 + ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]);
150 +
151 + if (of_find_property(np, "ath,eep-endian", NULL)) {
152 + ath9k_pdata.endian_check = true;
153 +
154 + dev_info(&pdev->dev, "endian check enabled.\n");
155 + }
156 +
157 + if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
158 + memcpy_fromio(athxk_eeprom_mac, (void*) ath9k_pdata.eeprom_data + mac_offset, 6);
159 + } else {
160 + random_ether_addr(athxk_eeprom_mac);
161 + if (of_get_mac_address_mtd(np, athxk_eeprom_mac))
162 + dev_warn(&pdev->dev, "using random mac\n");
163 + }
164 +
165 + if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
166 + athxk_eeprom_mac[5] += mac_inc;
167 +
168 + ath9k_pdata.macaddr = athxk_eeprom_mac;
169 + ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init;
170 +
171 + if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) {
172 + ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data);
173 + dev_info(&pdev->dev, "pci slot: %u\n", pci_slot);
174 + }
175 +
176 + dev_info(&pdev->dev, "loaded ath9k eeprom\n");
177 +
178 + return 0;
179 +}
180 +
181 +static struct of_device_id ath9k_eeprom_ids[] = {
182 + { .compatible = "ath9k,eeprom" },
183 + { }
184 +};
185 +
186 +static struct platform_driver ath9k_eeprom_driver = {
187 + .driver = {
188 + .name = "ath9k,eeprom",
189 + .owner = THIS_MODULE,
190 + .of_match_table = of_match_ptr(ath9k_eeprom_ids),
191 + },
192 +};
193 +
194 +static int ath9k_eep_loaded;
195 +static int __init of_ath9k_eeprom_init(void)
196 +{
197 + int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
198 +
199 + if (!ret)
200 + ath9k_eep_loaded = 1;
201 +
202 + return ret;
203 +}
204 +
205 +static int __init of_ath9k_eeprom_init_late(void)
206 +{
207 + if (ath9k_eep_loaded)
208 + return 0;
209 + return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
210 +}
211 +late_initcall(of_ath9k_eeprom_init_late);
212 +subsys_initcall(of_ath9k_eeprom_init);
213 +
214 +static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
215 +{
216 + dev->dev.platform_data = &ath5k_pdata;
217 + return 0;
218 +}
219 +
220 +int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
221 +{
222 + struct device_node *np = pdev->dev.of_node, *mtd_np;
223 + int mac_offset;
224 + u32 mac_inc = 0;
225 + int i;
226 + struct mtd_info *the_mtd;
227 + size_t flash_readlen;
228 + const __be32 *list;
229 + const char *part;
230 + phandle phandle;
231 +
232 + list = of_get_property(np, "ath,eep-flash", &i);
233 + if (!list || (i != (2 * sizeof(*list)))) {
234 + dev_err(&pdev->dev, "failed to find ath,eep-flash\n");
235 + return -ENODEV;
236 + }
237 +
238 + phandle = be32_to_cpup(list++);
239 + if (!phandle) {
240 + dev_err(&pdev->dev, "failed to find phandle\n");
241 + return -ENODEV;
242 + }
243 +
244 + mtd_np = of_find_node_by_phandle(phandle);
245 + if (!mtd_np) {
246 + dev_err(&pdev->dev, "failed to find mtd node\n");
247 + return -ENODEV;
248 + }
249 +
250 + part = of_get_property(mtd_np, "label", NULL);
251 + if (!part)
252 + part = mtd_np->name;
253 +
254 + the_mtd = get_mtd_device_nm(part);
255 + if (the_mtd == ERR_PTR(-ENODEV)) {
256 + dev_err(&pdev->dev, "failed to find mtd device\n");
257 + return -ENODEV;
258 + }
259 +
260 + i = mtd_read(the_mtd, be32_to_cpup(list),
261 + ATH5K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
262 + (void *) ath5k_pdata.eeprom_data);
263 + put_mtd_device(the_mtd);
264 + if ((sizeof(ath5k_pdata.eeprom_data) != flash_readlen) || i) {
265 + dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
266 + return -ENODEV;
267 + }
268 +
269 + if (of_find_property(np, "ath,eep-swap", NULL))
270 + for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
271 + ath5k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]);
272 +
273 + if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
274 + memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_pdata.eeprom_data + mac_offset, 6);
275 + } else {
276 + random_ether_addr(athxk_eeprom_mac);
277 + if (of_get_mac_address_mtd(np, athxk_eeprom_mac))
278 + dev_warn(&pdev->dev, "using random mac\n");
279 + }
280 +
281 + if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
282 + athxk_eeprom_mac[5] += mac_inc;
283 +
284 + ath5k_pdata.macaddr = athxk_eeprom_mac;
285 + ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
286 +
287 + dev_info(&pdev->dev, "loaded ath5k eeprom\n");
288 +
289 + return 0;
290 +}
291 +
292 +static struct of_device_id ath5k_eeprom_ids[] = {
293 + { .compatible = "ath5k,eeprom" },
294 + { }
295 +};
296 +
297 +static struct platform_driver ath5k_eeprom_driver = {
298 + .driver = {
299 + .name = "ath5k,eeprom",
300 + .owner = THIS_MODULE,
301 + .of_match_table = of_match_ptr(ath5k_eeprom_ids),
302 + },
303 +};
304 +
305 +static int __init of_ath5k_eeprom_init(void)
306 +{
307 + return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
308 +}
309 +device_initcall(of_ath5k_eeprom_init);
310 Index: linux-3.10.12/arch/mips/lantiq/xway/pci-ath-fixup.c
311 ===================================================================
312 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
313 +++ linux-3.10.12/arch/mips/lantiq/xway/pci-ath-fixup.c 2013-09-17 22:32:50.389021711 +0200
314 @@ -0,0 +1,109 @@
315 +/*
316 + * Atheros AP94 reference board PCI initialization
317 + *
318 + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
319 + *
320 + * This program is free software; you can redistribute it and/or modify it
321 + * under the terms of the GNU General Public License version 2 as published
322 + * by the Free Software Foundation.
323 + */
324 +
325 +#include <linux/pci.h>
326 +#include <linux/init.h>
327 +#include <linux/delay.h>
328 +#include <lantiq_soc.h>
329 +
330 +#define LTQ_PCI_MEM_BASE 0x18000000
331 +
332 +struct ath_fixup {
333 + u16 *cal_data;
334 + unsigned slot;
335 +};
336 +
337 +static int ath_num_fixups;
338 +static struct ath_fixup ath_fixups[2];
339 +
340 +static void ath_pci_fixup(struct pci_dev *dev)
341 +{
342 + void __iomem *mem;
343 + u16 *cal_data = NULL;
344 + u16 cmd;
345 + u32 bar0;
346 + u32 val;
347 + unsigned i;
348 +
349 + for (i = 0; i < ath_num_fixups; i++) {
350 + if (ath_fixups[i].cal_data == NULL)
351 + continue;
352 +
353 + if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
354 + continue;
355 +
356 + cal_data = ath_fixups[i].cal_data;
357 + break;
358 + }
359 +
360 + if (cal_data == NULL)
361 + return;
362 +
363 + if (*cal_data != 0xa55a) {
364 + pr_err("pci %s: invalid calibration data\n", pci_name(dev));
365 + return;
366 + }
367 +
368 + pr_info("pci %s: fixup device configuration\n", pci_name(dev));
369 +
370 + mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
371 + if (!mem) {
372 + pr_err("pci %s: ioremap error\n", pci_name(dev));
373 + return;
374 + }
375 +
376 + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
377 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
378 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
379 + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
380 + pci_write_config_word(dev, PCI_COMMAND, cmd);
381 +
382 + /* set pointer to first reg address */
383 + cal_data += 3;
384 + while (*cal_data != 0xffff) {
385 + u32 reg;
386 + reg = *cal_data++;
387 + val = *cal_data++;
388 + val |= (*cal_data++) << 16;
389 +
390 + ltq_w32(swab32(val), mem + reg);
391 + udelay(100);
392 + }
393 +
394 + pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
395 + dev->vendor = val & 0xffff;
396 + dev->device = (val >> 16) & 0xffff;
397 +
398 + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
399 + dev->revision = val & 0xff;
400 + dev->class = val >> 8; /* upper 3 bytes */
401 +
402 + pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n",
403 + pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
404 +
405 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
406 + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
407 + pci_write_config_word(dev, PCI_COMMAND, cmd);
408 +
409 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
410 +
411 + iounmap(mem);
412 +}
413 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
414 +
415 +void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
416 +{
417 + if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
418 + return;
419 +
420 + ath_fixups[ath_num_fixups].slot = slot;
421 + ath_fixups[ath_num_fixups].cal_data = cal_data;
422 + ath_num_fixups++;
423 +}
424 Index: linux-3.10.12/arch/mips/lantiq/xway/rt_eep.c
425 ===================================================================
426 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
427 +++ linux-3.10.12/arch/mips/lantiq/xway/rt_eep.c 2013-09-17 22:32:50.389021711 +0200
428 @@ -0,0 +1,60 @@
429 +/*
430 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
431 + *
432 + * This program is free software; you can redistribute it and/or modify it
433 + * under the terms of the GNU General Public License version 2 as published
434 + * by the Free Software Foundation.
435 + */
436 +
437 +#include <linux/init.h>
438 +#include <linux/module.h>
439 +#include <linux/pci.h>
440 +#include <linux/platform_device.h>
441 +#include <linux/rt2x00_platform.h>
442 +
443 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
444 +static struct rt2x00_platform_data rt2x00_pdata;
445 +
446 +static int rt2x00_pci_plat_dev_init(struct pci_dev *dev)
447 +{
448 + dev->dev.platform_data = &rt2x00_pdata;
449 + return 0;
450 +}
451 +
452 +int __init of_ralink_eeprom_probe(struct platform_device *pdev)
453 +{
454 + struct device_node *np = pdev->dev.of_node;
455 + const char *eeprom;
456 +
457 + if (of_property_read_string(np, "ralink,eeprom", &eeprom)) {
458 + dev_err(&pdev->dev, "failed to load eeprom filename\n");
459 + return 0;
460 + }
461 +
462 + rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL);
463 +// rt2x00_pdata.mac_address = mac;
464 + ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init;
465 +
466 + dev_info(&pdev->dev, "using %s as eeprom\n", eeprom);
467 +
468 + return 0;
469 +}
470 +
471 +static struct of_device_id ralink_eeprom_ids[] = {
472 + { .compatible = "ralink,eeprom" },
473 + { }
474 +};
475 +
476 +static struct platform_driver ralink_eeprom_driver = {
477 + .driver = {
478 + .name = "ralink,eeprom",
479 + .owner = THIS_MODULE,
480 + .of_match_table = of_match_ptr(ralink_eeprom_ids),
481 + },
482 +};
483 +
484 +static int __init of_ralink_eeprom_init(void)
485 +{
486 + return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe);
487 +}
488 +device_initcall(of_ralink_eeprom_init);