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[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.10 / 0020-NET-MIPS-lantiq-adds-xrx200-net.patch
1 From 5c7a5ddaf069b7061e1c7b536756b0b70d37b991 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: [PATCH 20/34] NET: MIPS: lantiq: adds xrx200-net
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++++
10 drivers/net/ethernet/lantiq_xrx200.c | 1203 ++++++++++++++++++++++++++++++++++
11 4 files changed, 1374 insertions(+), 1 deletion(-)
12 create mode 100644 drivers/net/ethernet/lantiq_pce.h
13 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
14
15 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
16 index ed956e0..9261fe4 100644
17 --- a/drivers/net/ethernet/Kconfig
18 +++ b/drivers/net/ethernet/Kconfig
19 @@ -83,7 +83,13 @@ config LANTIQ_ETOP
20 tristate "Lantiq SoC ETOP driver"
21 depends on SOC_TYPE_XWAY
22 ---help---
23 - Support for the MII0 inside the Lantiq SoC
24 + Support for the MII0 inside the Lantiq ADSL SoC
25 +
26 +config LANTIQ_XRX200
27 + tristate "Lantiq SoC XRX200 driver"
28 + depends on SOC_TYPE_XWAY
29 + ---help---
30 + Support for the MII0 inside the Lantiq VDSL SoC
31
32 source "drivers/net/ethernet/marvell/Kconfig"
33 source "drivers/net/ethernet/mellanox/Kconfig"
34 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
35 index 8268d85..e8410d8 100644
36 --- a/drivers/net/ethernet/Makefile
37 +++ b/drivers/net/ethernet/Makefile
38 @@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/
39 obj-$(CONFIG_JME) += jme.o
40 obj-$(CONFIG_KORINA) += korina.o
41 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
42 +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
43 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
44 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
45 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
46 diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h
47 new file mode 100644
48 index 0000000..0c38efe
49 --- /dev/null
50 +++ b/drivers/net/ethernet/lantiq_pce.h
51 @@ -0,0 +1,163 @@
52 +/*
53 + * This program is free software; you can redistribute it and/or modify it
54 + * under the terms of the GNU General Public License version 2 as published
55 + * by the Free Software Foundation.
56 + *
57 + * This program is distributed in the hope that it will be useful,
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + *
62 + * You should have received a copy of the GNU General Public License
63 + * along with this program; if not, write to the Free Software
64 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
65 + *
66 + * Copyright (C) 2010 Lantiq Deutschland GmbH
67 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
68 + *
69 + * PCE microcode extracted from UGW5.2 switch api
70 + */
71 +
72 +/* Switch API Micro Code V0.3 */
73 +enum {
74 + OUT_MAC0 = 0,
75 + OUT_MAC1,
76 + OUT_MAC2,
77 + OUT_MAC3,
78 + OUT_MAC4,
79 + OUT_MAC5,
80 + OUT_ETHTYP,
81 + OUT_VTAG0,
82 + OUT_VTAG1,
83 + OUT_ITAG0,
84 + OUT_ITAG1, /*10 */
85 + OUT_ITAG2,
86 + OUT_ITAG3,
87 + OUT_IP0,
88 + OUT_IP1,
89 + OUT_IP2,
90 + OUT_IP3,
91 + OUT_SIP0,
92 + OUT_SIP1,
93 + OUT_SIP2,
94 + OUT_SIP3, /*20*/
95 + OUT_SIP4,
96 + OUT_SIP5,
97 + OUT_SIP6,
98 + OUT_SIP7,
99 + OUT_DIP0,
100 + OUT_DIP1,
101 + OUT_DIP2,
102 + OUT_DIP3,
103 + OUT_DIP4,
104 + OUT_DIP5, /*30*/
105 + OUT_DIP6,
106 + OUT_DIP7,
107 + OUT_SESID,
108 + OUT_PROT,
109 + OUT_APP0,
110 + OUT_APP1,
111 + OUT_IGMP0,
112 + OUT_IGMP1,
113 + OUT_IPOFF, /*39*/
114 + OUT_NONE = 63
115 +};
116 +
117 +/* parser's microcode length type */
118 +#define INSTR 0
119 +#define IPV6 1
120 +#define LENACCU 2
121 +
122 +/* parser's microcode flag type */
123 +enum {
124 + FLAG_ITAG = 0,
125 + FLAG_VLAN,
126 + FLAG_SNAP,
127 + FLAG_PPPOE,
128 + FLAG_IPV6,
129 + FLAG_IPV6FL,
130 + FLAG_IPV4,
131 + FLAG_IGMP,
132 + FLAG_TU,
133 + FLAG_HOP,
134 + FLAG_NN1, /*10 */
135 + FLAG_NN2,
136 + FLAG_END,
137 + FLAG_NO, /*13*/
138 +};
139 +
140 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
141 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
142 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
143 +struct pce_microcode {
144 + unsigned short val[4];
145 +/* unsigned short val_2;
146 + unsigned short val_1;
147 + unsigned short val_0;*/
148 +} pce_microcode[] = {
149 + /* value mask ns fields L type flags ipv4_len */
150 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
151 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
152 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
153 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
154 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
155 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
156 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
158 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
160 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
161 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
163 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
165 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
166 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
167 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
168 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
170 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
172 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
173 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
174 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
175 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
176 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
177 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
178 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
179 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
180 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
181 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
182 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
183 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
184 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
185 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
186 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
187 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
188 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
189 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
208 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
209 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
210 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
211 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
212 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
213 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
214 +};
215 diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
216 new file mode 100644
217 index 0000000..2d40c64
218 --- /dev/null
219 +++ b/drivers/net/ethernet/lantiq_xrx200.c
220 @@ -0,0 +1,1203 @@
221 +/*
222 + * This program is free software; you can redistribute it and/or modify it
223 + * under the terms of the GNU General Public License version 2 as published
224 + * by the Free Software Foundation.
225 + *
226 + * This program is distributed in the hope that it will be useful,
227 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
228 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
229 + * GNU General Public License for more details.
230 + *
231 + * You should have received a copy of the GNU General Public License
232 + * along with this program; if not, write to the Free Software
233 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
234 + *
235 + * Copyright (C) 2010 Lantiq Deutschland
236 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
237 + */
238 +
239 +#include <linux/etherdevice.h>
240 +#include <linux/module.h>
241 +#include <linux/platform_device.h>
242 +#include <linux/interrupt.h>
243 +#include <linux/clk.h>
244 +#include <asm/delay.h>
245 +
246 +#include <linux/of_net.h>
247 +#include <linux/of_mdio.h>
248 +#include <linux/of_gpio.h>
249 +
250 +#include <xway_dma.h>
251 +#include <lantiq_soc.h>
252 +
253 +#include "lantiq_pce.h"
254 +
255 +#define SW_POLLING
256 +#define SW_ROUTING
257 +#define SW_PORTMAP
258 +
259 +#ifdef SW_ROUTING
260 + #ifdef SW_PORTMAP
261 +#define XRX200_MAX_DEV 2
262 + #else
263 +#define XRX200_MAX_DEV 2
264 + #endif
265 +#else
266 +#define XRX200_MAX_DEV 1
267 +#endif
268 +
269 +#define XRX200_MAX_PORT 7
270 +#define XRX200_MAX_DMA 8
271 +
272 +#define XRX200_HEADROOM 4
273 +
274 +#define XRX200_TX_TIMEOUT (10 * HZ)
275 +
276 +/* port type */
277 +#define XRX200_PORT_TYPE_PHY 1
278 +#define XRX200_PORT_TYPE_MAC 2
279 +
280 +/* DMA */
281 +#define XRX200_DMA_CRC_LEN 0x4
282 +#define XRX200_DMA_DATA_LEN 0x600
283 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
284 +#define XRX200_DMA_RX 0
285 +#define XRX200_DMA_TX 1
286 +#define XRX200_DMA_IS_TX(x) (x%2)
287 +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
288 +
289 +/* fetch / store dma */
290 +#define FDMA_PCTRL0 0x2A00
291 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
292 +#define SDMA_PCTRL0 0x2F00
293 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
294 +
295 +/* buffer management */
296 +#define BM_PCFG0 0x200
297 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
298 +
299 +/* MDIO */
300 +#define MDIO_GLOB 0x0000
301 +#define MDIO_CTRL 0x0020
302 +#define MDIO_READ 0x0024
303 +#define MDIO_WRITE 0x0028
304 +#define MDIO_PHY0 0x0054
305 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
306 +#define MDIO_CLK_CFG0 0x002C
307 +#define MDIO_CLK_CFG1 0x0030
308 +
309 +#define MDIO_GLOB_ENABLE 0x8000
310 +#define MDIO_BUSY BIT(12)
311 +#define MDIO_RD BIT(11)
312 +#define MDIO_WR BIT(10)
313 +#define MDIO_MASK 0x1f
314 +#define MDIO_ADDRSHIFT 5
315 +#define MDIO1_25MHZ 9
316 +
317 +#define MDIO_PHY_LINK_DOWN 0x4000
318 +#define MDIO_PHY_LINK_UP 0x2000
319 +
320 +#define MDIO_PHY_SPEED_M10 0x0000
321 +#define MDIO_PHY_SPEED_M100 0x0800
322 +#define MDIO_PHY_SPEED_G1 0x1000
323 +
324 +#define MDIO_PHY_FDUP_EN 0x0600
325 +#define MDIO_PHY_FDUP_DIS 0x0200
326 +
327 +#define MDIO_PHY_LINK_MASK 0x6000
328 +#define MDIO_PHY_SPEED_MASK 0x1800
329 +#define MDIO_PHY_FDUP_MASK 0x0600
330 +#define MDIO_PHY_ADDR_MASK 0x001f
331 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
332 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
333 +
334 +/* MII */
335 +#define MII_CFG(p) (p * 8)
336 +
337 +#define MII_CFG_EN BIT(14)
338 +
339 +#define MII_CFG_MODE_MIIP 0x0
340 +#define MII_CFG_MODE_MIIM 0x1
341 +#define MII_CFG_MODE_RMIIP 0x2
342 +#define MII_CFG_MODE_RMIIM 0x3
343 +#define MII_CFG_MODE_RGMII 0x4
344 +#define MII_CFG_MODE_MASK 0xf
345 +
346 +#define MII_CFG_RATE_M2P5 0x00
347 +#define MII_CFG_RATE_M25 0x10
348 +#define MII_CFG_RATE_M125 0x20
349 +#define MII_CFG_RATE_M50 0x30
350 +#define MII_CFG_RATE_AUTO 0x40
351 +#define MII_CFG_RATE_MASK 0x70
352 +
353 +/* cpu port mac */
354 +#define PMAC_HD_CTL 0x0000
355 +#define PMAC_RX_IPG 0x0024
356 +#define PMAC_EWAN 0x002c
357 +
358 +#define PMAC_IPG_MASK 0xf
359 +#define PMAC_HD_CTL_AS 0x0008
360 +#define PMAC_HD_CTL_AC 0x0004
361 +#define PMAC_HD_CTL_RXSH 0x0040
362 +#define PMAC_HD_CTL_AST 0x0080
363 +#define PMAC_HD_CTL_RST 0x0100
364 +
365 +/* PCE */
366 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
367 +#define PCE_TBL_MASK 0x1120
368 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
369 +#define PCE_TBL_ADDR 0x1138
370 +#define PCE_TBL_CTRL 0x113c
371 +#define PCE_PMAP1 0x114c
372 +#define PCE_PMAP2 0x1150
373 +#define PCE_PMAP3 0x1154
374 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
375 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
376 +
377 +#define PCE_TBL_BUSY BIT(15)
378 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
379 +#define PCE_TBL_CFG_ADWR 0x20
380 +#define PCE_TBL_CFG_ADWR_MASK 0x60
381 +#define PCE_INGRESS BIT(11)
382 +
383 +/* MAC */
384 +#define MAC_FLEN_REG (0x2314)
385 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
386 +
387 +/* buffer management */
388 +#define BM_PCFG(p) (0x200 + (p * 8))
389 +
390 +/* special tag in TX path header */
391 +#define SPID_SHIFT 24
392 +#define DPID_SHIFT 16
393 +#define DPID_ENABLE 1
394 +#define SPID_CPU_PORT 2
395 +#define PORT_MAP_SEL BIT(15)
396 +#define PORT_MAP_EN BIT(14)
397 +#define PORT_MAP_SHIFT 1
398 +#define PORT_MAP_MASK 0x3f
399 +
400 +#define SPPID_MASK 0x7
401 +#define SPPID_SHIFT 4
402 +
403 +/* MII regs not yet in linux */
404 +#define MDIO_DEVAD_NONE (-1)
405 +#define ADVERTIZE_MPD (1 << 10)
406 +
407 +struct xrx200_port {
408 + u8 num;
409 + u8 phy_addr;
410 + u16 flags;
411 + phy_interface_t phy_if;
412 +
413 + int link;
414 + int gpio;
415 + enum of_gpio_flags gpio_flags;
416 +
417 + struct phy_device *phydev;
418 + struct device_node *phy_node;
419 +};
420 +
421 +struct xrx200_chan {
422 + int idx;
423 + int refcount;
424 + int tx_free;
425 +
426 + struct net_device dummy_dev;
427 + struct net_device *devs[XRX200_MAX_DEV];
428 +
429 + struct tasklet_struct tasklet;
430 + struct napi_struct napi;
431 + struct ltq_dma_channel dma;
432 + struct sk_buff *skb[LTQ_DESC_NUM];
433 +};
434 +
435 +struct xrx200_hw {
436 + struct clk *clk;
437 + struct mii_bus *mii_bus;
438 +
439 + struct xrx200_chan chan[XRX200_MAX_DMA];
440 +
441 + struct net_device *devs[XRX200_MAX_DEV];
442 + int num_devs;
443 +
444 + int port_map[XRX200_MAX_PORT];
445 + unsigned short wan_map;
446 +
447 + spinlock_t lock;
448 +};
449 +
450 +struct xrx200_priv {
451 + struct net_device_stats stats;
452 + int id;
453 +
454 + struct xrx200_port port[XRX200_MAX_PORT];
455 + int num_port;
456 + int wan;
457 + unsigned short port_map;
458 + unsigned char mac[6];
459 +
460 + struct xrx200_hw *hw;
461 +};
462 +
463 +static __iomem void *xrx200_switch_membase;
464 +static __iomem void *xrx200_mii_membase;
465 +static __iomem void *xrx200_mdio_membase;
466 +static __iomem void *xrx200_pmac_membase;
467 +
468 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
469 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
470 +#define ltq_switch_w32_mask(x, y, z) \
471 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
472 +
473 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
474 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
475 +#define ltq_mdio_w32_mask(x, y, z) \
476 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
477 +
478 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
479 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
480 +#define ltq_mii_w32_mask(x, y, z) \
481 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
482 +
483 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
484 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
485 +#define ltq_pmac_w32_mask(x, y, z) \
486 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
487 +
488 +static int xrx200_open(struct net_device *dev)
489 +{
490 + struct xrx200_priv *priv = netdev_priv(dev);
491 + unsigned long flags;
492 + int i;
493 +
494 + for (i = 0; i < XRX200_MAX_DMA; i++) {
495 + if (!priv->hw->chan[i].dma.irq)
496 + continue;
497 + spin_lock_irqsave(&priv->hw->lock, flags);
498 + if (!priv->hw->chan[i].refcount) {
499 + if (XRX200_DMA_IS_RX(i))
500 + napi_enable(&priv->hw->chan[i].napi);
501 + ltq_dma_open(&priv->hw->chan[i].dma);
502 + }
503 + priv->hw->chan[i].refcount++;
504 + spin_unlock_irqrestore(&priv->hw->lock, flags);
505 + }
506 + for (i = 0; i < priv->num_port; i++)
507 + if (priv->port[i].phydev)
508 + phy_start(priv->port[i].phydev);
509 + netif_start_queue(dev);
510 +
511 + return 0;
512 +}
513 +
514 +static int xrx200_close(struct net_device *dev)
515 +{
516 + struct xrx200_priv *priv = netdev_priv(dev);
517 + unsigned long flags;
518 + int i;
519 +
520 + netif_stop_queue(dev);
521 +
522 + for (i = 0; i < priv->num_port; i++)
523 + if (priv->port[i].phydev)
524 + phy_stop(priv->port[i].phydev);
525 +
526 + for (i = 0; i < XRX200_MAX_DMA; i++) {
527 + if (!priv->hw->chan[i].dma.irq)
528 + continue;
529 + spin_lock_irqsave(&priv->hw->lock, flags);
530 + priv->hw->chan[i].refcount--;
531 + if (!priv->hw->chan[i].refcount) {
532 + if (XRX200_DMA_IS_RX(i))
533 + napi_disable(&priv->hw->chan[i].napi);
534 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
535 + }
536 + spin_unlock_irqrestore(&priv->hw->lock, flags);
537 + }
538 +
539 + return 0;
540 +}
541 +
542 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
543 +{
544 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
545 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
546 + if (!ch->skb[ch->dma.desc])
547 + return -ENOMEM;
548 +
549 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
550 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
551 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
552 + DMA_FROM_DEVICE);
553 + ch->dma.desc_base[ch->dma.desc].addr =
554 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
555 + ch->dma.desc_base[ch->dma.desc].ctl =
556 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
557 + XRX200_DMA_DATA_LEN;
558 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
559 +
560 + return 0;
561 +}
562 +
563 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
564 +{
565 + struct net_device *dev = ch->devs[id];
566 + struct xrx200_priv *priv = netdev_priv(dev);
567 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
568 + struct sk_buff *skb = ch->skb[ch->dma.desc];
569 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
570 + unsigned long flags;
571 +
572 + spin_lock_irqsave(&priv->hw->lock, flags);
573 + if (xrx200_alloc_skb(ch)) {
574 + netdev_err(dev,
575 + "failed to allocate new rx buffer, stopping DMA\n");
576 + ltq_dma_close(&ch->dma);
577 + }
578 +
579 + ch->dma.desc++;
580 + ch->dma.desc %= LTQ_DESC_NUM;
581 + spin_unlock_irqrestore(&priv->hw->lock, flags);
582 +
583 + skb_put(skb, len);
584 +#ifdef SW_ROUTING
585 + skb_pull(skb, 8);
586 +#endif
587 + skb->dev = dev;
588 + skb->protocol = eth_type_trans(skb, dev);
589 + netif_receive_skb(skb);
590 + priv->stats.rx_packets++;
591 + priv->stats.rx_bytes+=len;
592 +}
593 +
594 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
595 +{
596 + struct xrx200_chan *ch = container_of(napi,
597 + struct xrx200_chan, napi);
598 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
599 + int rx = 0;
600 + int complete = 0;
601 + unsigned long flags;
602 +
603 + while ((rx < budget) && !complete) {
604 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
605 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
606 +#ifdef SW_ROUTING
607 + struct sk_buff *skb = ch->skb[ch->dma.desc];
608 + u32 *special_tag = (u32*)skb->data;
609 + int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
610 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
611 +#else
612 + xrx200_hw_receive(ch, 0);
613 +#endif
614 + rx++;
615 + } else {
616 + complete = 1;
617 + }
618 + }
619 + if (complete || !rx) {
620 + napi_complete(&ch->napi);
621 + spin_lock_irqsave(&priv->hw->lock, flags);
622 + ltq_dma_ack_irq(&ch->dma);
623 + spin_unlock_irqrestore(&priv->hw->lock, flags);
624 + }
625 + return rx;
626 +}
627 +
628 +static void xrx200_tx_housekeeping(unsigned long ptr)
629 +{
630 + struct xrx200_hw *hw = (struct xrx200_hw *) ptr;
631 + struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX];
632 + unsigned long flags;
633 + int i;
634 +
635 + spin_lock_irqsave(&hw->lock, flags);
636 + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
637 + dev_kfree_skb_any(ch->skb[ch->tx_free]);
638 + ch->skb[ch->tx_free] = NULL;
639 + memset(&ch->dma.desc_base[ch->tx_free], 0,
640 + sizeof(struct ltq_dma_desc));
641 + ch->tx_free++;
642 + ch->tx_free %= LTQ_DESC_NUM;
643 + }
644 + spin_unlock_irqrestore(&hw->lock, flags);
645 +
646 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) {
647 + struct netdev_queue *txq =
648 + netdev_get_tx_queue(ch->devs[i], 0);
649 + if (netif_tx_queue_stopped(txq))
650 + netif_tx_start_queue(txq);
651 + }
652 +
653 + spin_lock_irqsave(&hw->lock, flags);
654 + ltq_dma_ack_irq(&ch->dma);
655 + spin_unlock_irqrestore(&hw->lock, flags);
656 +}
657 +
658 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
659 +{
660 + struct xrx200_priv *priv = netdev_priv(dev);
661 +
662 + return &priv->stats;
663 +}
664 +
665 +static void xrx200_tx_timeout(struct net_device *dev)
666 +{
667 + struct xrx200_priv *priv = netdev_priv(dev);
668 +
669 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
670 +
671 + priv->stats.tx_errors++;
672 + netif_wake_queue(dev);
673 +}
674 +
675 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
676 +{
677 + int queue = skb_get_queue_mapping(skb);
678 + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
679 + struct xrx200_priv *priv = netdev_priv(dev);
680 + struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
681 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
682 + unsigned long flags;
683 + u32 byte_offset;
684 + int len;
685 +#ifdef SW_ROUTING
686 + #ifdef SW_PORTMAP
687 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE;
688 + #else
689 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
690 + #endif
691 +#endif
692 +
693 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
694 +
695 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
696 + netdev_err(dev, "tx ring full\n");
697 + netif_tx_stop_queue(txq);
698 + return NETDEV_TX_BUSY;
699 + }
700 +#ifdef SW_ROUTING
701 + #ifdef SW_PORTMAP
702 + special_tag |= priv->port_map << PORT_MAP_SHIFT;
703 + #else
704 + if(priv->id)
705 + special_tag |= (1 << DPID_SHIFT);
706 + #endif
707 + if(skb_headroom(skb) < 4) {
708 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
709 + dev_kfree_skb_any(skb);
710 + skb = tmp;
711 + }
712 + skb_push(skb, 4);
713 + memcpy(skb->data, &special_tag, sizeof(u32));
714 + len += 4;
715 +#endif
716 +
717 + /* dma needs to start on a 16 byte aligned address */
718 + byte_offset = CPHYSADDR(skb->data) % 16;
719 + ch->skb[ch->dma.desc] = skb;
720 +
721 + dev->trans_start = jiffies;
722 +
723 + spin_lock_irqsave(&priv->hw->lock, flags);
724 + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
725 + DMA_TO_DEVICE)) - byte_offset;
726 + wmb();
727 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
728 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
729 + ch->dma.desc++;
730 + ch->dma.desc %= LTQ_DESC_NUM;
731 + spin_unlock_irqrestore(&priv->hw->lock, flags);
732 +
733 + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
734 + netif_tx_stop_queue(txq);
735 +
736 + priv->stats.tx_packets++;
737 + priv->stats.tx_bytes+=len;
738 +
739 + return NETDEV_TX_OK;
740 +}
741 +
742 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
743 +{
744 + struct xrx200_hw *hw = priv;
745 + int ch = irq - XRX200_DMA_IRQ;
746 +
747 + if (ch % 2)
748 + tasklet_schedule(&hw->chan[ch].tasklet);
749 + else
750 + napi_schedule(&hw->chan[ch].napi);
751 +
752 + return IRQ_HANDLED;
753 +}
754 +
755 +static int xrx200_dma_init(struct xrx200_hw *hw)
756 +{
757 + int i, err = 0;
758 +
759 + ltq_dma_init_port(DMA_PORT_ETOP);
760 +
761 + for (i = 0; i < 8 && !err; i++) {
762 + int irq = XRX200_DMA_IRQ + i;
763 + struct xrx200_chan *ch = &hw->chan[i];
764 +
765 + ch->idx = ch->dma.nr = i;
766 +
767 + if (i == XRX200_DMA_TX) {
768 + ltq_dma_alloc_tx(&ch->dma);
769 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
770 + } else if (i == XRX200_DMA_RX) {
771 + ltq_dma_alloc_rx(&ch->dma);
772 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
773 + ch->dma.desc++)
774 + if (xrx200_alloc_skb(ch))
775 + err = -ENOMEM;
776 + ch->dma.desc = 0;
777 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
778 + } else
779 + continue;
780 +
781 + if (!err)
782 + ch->dma.irq = irq;
783 + }
784 +
785 + return err;
786 +}
787 +
788 +#ifdef SW_POLLING
789 +static void xrx200_gmac_update(struct xrx200_port *port)
790 +{
791 + u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
792 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
793 + u16 miirate = 0;
794 +
795 + switch (port->phydev->speed) {
796 + case SPEED_1000:
797 + phyaddr |= MDIO_PHY_SPEED_G1;
798 + miirate = MII_CFG_RATE_M125;
799 + break;
800 +
801 + case SPEED_100:
802 + phyaddr |= MDIO_PHY_SPEED_M100;
803 + switch (miimode) {
804 + case MII_CFG_MODE_RMIIM:
805 + case MII_CFG_MODE_RMIIP:
806 + miirate = MII_CFG_RATE_M50;
807 + break;
808 + default:
809 + miirate = MII_CFG_RATE_M25;
810 + break;
811 + }
812 + break;
813 +
814 + default:
815 + phyaddr |= MDIO_PHY_SPEED_M10;
816 + miirate = MII_CFG_RATE_M2P5;
817 + break;
818 + }
819 +
820 + if (port->phydev->link)
821 + phyaddr |= MDIO_PHY_LINK_UP;
822 + else
823 + phyaddr |= MDIO_PHY_LINK_DOWN;
824 +
825 + if (port->phydev->duplex == DUPLEX_FULL)
826 + phyaddr |= MDIO_PHY_FDUP_EN;
827 + else
828 + phyaddr |= MDIO_PHY_FDUP_DIS;
829 +
830 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
831 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
832 + udelay(1);
833 +}
834 +#else
835 +static void xrx200_gmac_update(struct xrx200_port *port)
836 +{
837 +
838 +}
839 +#endif
840 +
841 +static void xrx200_mdio_link(struct net_device *dev)
842 +{
843 + struct xrx200_priv *priv = netdev_priv(dev);
844 + int i;
845 +
846 + for (i = 0; i < priv->num_port; i++) {
847 + if (!priv->port[i].phydev)
848 + continue;
849 +
850 + if (priv->port[i].link != priv->port[i].phydev->link) {
851 + xrx200_gmac_update(&priv->port[i]);
852 + priv->port[i].link = priv->port[i].phydev->link;
853 + netdev_info(dev, "port %d %s link\n",
854 + priv->port[i].num,
855 + (priv->port[i].link)?("got"):("lost"));
856 + }
857 + }
858 +}
859 +
860 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
861 +{
862 + unsigned cnt = 10000;
863 +
864 + while (likely(cnt--)) {
865 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
866 + if ((ctrl & MDIO_BUSY) == 0)
867 + return 0;
868 + }
869 +
870 + return 1;
871 +}
872 +
873 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
874 +{
875 + if (xrx200_mdio_poll(bus))
876 + return 1;
877 +
878 + ltq_mdio_w32(val, MDIO_WRITE);
879 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
880 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
881 + (reg & MDIO_MASK),
882 + MDIO_CTRL);
883 +
884 + return 0;
885 +}
886 +
887 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
888 +{
889 + if (xrx200_mdio_poll(bus))
890 + return -1;
891 +
892 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
893 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
894 + (reg & MDIO_MASK),
895 + MDIO_CTRL);
896 +
897 + if (xrx200_mdio_poll(bus))
898 + return -1;
899 +
900 + return ltq_mdio_r32(MDIO_READ);
901 +}
902 +
903 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
904 +{
905 + struct xrx200_priv *priv = netdev_priv(dev);
906 + struct phy_device *phydev = NULL;
907 + unsigned val;
908 +
909 + phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
910 +
911 + if (!phydev) {
912 + netdev_err(dev, "no PHY found\n");
913 + return -ENODEV;
914 + }
915 +
916 + phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
917 + port->phy_if);
918 +
919 + if (IS_ERR(phydev)) {
920 + netdev_err(dev, "Could not attach to PHY\n");
921 + return PTR_ERR(phydev);
922 + }
923 +
924 + phydev->supported &= (SUPPORTED_10baseT_Half
925 + | SUPPORTED_10baseT_Full
926 + | SUPPORTED_100baseT_Half
927 + | SUPPORTED_100baseT_Full
928 + | SUPPORTED_1000baseT_Half
929 + | SUPPORTED_1000baseT_Full
930 + | SUPPORTED_Autoneg
931 + | SUPPORTED_MII
932 + | SUPPORTED_TP);
933 + phydev->advertising = phydev->supported;
934 + port->phydev = phydev;
935 +
936 + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
937 + dev->name, phydev->drv->name,
938 + dev_name(&phydev->dev), phydev->irq);
939 +
940 +#ifdef SW_POLLING
941 + phy_read_status(phydev);
942 +
943 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
944 + val |= ADVERTIZE_MPD;
945 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
946 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
947 +
948 + phy_start_aneg(phydev);
949 +#endif
950 + return 0;
951 +}
952 +
953 +static void xrx200_port_config(struct xrx200_priv *priv,
954 + const struct xrx200_port *port)
955 +{
956 + u16 miimode = 0;
957 +
958 + switch (port->num) {
959 + case 0: /* xMII0 */
960 + case 1: /* xMII1 */
961 + switch (port->phy_if) {
962 + case PHY_INTERFACE_MODE_MII:
963 + if (port->flags & XRX200_PORT_TYPE_PHY)
964 + /* MII MAC mode, connected to external PHY */
965 + miimode = MII_CFG_MODE_MIIM;
966 + else
967 + /* MII PHY mode, connected to external MAC */
968 + miimode = MII_CFG_MODE_MIIP;
969 + break;
970 + case PHY_INTERFACE_MODE_RMII:
971 + if (port->flags & XRX200_PORT_TYPE_PHY)
972 + /* RMII MAC mode, connected to external PHY */
973 + miimode = MII_CFG_MODE_RMIIM;
974 + else
975 + /* RMII PHY mode, connected to external MAC */
976 + miimode = MII_CFG_MODE_RMIIP;
977 + break;
978 + case PHY_INTERFACE_MODE_RGMII:
979 + /* RGMII MAC mode, connected to external PHY */
980 + miimode = MII_CFG_MODE_RGMII;
981 + break;
982 + default:
983 + break;
984 + }
985 + break;
986 + case 2: /* internal GPHY0 */
987 + case 3: /* internal GPHY0 */
988 + case 4: /* internal GPHY1 */
989 + switch (port->phy_if) {
990 + case PHY_INTERFACE_MODE_MII:
991 + case PHY_INTERFACE_MODE_GMII:
992 + /* MII MAC mode, connected to internal GPHY */
993 + miimode = MII_CFG_MODE_MIIM;
994 + break;
995 + default:
996 + break;
997 + }
998 + break;
999 + case 5: /* internal GPHY1 or xMII2 */
1000 + switch (port->phy_if) {
1001 + case PHY_INTERFACE_MODE_MII:
1002 + /* MII MAC mode, connected to internal GPHY */
1003 + miimode = MII_CFG_MODE_MIIM;
1004 + break;
1005 + case PHY_INTERFACE_MODE_RGMII:
1006 + /* RGMII MAC mode, connected to external PHY */
1007 + miimode = MII_CFG_MODE_RGMII;
1008 + break;
1009 + default:
1010 + break;
1011 + }
1012 + break;
1013 + default:
1014 + break;
1015 + }
1016 +
1017 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1018 + MII_CFG(port->num));
1019 +}
1020 +
1021 +static int xrx200_init(struct net_device *dev)
1022 +{
1023 + struct xrx200_priv *priv = netdev_priv(dev);
1024 + struct sockaddr mac;
1025 + int err, i;
1026 +
1027 +#ifndef SW_POLLING
1028 + unsigned int reg = 0;
1029 +
1030 + /* enable auto polling */
1031 + for (i = 0; i < priv->num_port; i++)
1032 + reg |= BIT(priv->port[i].num);
1033 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1034 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1035 +#endif
1036 +
1037 + /* setup each port */
1038 + for (i = 0; i < priv->num_port; i++)
1039 + xrx200_port_config(priv, &priv->port[i]);
1040 +
1041 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1042 + if (!is_valid_ether_addr(mac.sa_data)) {
1043 + pr_warn("net-xrx200: invalid MAC, using random\n");
1044 + eth_random_addr(mac.sa_data);
1045 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1046 + }
1047 +
1048 + err = eth_mac_addr(dev, &mac);
1049 + if (err)
1050 + goto err_netdev;
1051 +
1052 + for (i = 0; i < priv->num_port; i++)
1053 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1054 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1055 + priv->port[i].num);
1056 +
1057 + return 0;
1058 +
1059 +err_netdev:
1060 + unregister_netdev(dev);
1061 + free_netdev(dev);
1062 + return err;
1063 +}
1064 +
1065 +static void xrx200_pci_microcode(void)
1066 +{
1067 + int i;
1068 +
1069 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1070 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1071 + ltq_switch_w32(0, PCE_TBL_MASK);
1072 +
1073 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1074 + ltq_switch_w32(i, PCE_TBL_ADDR);
1075 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1076 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1077 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1078 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1079 +
1080 + // start the table access:
1081 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1082 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1083 + }
1084 +
1085 + /* tell the switch that the microcode is loaded */
1086 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1087 +}
1088 +
1089 +static void xrx200_hw_init(struct xrx200_hw *hw)
1090 +{
1091 + int i;
1092 +
1093 + /* enable clock gate */
1094 + clk_enable(hw->clk);
1095 +
1096 + ltq_switch_w32(1, 0);
1097 + mdelay(100);
1098 + ltq_switch_w32(0, 0);
1099 + /*
1100 + * TODO: we should really disbale all phys/miis here and explicitly
1101 + * enable them in the device secific init function
1102 + */
1103 +
1104 + /* disable port fetch/store dma */
1105 + for (i = 0; i < 7; i++ ) {
1106 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1107 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1108 + }
1109 +
1110 + /* enable Switch */
1111 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1112 +
1113 + /* load the pce microcode */
1114 + xrx200_pci_microcode();
1115 +
1116 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1117 + ltq_switch_w32(0x7f, PCE_PMAP1);
1118 + ltq_switch_w32(0x7f, PCE_PMAP2);
1119 + ltq_switch_w32(0x7f, PCE_PMAP3);
1120 +
1121 + /* RMON Counter Enable for all physical ports */
1122 + for (i = 0; i < 7; i++)
1123 + ltq_switch_w32(0x1, BM_PCFG(i));
1124 +
1125 + /* disable auto polling */
1126 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1127 +
1128 + /* enable port statistic counters */
1129 + for (i = 0; i < 7; i++)
1130 + ltq_switch_w32(0x1, BM_PCFGx(i));
1131 +
1132 + /* set IPG to 12 */
1133 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1134 +
1135 +#ifdef SW_ROUTING
1136 + /* enable status header, enable CRC */
1137 + ltq_pmac_w32_mask(0,
1138 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
1139 + PMAC_HD_CTL);
1140 +#else
1141 + /* disable status header, enable CRC */
1142 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1143 + PMAC_HD_CTL_AC,
1144 + PMAC_HD_CTL);
1145 +#endif
1146 +
1147 + /* enable port fetch/store dma */
1148 + for (i = 0; i < 7; i++ ) {
1149 + ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
1150 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1151 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1152 + }
1153 +
1154 + /* enable special tag insertion on cpu port */
1155 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1156 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1157 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1158 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1159 +}
1160 +
1161 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1162 +{
1163 + int i;
1164 +
1165 + /* disable the switch */
1166 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1167 +
1168 + /* free the channels and IRQs */
1169 + for (i = 0; i < 2; i++) {
1170 + ltq_dma_free(&hw->chan[i].dma);
1171 + if (hw->chan[i].dma.irq)
1172 + free_irq(hw->chan[i].dma.irq, hw);
1173 + }
1174 +
1175 + /* free the allocated RX ring */
1176 + for (i = 0; i < LTQ_DESC_NUM; i++)
1177 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1178 +
1179 + /* clear the mdio bus */
1180 + mdiobus_unregister(hw->mii_bus);
1181 + mdiobus_free(hw->mii_bus);
1182 +
1183 + /* release the clock */
1184 + clk_disable(hw->clk);
1185 + clk_put(hw->clk);
1186 +}
1187 +
1188 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1189 +{
1190 + hw->mii_bus = mdiobus_alloc();
1191 + if (!hw->mii_bus)
1192 + return -ENOMEM;
1193 +
1194 + hw->mii_bus->read = xrx200_mdio_rd;
1195 + hw->mii_bus->write = xrx200_mdio_wr;
1196 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1197 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1198 +
1199 + if (of_mdiobus_register(hw->mii_bus, np)) {
1200 + mdiobus_free(hw->mii_bus);
1201 + return -ENXIO;
1202 + }
1203 +
1204 + return 0;
1205 +}
1206 +
1207 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1208 +{
1209 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1210 + struct xrx200_port *p = &priv->port[priv->num_port];
1211 +
1212 + if (!id)
1213 + return;
1214 +
1215 + memset(p, 0, sizeof(struct xrx200_port));
1216 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1217 + addr = of_get_property(p->phy_node, "reg", NULL);
1218 + if (!addr)
1219 + return;
1220 +
1221 + p->num = *id;
1222 + p->phy_addr = *addr;
1223 + p->phy_if = of_get_phy_mode(port);
1224 + if (p->phy_addr > 0x10)
1225 + p->flags = XRX200_PORT_TYPE_MAC;
1226 + else
1227 + p->flags = XRX200_PORT_TYPE_PHY;
1228 + priv->num_port++;
1229 +
1230 + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
1231 + if (gpio_is_valid(p->gpio))
1232 + if (!gpio_request(p->gpio, "phy-reset")) {
1233 + gpio_direction_output(p->gpio,
1234 + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
1235 + udelay(100);
1236 + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
1237 + }
1238 + /* is this port a wan port ? */
1239 + if (priv->wan)
1240 + priv->hw->wan_map |= BIT(p->num);
1241 +
1242 + priv->port_map |= BIT(p->num);
1243 +
1244 + /* store the port id in the hw struct so we can map ports -> devices */
1245 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1246 +}
1247 +
1248 +static const struct net_device_ops xrx200_netdev_ops = {
1249 + .ndo_init = xrx200_init,
1250 + .ndo_open = xrx200_open,
1251 + .ndo_stop = xrx200_close,
1252 + .ndo_start_xmit = xrx200_start_xmit,
1253 + .ndo_set_mac_address = eth_mac_addr,
1254 + .ndo_validate_addr = eth_validate_addr,
1255 + .ndo_change_mtu = eth_change_mtu,
1256 + .ndo_get_stats = xrx200_get_stats,
1257 + .ndo_tx_timeout = xrx200_tx_timeout,
1258 +};
1259 +
1260 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
1261 +{
1262 + struct xrx200_priv *priv;
1263 + struct device_node *port;
1264 + const __be32 *wan;
1265 +
1266 + /* alloc the network device */
1267 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1268 + if (!hw->devs[hw->num_devs])
1269 + return;
1270 +
1271 + /* setup the network device */
1272 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1273 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1274 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1275 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1276 +
1277 + /* setup our private data */
1278 + priv = netdev_priv(hw->devs[hw->num_devs]);
1279 + priv->hw = hw;
1280 + of_get_mac_address_mtd(iface, priv->mac);
1281 + priv->id = hw->num_devs;
1282 +
1283 + /* is this the wan interface ? */
1284 + wan = of_get_property(iface, "lantiq,wan", NULL);
1285 + if (wan && (*wan == 1))
1286 + priv->wan = 1;
1287 +
1288 + /* load the ports that are part of the interface */
1289 + for_each_child_of_node(iface, port)
1290 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1291 + xrx200_of_port(priv, port);
1292 +
1293 + /* register the actual device */
1294 + if (!register_netdev(hw->devs[hw->num_devs]))
1295 + hw->num_devs++;
1296 +}
1297 +
1298 +static struct xrx200_hw xrx200_hw;
1299 +
1300 +static int xrx200_probe(struct platform_device *pdev)
1301 +{
1302 + struct resource *res[4];
1303 + struct device_node *mdio_np, *iface_np;
1304 + int i;
1305 +
1306 + /* load the memory ranges */
1307 + for (i = 0; i < 4; i++) {
1308 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
1309 + if (!res[i]) {
1310 + dev_err(&pdev->dev, "failed to get resources\n");
1311 + return -ENOENT;
1312 + }
1313 + }
1314 + xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
1315 + xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
1316 + xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
1317 + xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
1318 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
1319 + !xrx200_mii_membase || !xrx200_pmac_membase) {
1320 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
1321 + return -ENOMEM;
1322 + }
1323 +
1324 + /* get the clock */
1325 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
1326 + if (IS_ERR(xrx200_hw.clk)) {
1327 + dev_err(&pdev->dev, "failed to get clock\n");
1328 + return PTR_ERR(xrx200_hw.clk);
1329 + }
1330 +
1331 + /* bring up the dma engine and IP core */
1332 + spin_lock_init(&xrx200_hw.lock);
1333 + xrx200_dma_init(&xrx200_hw);
1334 + xrx200_hw_init(&xrx200_hw);
1335 + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw);
1336 +
1337 + /* bring up the mdio bus */
1338 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
1339 + "lantiq,xrx200-mdio");
1340 + if (mdio_np)
1341 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
1342 + dev_err(&pdev->dev, "mdio probe failed\n");
1343 +
1344 + /* load the interfaces */
1345 + for_each_child_of_node(pdev->dev.of_node, iface_np)
1346 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
1347 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
1348 + xrx200_of_iface(&xrx200_hw, iface_np);
1349 + else
1350 + dev_err(&pdev->dev,
1351 + "only %d interfaces allowed\n",
1352 + XRX200_MAX_DEV);
1353 + }
1354 +
1355 + if (!xrx200_hw.num_devs) {
1356 + xrx200_hw_cleanup(&xrx200_hw);
1357 + dev_err(&pdev->dev, "failed to load interfaces\n");
1358 + return -ENOENT;
1359 + }
1360 +
1361 + /* set wan port mask */
1362 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
1363 +
1364 + for (i = 0; i < xrx200_hw.num_devs; i++) {
1365 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
1366 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
1367 + }
1368 +
1369 + /* setup NAPI */
1370 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
1371 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
1372 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
1373 +
1374 + platform_set_drvdata(pdev, &xrx200_hw);
1375 +
1376 + return 0;
1377 +}
1378 +
1379 +static int xrx200_remove(struct platform_device *pdev)
1380 +{
1381 + struct net_device *dev = platform_get_drvdata(pdev);
1382 + struct xrx200_priv *priv;
1383 +
1384 + if (!dev)
1385 + return 0;
1386 +
1387 + priv = netdev_priv(dev);
1388 +
1389 + /* free stack related instances */
1390 + netif_stop_queue(dev);
1391 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
1392 +
1393 + /* shut down hardware */
1394 + xrx200_hw_cleanup(&xrx200_hw);
1395 +
1396 + /* remove the actual device */
1397 + unregister_netdev(dev);
1398 + free_netdev(dev);
1399 +
1400 + return 0;
1401 +}
1402 +
1403 +static const struct of_device_id xrx200_match[] = {
1404 + { .compatible = "lantiq,xrx200-net" },
1405 + {},
1406 +};
1407 +MODULE_DEVICE_TABLE(of, xrx200_match);
1408 +
1409 +static struct platform_driver xrx200_driver = {
1410 + .probe = xrx200_probe,
1411 + .remove = xrx200_remove,
1412 + .driver = {
1413 + .name = "lantiq,xrx200-net",
1414 + .of_match_table = xrx200_match,
1415 + .owner = THIS_MODULE,
1416 + },
1417 +};
1418 +
1419 +module_platform_driver(xrx200_driver);
1420 +
1421 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1422 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
1423 +MODULE_LICENSE("GPL");
1424 --
1425 1.7.10.4
1426
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