lantiq: add v3.10 patches
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.10 / 0021-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
1 From e8c43773eac79f73f2dc4f10abd6d76f88540e91 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 29 Jun 2013 19:42:16 +0200
4 Subject: [PATCH 21/34] NET: MIPS: lantiq: update etop driver for devicetree
5
6 ---
7 drivers/net/ethernet/lantiq_etop.c | 501 +++++++++++++++++++++++++-----------
8 1 file changed, 355 insertions(+), 146 deletions(-)
9
10 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
11 index bfdb0686..cdc0c0e 100644
12 --- a/drivers/net/ethernet/lantiq_etop.c
13 +++ b/drivers/net/ethernet/lantiq_etop.c
14 @@ -12,7 +12,7 @@
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 *
18 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
19 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
20 */
21
22 #include <linux/kernel.h>
23 @@ -36,6 +36,10 @@
24 #include <linux/io.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/module.h>
27 +#include <linux/clk.h>
28 +#include <linux/of_net.h>
29 +#include <linux/of_irq.h>
30 +#include <linux/of_platform.h>
31
32 #include <asm/checksum.h>
33
34 @@ -71,25 +75,61 @@
35 #define ETOP_MII_REVERSE 0xe
36 #define ETOP_PLEN_UNDER 0x40
37 #define ETOP_CGEN 0x800
38 -
39 -/* use 2 static channels for TX/RX */
40 -#define LTQ_ETOP_TX_CHANNEL 1
41 -#define LTQ_ETOP_RX_CHANNEL 6
42 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
43 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
44 -
45 +#define ETOP_CFG_MII0 0x01
46 +
47 +#define LTQ_GBIT_MDIO_CTL 0xCC
48 +#define LTQ_GBIT_MDIO_DATA 0xd0
49 +#define LTQ_GBIT_GCTL0 0x68
50 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
51 +#define LTQ_GBIT_P0_CTL 0x4
52 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
53 +#define LTQ_GBIT_RGMII_CTL 0x78
54 +
55 +#define PMAC_HD_CTL_AS (1 << 19)
56 +#define PMAC_HD_CTL_RXSH (1 << 22)
57 +
58 +/* Switch Enable (0=disable, 1=enable) */
59 +#define GCTL0_SE 0x80000000
60 +/* Disable MDIO auto polling (0=disable, 1=enable) */
61 +#define PX_CTL_DMDIO 0x00400000
62 +
63 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
64 +#define MDC_CLOCK_MASK 0xff000000
65 +#define MDC_CLOCK_OFFSET 24
66 +
67 +/* register information for the gbit's MDIO bus */
68 +#define MDIO_XR9_REQUEST 0x00008000
69 +#define MDIO_XR9_READ 0x00000800
70 +#define MDIO_XR9_WRITE 0x00000400
71 +#define MDIO_XR9_REG_MASK 0x1f
72 +#define MDIO_XR9_ADDR_MASK 0x1f
73 +#define MDIO_XR9_RD_MASK 0xffff
74 +#define MDIO_XR9_REG_OFFSET 0
75 +#define MDIO_XR9_ADDR_OFFSET 5
76 +#define MDIO_XR9_WR_OFFSET 16
77 +
78 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
79 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
80 +
81 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
82 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
83 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
84 #define ltq_etop_w32_mask(x, y, z) \
85 ltq_w32_mask(x, y, ltq_etop_membase + (z))
86
87 -#define DRV_VERSION "1.0"
88 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
89 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
90 +#define ltq_gbit_w32_mask(x, y, z) \
91 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
92 +
93 +#define DRV_VERSION "1.2"
94
95 static void __iomem *ltq_etop_membase;
96 +static void __iomem *ltq_gbit_membase;
97
98 struct ltq_etop_chan {
99 - int idx;
100 int tx_free;
101 + int irq;
102 struct net_device *netdev;
103 struct napi_struct napi;
104 struct ltq_dma_channel dma;
105 @@ -99,22 +139,35 @@ struct ltq_etop_chan {
106 struct ltq_etop_priv {
107 struct net_device *netdev;
108 struct platform_device *pdev;
109 - struct ltq_eth_data *pldata;
110 struct resource *res;
111
112 struct mii_bus *mii_bus;
113 struct phy_device *phydev;
114
115 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
116 - int tx_free[MAX_DMA_CHAN >> 1];
117 + struct ltq_etop_chan txch;
118 + struct ltq_etop_chan rxch;
119 +
120 + int tx_irq;
121 + int rx_irq;
122 +
123 + const void *mac;
124 + int mii_mode;
125
126 spinlock_t lock;
127 +
128 + struct clk *clk_ppe;
129 + struct clk *clk_switch;
130 + struct clk *clk_ephy;
131 + struct clk *clk_ephycgu;
132 };
133
134 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
135 + int phy_reg, u16 phy_data);
136 +
137 static int
138 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
139 {
140 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
141 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
142 if (!ch->skb[ch->dma.desc])
143 return -ENOMEM;
144 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
145 @@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
146 spin_unlock_irqrestore(&priv->lock, flags);
147
148 skb_put(skb, len);
149 + skb->dev = ch->netdev;
150 skb->protocol = eth_type_trans(skb, ch->netdev);
151 netif_receive_skb(skb);
152 + ch->netdev->stats.rx_packets++;
153 + ch->netdev->stats.rx_bytes += len;
154 }
155
156 static int
157 @@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
158 {
159 struct ltq_etop_chan *ch = container_of(napi,
160 struct ltq_etop_chan, napi);
161 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
162 int rx = 0;
163 int complete = 0;
164 + unsigned long flags;
165
166 while ((rx < budget) && !complete) {
167 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
168 @@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
169 }
170 if (complete || !rx) {
171 napi_complete(&ch->napi);
172 + spin_lock_irqsave(&priv->lock, flags);
173 ltq_dma_ack_irq(&ch->dma);
174 + spin_unlock_irqrestore(&priv->lock, flags);
175 }
176 return rx;
177 }
178 @@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
179 container_of(napi, struct ltq_etop_chan, napi);
180 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
181 struct netdev_queue *txq =
182 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
183 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
184 unsigned long flags;
185
186 spin_lock_irqsave(&priv->lock, flags);
187 while ((ch->dma.desc_base[ch->tx_free].ctl &
188 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
189 + ch->netdev->stats.tx_packets++;
190 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
191 dev_kfree_skb_any(ch->skb[ch->tx_free]);
192 ch->skb[ch->tx_free] = NULL;
193 memset(&ch->dma.desc_base[ch->tx_free], 0,
194 @@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
195 if (netif_tx_queue_stopped(txq))
196 netif_tx_start_queue(txq);
197 napi_complete(&ch->napi);
198 + spin_lock_irqsave(&priv->lock, flags);
199 ltq_dma_ack_irq(&ch->dma);
200 + spin_unlock_irqrestore(&priv->lock, flags);
201 return 1;
202 }
203
204 @@ -211,9 +275,10 @@ static irqreturn_t
205 ltq_etop_dma_irq(int irq, void *_priv)
206 {
207 struct ltq_etop_priv *priv = _priv;
208 - int ch = irq - LTQ_DMA_CH0_INT;
209 -
210 - napi_schedule(&priv->ch[ch].napi);
211 + if (irq == priv->txch.dma.irq)
212 + napi_schedule(&priv->txch.napi);
213 + else
214 + napi_schedule(&priv->rxch.napi);
215 return IRQ_HANDLED;
216 }
217
218 @@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
219 ltq_dma_free(&ch->dma);
220 if (ch->dma.irq)
221 free_irq(ch->dma.irq, priv);
222 - if (IS_RX(ch->idx)) {
223 + if (ch == &priv->txch) {
224 int desc;
225 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
226 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
227 @@ -236,23 +301,62 @@ static void
228 ltq_etop_hw_exit(struct net_device *dev)
229 {
230 struct ltq_etop_priv *priv = netdev_priv(dev);
231 - int i;
232
233 - ltq_pmu_disable(PMU_PPE);
234 - for (i = 0; i < MAX_DMA_CHAN; i++)
235 - if (IS_TX(i) || IS_RX(i))
236 - ltq_etop_free_channel(dev, &priv->ch[i]);
237 + clk_disable(priv->clk_ppe);
238 +
239 + if (of_machine_is_compatible("lantiq,ar9"))
240 + clk_disable(priv->clk_switch);
241 +
242 + if (of_machine_is_compatible("lantiq,ase")) {
243 + clk_disable(priv->clk_ephy);
244 + clk_disable(priv->clk_ephycgu);
245 + }
246 +
247 + ltq_etop_free_channel(dev, &priv->txch);
248 + ltq_etop_free_channel(dev, &priv->rxch);
249 +}
250 +
251 +static void
252 +ltq_etop_gbit_init(struct net_device *dev)
253 +{
254 + struct ltq_etop_priv *priv = netdev_priv(dev);
255 +
256 + clk_enable(priv->clk_switch);
257 +
258 + /* enable gbit port0 on the SoC */
259 + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
260 +
261 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
262 + /* disable MDIO auto polling mode */
263 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
264 + /* set 1522 packet size */
265 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
266 + /* disable pmac & dmac headers */
267 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
268 + LTQ_GBIT_PMAC_HD_CTL);
269 + /* Due to traffic halt when burst length 8,
270 + replace default IPG value with 0x3B */
271 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
272 + /* set mdc clock to 2.5 MHz */
273 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
274 + LTQ_GBIT_RGMII_CTL);
275 }
276
277 static int
278 ltq_etop_hw_init(struct net_device *dev)
279 {
280 struct ltq_etop_priv *priv = netdev_priv(dev);
281 - int i;
282 + int mii_mode = priv->mii_mode;
283 +
284 + clk_enable(priv->clk_ppe);
285
286 - ltq_pmu_enable(PMU_PPE);
287 + if (of_machine_is_compatible("lantiq,ar9")) {
288 + ltq_etop_gbit_init(dev);
289 + /* force the etops link to the gbit to MII */
290 + mii_mode = PHY_INTERFACE_MODE_MII;
291 + }
292
293 - switch (priv->pldata->mii_mode) {
294 + switch (mii_mode) {
295 case PHY_INTERFACE_MODE_RMII:
296 ltq_etop_w32_mask(ETOP_MII_MASK,
297 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
298 @@ -264,39 +368,68 @@ ltq_etop_hw_init(struct net_device *dev)
299 break;
300
301 default:
302 + if (of_machine_is_compatible("lantiq,ase")) {
303 + clk_enable(priv->clk_ephy);
304 + /* disable external MII */
305 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
306 + /* enable clock for internal PHY */
307 + clk_enable(priv->clk_ephycgu);
308 + /* we need to write this magic to the internal phy to
309 + make it work */
310 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
311 + pr_info("Selected EPHY mode\n");
312 + break;
313 + }
314 netdev_err(dev, "unknown mii mode %d\n",
315 - priv->pldata->mii_mode);
316 + mii_mode);
317 return -ENOTSUPP;
318 }
319
320 /* enable crc generation */
321 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
322
323 + return 0;
324 +}
325 +
326 +static int
327 +ltq_etop_dma_init(struct net_device *dev)
328 +{
329 + struct ltq_etop_priv *priv = netdev_priv(dev);
330 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
331 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
332 + int err;
333 +
334 ltq_dma_init_port(DMA_PORT_ETOP);
335
336 - for (i = 0; i < MAX_DMA_CHAN; i++) {
337 - int irq = LTQ_DMA_CH0_INT + i;
338 - struct ltq_etop_chan *ch = &priv->ch[i];
339 -
340 - ch->idx = ch->dma.nr = i;
341 -
342 - if (IS_TX(i)) {
343 - ltq_dma_alloc_tx(&ch->dma);
344 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
345 - "etop_tx", priv);
346 - } else if (IS_RX(i)) {
347 - ltq_dma_alloc_rx(&ch->dma);
348 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
349 - ch->dma.desc++)
350 - if (ltq_etop_alloc_skb(ch))
351 - return -ENOMEM;
352 - ch->dma.desc = 0;
353 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
354 - "etop_rx", priv);
355 + priv->txch.dma.nr = tx;
356 + ltq_dma_alloc_tx(&priv->txch.dma);
357 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
358 + "eth_tx", priv);
359 + if (err) {
360 + netdev_err(dev, "failed to allocate tx irq\n");
361 + goto err_out;
362 + }
363 + priv->txch.dma.irq = priv->tx_irq;
364 +
365 + priv->rxch.dma.nr = rx;
366 + ltq_dma_alloc_rx(&priv->rxch.dma);
367 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
368 + priv->rxch.dma.desc++) {
369 + if (ltq_etop_alloc_skb(&priv->rxch)) {
370 + netdev_err(dev, "failed to allocate skbs\n");
371 + err = -ENOMEM;
372 + goto err_out;
373 }
374 - ch->dma.irq = irq;
375 }
376 - return 0;
377 + priv->rxch.dma.desc = 0;
378 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
379 + "eth_rx", priv);
380 + if (err)
381 + netdev_err(dev, "failed to allocate rx irq\n");
382 + else
383 + priv->rxch.dma.irq = priv->rx_irq;
384 +err_out:
385 + return err;
386 }
387
388 static void
389 @@ -312,7 +445,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
390 {
391 struct ltq_etop_priv *priv = netdev_priv(dev);
392
393 - return phy_ethtool_gset(priv->phydev, cmd);
394 + if (priv->phydev)
395 + return phy_ethtool_gset(priv->phydev, cmd);
396 + else
397 + return 0;
398 }
399
400 static int
401 @@ -320,7 +456,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
402 {
403 struct ltq_etop_priv *priv = netdev_priv(dev);
404
405 - return phy_ethtool_sset(priv->phydev, cmd);
406 + if (priv->phydev)
407 + return phy_ethtool_sset(priv->phydev, cmd);
408 + else
409 + return 0;
410 }
411
412 static int
413 @@ -328,7 +467,10 @@ ltq_etop_nway_reset(struct net_device *dev)
414 {
415 struct ltq_etop_priv *priv = netdev_priv(dev);
416
417 - return phy_start_aneg(priv->phydev);
418 + if (priv->phydev)
419 + return phy_start_aneg(priv->phydev);
420 + else
421 + return 0;
422 }
423
424 static const struct ethtool_ops ltq_etop_ethtool_ops = {
425 @@ -339,6 +481,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
426 };
427
428 static int
429 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
430 + int phy_reg, u16 phy_data)
431 +{
432 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
433 + (phy_data << MDIO_XR9_WR_OFFSET) |
434 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
435 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
436 +
437 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
438 + ;
439 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
440 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
441 + ;
442 + return 0;
443 +}
444 +
445 +static int
446 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
447 +{
448 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
449 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
450 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
451 +
452 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
453 + ;
454 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
455 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
456 + ;
457 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
458 + return val;
459 +}
460 +
461 +static int
462 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
463 {
464 u32 val = MDIO_REQUEST |
465 @@ -379,14 +554,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
466 {
467 struct ltq_etop_priv *priv = netdev_priv(dev);
468 struct phy_device *phydev = NULL;
469 - int phy_addr;
470 -
471 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
472 - if (priv->mii_bus->phy_map[phy_addr]) {
473 - phydev = priv->mii_bus->phy_map[phy_addr];
474 - break;
475 - }
476 - }
477 + u32 phy_supported = (SUPPORTED_10baseT_Half
478 + | SUPPORTED_10baseT_Full
479 + | SUPPORTED_100baseT_Half
480 + | SUPPORTED_100baseT_Full
481 + | SUPPORTED_Autoneg
482 + | SUPPORTED_MII
483 + | SUPPORTED_TP);
484 +
485 + if (of_machine_is_compatible("lantiq,ase"))
486 + phydev = priv->mii_bus->phy_map[8];
487 + else
488 + phydev = priv->mii_bus->phy_map[0];
489
490 if (!phydev) {
491 netdev_err(dev, "no PHY found\n");
492 @@ -394,21 +573,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
493 }
494
495 phydev = phy_connect(dev, dev_name(&phydev->dev),
496 - &ltq_etop_mdio_link, priv->pldata->mii_mode);
497 + &ltq_etop_mdio_link, priv->mii_mode);
498
499 if (IS_ERR(phydev)) {
500 netdev_err(dev, "Could not attach to PHY\n");
501 return PTR_ERR(phydev);
502 }
503
504 - phydev->supported &= (SUPPORTED_10baseT_Half
505 - | SUPPORTED_10baseT_Full
506 - | SUPPORTED_100baseT_Half
507 - | SUPPORTED_100baseT_Full
508 - | SUPPORTED_Autoneg
509 - | SUPPORTED_MII
510 - | SUPPORTED_TP);
511 + if (of_machine_is_compatible("lantiq,ar9"))
512 + phy_supported |= SUPPORTED_1000baseT_Half
513 + | SUPPORTED_1000baseT_Full;
514
515 + phydev->supported &= phy_supported;
516 phydev->advertising = phydev->supported;
517 priv->phydev = phydev;
518 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
519 @@ -433,8 +609,13 @@ ltq_etop_mdio_init(struct net_device *dev)
520 }
521
522 priv->mii_bus->priv = dev;
523 - priv->mii_bus->read = ltq_etop_mdio_rd;
524 - priv->mii_bus->write = ltq_etop_mdio_wr;
525 + if (of_machine_is_compatible("lantiq,ar9")) {
526 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
527 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
528 + } else {
529 + priv->mii_bus->read = ltq_etop_mdio_rd;
530 + priv->mii_bus->write = ltq_etop_mdio_wr;
531 + }
532 priv->mii_bus->name = "ltq_mii";
533 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
534 priv->pdev->name, priv->pdev->id);
535 @@ -483,17 +664,19 @@ static int
536 ltq_etop_open(struct net_device *dev)
537 {
538 struct ltq_etop_priv *priv = netdev_priv(dev);
539 - int i;
540 + unsigned long flags;
541
542 - for (i = 0; i < MAX_DMA_CHAN; i++) {
543 - struct ltq_etop_chan *ch = &priv->ch[i];
544 + napi_enable(&priv->txch.napi);
545 + napi_enable(&priv->rxch.napi);
546 +
547 + spin_lock_irqsave(&priv->lock, flags);
548 + ltq_dma_open(&priv->txch.dma);
549 + ltq_dma_open(&priv->rxch.dma);
550 + spin_unlock_irqrestore(&priv->lock, flags);
551 +
552 + if (priv->phydev)
553 + phy_start(priv->phydev);
554
555 - if (!IS_TX(i) && (!IS_RX(i)))
556 - continue;
557 - ltq_dma_open(&ch->dma);
558 - napi_enable(&ch->napi);
559 - }
560 - phy_start(priv->phydev);
561 netif_tx_start_all_queues(dev);
562 return 0;
563 }
564 @@ -502,18 +685,19 @@ static int
565 ltq_etop_stop(struct net_device *dev)
566 {
567 struct ltq_etop_priv *priv = netdev_priv(dev);
568 - int i;
569 + unsigned long flags;
570
571 netif_tx_stop_all_queues(dev);
572 - phy_stop(priv->phydev);
573 - for (i = 0; i < MAX_DMA_CHAN; i++) {
574 - struct ltq_etop_chan *ch = &priv->ch[i];
575 + if (priv->phydev)
576 + phy_stop(priv->phydev);
577 + napi_disable(&priv->txch.napi);
578 + napi_disable(&priv->rxch.napi);
579 +
580 + spin_lock_irqsave(&priv->lock, flags);
581 + ltq_dma_close(&priv->txch.dma);
582 + ltq_dma_close(&priv->rxch.dma);
583 + spin_unlock_irqrestore(&priv->lock, flags);
584
585 - if (!IS_RX(i) && !IS_TX(i))
586 - continue;
587 - napi_disable(&ch->napi);
588 - ltq_dma_close(&ch->dma);
589 - }
590 return 0;
591 }
592
593 @@ -523,16 +707,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
594 int queue = skb_get_queue_mapping(skb);
595 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
596 struct ltq_etop_priv *priv = netdev_priv(dev);
597 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
598 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
599 - int len;
600 + struct ltq_dma_desc *desc =
601 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
602 unsigned long flags;
603 u32 byte_offset;
604 + int len;
605
606 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
607
608 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
609 - dev_kfree_skb_any(skb);
610 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
611 + priv->txch.skb[priv->txch.dma.desc]) {
612 netdev_err(dev, "tx ring full\n");
613 netif_tx_stop_queue(txq);
614 return NETDEV_TX_BUSY;
615 @@ -540,7 +724,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
616
617 /* dma needs to start on a 16 byte aligned address */
618 byte_offset = CPHYSADDR(skb->data) % 16;
619 - ch->skb[ch->dma.desc] = skb;
620 + priv->txch.skb[priv->txch.dma.desc] = skb;
621
622 dev->trans_start = jiffies;
623
624 @@ -550,11 +734,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
625 wmb();
626 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
627 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
628 - ch->dma.desc++;
629 - ch->dma.desc %= LTQ_DESC_NUM;
630 + priv->txch.dma.desc++;
631 + priv->txch.dma.desc %= LTQ_DESC_NUM;
632 spin_unlock_irqrestore(&priv->lock, flags);
633
634 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
635 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
636 netif_tx_stop_queue(txq);
637
638 return NETDEV_TX_OK;
639 @@ -633,34 +817,33 @@ ltq_etop_init(struct net_device *dev)
640 struct ltq_etop_priv *priv = netdev_priv(dev);
641 struct sockaddr mac;
642 int err;
643 - bool random_mac = false;
644
645 ether_setup(dev);
646 dev->watchdog_timeo = 10 * HZ;
647 err = ltq_etop_hw_init(dev);
648 if (err)
649 goto err_hw;
650 + err = ltq_etop_dma_init(dev);
651 + if (err)
652 + goto err_hw;
653 +
654 ltq_etop_change_mtu(dev, 1500);
655
656 - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
657 + if (priv->mac)
658 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
659 if (!is_valid_ether_addr(mac.sa_data)) {
660 pr_warn("etop: invalid MAC, using random\n");
661 - eth_random_addr(mac.sa_data);
662 - random_mac = true;
663 + random_ether_addr(mac.sa_data);
664 }
665
666 err = ltq_etop_set_mac_address(dev, &mac);
667 if (err)
668 goto err_netdev;
669 -
670 - /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
671 - if (random_mac)
672 - dev->addr_assign_type = NET_ADDR_RANDOM;
673 -
674 ltq_etop_set_multicast_list(dev);
675 - err = ltq_etop_mdio_init(dev);
676 - if (err)
677 - goto err_netdev;
678 + if (!ltq_etop_mdio_init(dev))
679 + dev->ethtool_ops = &ltq_etop_ethtool_ops;
680 + else
681 + pr_warn("etop: mdio probe failed\n");;
682 return 0;
683
684 err_netdev:
685 @@ -680,6 +863,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
686 err = ltq_etop_hw_init(dev);
687 if (err)
688 goto err_hw;
689 + err = ltq_etop_dma_init(dev);
690 + if (err)
691 + goto err_hw;
692 dev->trans_start = jiffies;
693 netif_wake_queue(dev);
694 return;
695 @@ -703,14 +889,18 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
696 .ndo_tx_timeout = ltq_etop_tx_timeout,
697 };
698
699 -static int __init
700 -ltq_etop_probe(struct platform_device *pdev)
701 +static int ltq_etop_probe(struct platform_device *pdev)
702 {
703 struct net_device *dev;
704 struct ltq_etop_priv *priv;
705 - struct resource *res;
706 + struct resource *res, *gbit_res, irqres[2];
707 int err;
708 - int i;
709 +
710 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
711 + if (err != 2) {
712 + dev_err(&pdev->dev, "failed to get etop irqs\n");
713 + return -EINVAL;
714 + }
715
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 if (!res) {
718 @@ -736,30 +926,58 @@ ltq_etop_probe(struct platform_device *pdev)
719 goto err_out;
720 }
721
722 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
723 - if (!dev) {
724 - err = -ENOMEM;
725 - goto err_out;
726 + if (of_machine_is_compatible("lantiq,ar9")) {
727 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
728 + if (!gbit_res) {
729 + dev_err(&pdev->dev, "failed to get gbit resource\n");
730 + err = -ENOENT;
731 + goto err_out;
732 + }
733 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
734 + gbit_res->start, resource_size(gbit_res));
735 + if (!ltq_gbit_membase) {
736 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
737 + pdev->id);
738 + err = -ENOMEM;
739 + goto err_out;
740 + }
741 }
742 +
743 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
744 strcpy(dev->name, "eth%d");
745 dev->netdev_ops = &ltq_eth_netdev_ops;
746 - dev->ethtool_ops = &ltq_etop_ethtool_ops;
747 priv = netdev_priv(dev);
748 priv->res = res;
749 priv->pdev = pdev;
750 - priv->pldata = dev_get_platdata(&pdev->dev);
751 priv->netdev = dev;
752 + priv->tx_irq = irqres[0].start;
753 + priv->rx_irq = irqres[1].start;
754 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
755 + of_get_mac_address_mtd(pdev->dev.of_node, priv->mac);
756 +
757 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
758 + if (IS_ERR(priv->clk_ppe))
759 + return PTR_ERR(priv->clk_ppe);
760 + if (of_machine_is_compatible("lantiq,ar9")) {
761 + priv->clk_switch = clk_get(&pdev->dev, "switch");
762 + if (IS_ERR(priv->clk_switch))
763 + return PTR_ERR(priv->clk_switch);
764 + }
765 + if (of_machine_is_compatible("lantiq,ase")) {
766 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
767 + if (IS_ERR(priv->clk_ephy))
768 + return PTR_ERR(priv->clk_ephy);
769 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
770 + if (IS_ERR(priv->clk_ephycgu))
771 + return PTR_ERR(priv->clk_ephycgu);
772 + }
773 +
774 spin_lock_init(&priv->lock);
775
776 - for (i = 0; i < MAX_DMA_CHAN; i++) {
777 - if (IS_TX(i))
778 - netif_napi_add(dev, &priv->ch[i].napi,
779 - ltq_etop_poll_tx, 8);
780 - else if (IS_RX(i))
781 - netif_napi_add(dev, &priv->ch[i].napi,
782 - ltq_etop_poll_rx, 32);
783 - priv->ch[i].netdev = dev;
784 - }
785 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
786 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
787 + priv->txch.netdev = dev;
788 + priv->rxch.netdev = dev;
789
790 err = register_netdev(dev);
791 if (err)
792 @@ -788,32 +1006,23 @@ ltq_etop_remove(struct platform_device *pdev)
793 return 0;
794 }
795
796 +static const struct of_device_id ltq_etop_match[] = {
797 + { .compatible = "lantiq,etop-xway" },
798 + {},
799 +};
800 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
801 +
802 static struct platform_driver ltq_mii_driver = {
803 + .probe = ltq_etop_probe,
804 .remove = ltq_etop_remove,
805 .driver = {
806 .name = "ltq_etop",
807 .owner = THIS_MODULE,
808 + .of_match_table = ltq_etop_match,
809 },
810 };
811
812 -int __init
813 -init_ltq_etop(void)
814 -{
815 - int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
816 -
817 - if (ret)
818 - pr_err("ltq_etop: Error registering platform driver!");
819 - return ret;
820 -}
821 -
822 -static void __exit
823 -exit_ltq_etop(void)
824 -{
825 - platform_driver_unregister(&ltq_mii_driver);
826 -}
827 -
828 -module_init(init_ltq_etop);
829 -module_exit(exit_ltq_etop);
830 +module_platform_driver(ltq_mii_driver);
831
832 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
833 MODULE_DESCRIPTION("Lantiq SoC ETOP");
834 --
835 1.7.10.4
836